Scope and Limit of Lithography to the End of Moore s Law

Transcription

1 Scope and Limit of Lithography to the End of Moore s Law Burn J. Lin tsmc, Inc. 1

2 What dictate the end of Moore s Law Economy Device limits Lithography limits 2

3 Litho Requirement of Critical Layers Logic Node (nm) Poly Half Pitch (nm) CD Uniformity (nm) Overlay Accuracy (nm) These are generic technology nodes that have no correlation to TSMC nodes 3

4 Pushing the Limits of Lithography Pitch splitting with ArF water immersion Further wavelength reduction to EUV Multiple E-Beam Maskless lithography 4

5 Resolution of Tools from ArF to MEB λ NA nλ DOF = k3 NHA2 MFS = k1 5

6 Multiple Patterning Double patterning => L + E + L + E = 2L2E Triple patterning => 3L3E Multiple patterning can be used for Pitch splitting Pattern trimming Spacers 6

7 Split Pitch with Line-End Cutting Mask B Mask A Mask C Active Cut 7

8 Contact Pitch Splitting C A Watch out for G-rule violation Mask 1 B Mask 2 8

9 Multiple Patterning in ArF Immersion Logic Node Poly Half Pitch (nm) Contact Half Pitch (nm) Metal Half Pitch (nm) Immersion k1 for Poly Immersion k1 for Contact Immersion k1 for Metal Multiple Patterning Immersion k1 for Poly Immersion k1 for Contact Immersion k1 for Metal 32nm 22nm 16nm 11nm 8nm

10 Pushing the Limits of Lithography Pitch splitting Cost Multiple E-Beam Maskless lithography Design rule restriction Processing complexity Requirement of overlay accuracy Further wavelength reduction EUV 10

11 EUV Lithography 11

12 k1 of EUVL Node NA EUV k1 for Poly EUV k1 for Contact EUV k1 for Metal 22nm nm nm nm

13 EUV Lithography APPEALS Wavelength=13.5 nm 7% of 193 nm 10% of 134 nm For 22-nm half pitch at 1.35NA and 193-nm wavelength, k1=0.15. Same half pitch at 0.25NA and 13.5-nm wavelength, k1=0.52. Ample DOF Simpler OPC intuitively Evolutional mask writing CHALLENGES Laser power/resist sensitivity/ LWR impasse Stringent mask spec. Absence of pellicle Mask inspection and repair Atomic-precision optics Stray light(lens flare) Contamination and life time of optical elements Cost 13

14 Comparison of LPP and DPP Sources Need >400W for HVM LPP DPP No hardware close to plasma One-stage energy conversion No moving part in vacuum Easy 100% duty cycle Good point source Two-stage energy conversion (low efficiency) Need IR filter Large footprint in subfab Difficult debris mitigation Smaller footprint in subfab Does not need IR filter Needs little H2 for debris mitigation Difficult thermal management at hardware close to plasma Source shape not as good Difficult to achieve 100% duty cycle High H2 consumption 14

15 Positioning Errors due to Mask Rotation and Translation From M1 Mask a To M6 θ =60 Wafer a' α 2α 2 mα δ x' a' X Xα Off-center tilt 2 mα δ Ztran 2 δ Ztran tanθ δ z' Mask surface misposition 15

16 EUV Mask Flatness Requirement Node 22nm 16nm 11nm 8nm θ (deg) tan(θ ) Mask flatness required (nm)

17 OPC Considerations Uneven flare and shadowing effect require fielddependent OPC. Inter-field flare necessitates dummy exposures at wafer edge. Flare signature if inconsistent between scanners, requires dedicated mask. Flare stability still unknown. 17

18 On Lack of Pellicle Developed reticle box for freedom from contamination during storage, transportation, loading/unloading. Attraction of particulates by the electrostatic mask chucking has to be minimized. Need to block line-of-sight exposure to Sn debris source. Maintain high vacuum. Minimize presence of trace Carbon-containing vapor and H2O vapor. 18

19 EUV Extendibility 19

20 High-NA EUV Design Solutions NA x 0.7 central obscured 6 mirrors unobscured 8 mirrors 27 nm NXE: nm NXE:3300 schematic designs for illustration only. central obscured 11 nm 8 nm W. Kaiser et al., SPIE

21 NA and k1 of Photon Tools Node 22nm 16nm 11nm 8nm Half pitch (nm) ArF λ (nm) water NA k1 immersion EUV at λ (nm) constant NA k1 k1 EUV at λ (nm) diminishing NA k1 k Cannot maintain constant k1 because of Diminishing DOF Expensive NA 21

22 DOF of EUV Node EUV at λ (nm) diminishing NA k1 k1 DOF (k3) Theoretical (nm) Experimental (nm) 22nm nm nm nm DOF determined with common E-D window 0.4:0.6 Resist line : space Allowance for mixed pitches 22

23 13.5nm light may be reaching physical resolution & DOF limits at 11nm Half Pitch or earlier. 23

24 It may reach the economic limit much earlier. 24

25 Multiple E-Beam Maskless Lithography 25

26 Reflective E-Beam Lithography (REBL) Key Features DPG: Dynamic e-beam reflective mask Rotary wafer stage: * Eliminates acceleration/deceleration * Allows multiple columns per stage Conventional 50keV e-beam reduction optics Figure provided by KLA-Tencor 26

27 REBL Source Current Utilization DPG efficiency >50% Aperture 2 : > 90% Aperture 1 : 10% Aperture 3 : 95% REBL EUV ~ 4.4% source current utilization ~ 0.1% from IF to wafer 27

28 Components of DPG Image Placement System DPG Clocking and Print Enable E beam Deflectors and Focus Electronics and Algorithms: WMS system GA C -Several complex subsystems with very tight synchronization -Sophisticated Controls and Signal Processing -High speed Signal Processing (~200MHz) -Sensor fusion algorithms to drive beam deflection Wafer with Patterns Maglev Stage: Various Sensors And Actuators Height Sensor E beam Position Detection System Differential IFM: Master Coordinate System 28

29 Simulation of REBL Imaging 29

30 MAPPER Technology Single electron source split in 13,000 Gaussian beams Vacc = 5 kev Apertures are imaged on substrate through 13,000 micro lenses MEMS-stacked static electric lenses. Optical-switch, CMOS-MEMS blanker array Simple B&W bitmap data through light signal * Infomation from MAPPER Lithography. 30

31 Direct Write Scheme 300 mm wafer Each beam writes 2 µm stripe Electron beam Field 26 mm EO slit EO slit 13,000 beams 150 µm 150 µm 2.25 nm 1 field ~ 26x33mm2 Beam OFF Beam ON Wafer movement 2 um <~ 33 mm (match to scanner field size), then repeat Each beam writes 2µm width by up to 33mm long stripe. 31

32 Multiple E-Beam Maskless Lithography for High Volume Manufacturing HVM clustered production tool: >13,000 beams per chamber (10 WPH) 10 WPH x 5 x 2 = 100 WPH Footprint ~ArF scanner 1m 32

33 PEC Verification Against Immersion Image ArF immersion MAPPER Raster scan 15µC/cm2 P-CAR 45 nm thickness Pixel size 2.25 nm EPC by Double Gaussian model 33

34 Multiple-E-Beam Results 110 beams working Each beam covers a 2x2µm2 block Met CD mean-to-target & CDU spec From 11 randomly selected beams. Data from 110 beams are substantially identical. B.J. Lin, SPIE Proceedings vol. 7379, pp ~11,

35 EPC for MAPPER Pre-α TSMC P72 P81 P90 P122 P180 P360 P1202 Before EPC After EPC 45-nm CAR-P1@ 30 µc/cm2 Proximity 50.0 Proximity error: 12.3 nm before EPC, 8.7 nm after EPC (not yet optimized) DOW (nm) Before Correction After Correction Pitch (nm) 35

36 Challenge in Data Rate and Volume Total pixels in a field (0 & 1 bitmap) = (33mm*26mm) / (2.25nm*2.25nm) * 1.1(10% over scan) = 190 T-bits = 21.2 T-Bytes A 300-mm wafer has ~ 90 fields 20 WPH < 1.8 sec / field 13,000 beams data rate > 7.5 Gbps / beam! In addition to data rate, also challenge in data storage and cost 36

37 11-nm Node Dithering Raster Results 16-nm HP L/S with 0.1-nm EPC layout grid CD accuracy vs NDV (nm) CD accuracy/weef vs NDV (nm) Tot.Blur (nm) Tot.Blur (nm) ) m (n F E /W ry u c a D C ) m (n ry u c a D C NDV (bit/nm (bit/nm ) NDV ) NDV (bit/nm ) NDV (bit/nm2) 2 2 Gray level (bit) /3 Tot.Blur (nm) Tot.Blur (nm) /3 8 it) (b v le y ra G 2) NDV vs Pixel size (bit/nm2) m it/n (b V D N Pixel size (nm) Pixel size (nm) Pixel size (nm) Pixel size (nm) 50% NDV improvement by dithering raster 37

38 Data Path Challenges Memory Bank Data processors Data Beam transmitters modulator (per channel) 3.5 Gbit/s Per channel System size and cost with large amount of memory, processors, and transmitters Main driver is high total raw data bandwidth (e.g. 45 Tbit/s) I/O Bandwidth Wall may limit scaling Power 38

39 Related Presentations Wednesday Influence of Massively Parallel E-Beam Direct Write Pixel Size on Electron Proximity Correction Data path development for multiple electron beam maskless lithography

40 Comparison of EUVL and MEB ML2 40

41 CD Tolerance Considerations CD tol budget Node 22nm 16nm 11nm 8nm Half Pitch (nm) CD (nm) Mask CD tol at 1X (nm) 60% of wafer, MEEF=1.5 Wafer litho CD tol (nm) Wafer non-litho CD tol (nm) % % 3.4% Total EUV CD tol (nm) % Total maskless CD tol (nm) % 41

42 Overlay Considerations Node 22nm 16nm 11nm 8nm CD (nm) Overlay requirement (nm) CD/3 Wafer overlay (nm) single tool Mask edge placement budget (nm) 60% wafer overlay residue Mask flatness contribution allowed (nm) 1/3 of overlay requirement EUV CD contribution to overlay (nm) [CD Tol]/ 2 Maskless CD contribution to overlay (nm) [CD Tol]/ 2 EUV total overlay accuracy (nm) Overlay budget 100% 33.3% 27.3% % % % % % Maskless total overlay accuracy (nm) % 42

43 Defect Considerations MEB EUV Electrostatic chuck if a proprietary non-static chuck is not used Electrostatic chuck Contamination Source debris Wafer processing Mask defects Contamination Wafer processing 43

44 Throughput Loss at Node Advances MEB EUV 2X due to data volume Use next-node datapath 2X due to shot noise Increase source power 2X due to shot noise Increase parallelism or source brightness 2X due to more mirrors for higher NA Increase source power st 2X due to lower current 1 method for higher resolution Increase parallelism ornd 2 method source brightness 3rd method 1st method 44

45 Cost Considerations MEB EUV Strong function of tool price and throughput Strong function of tool price and throughput Datapath Atomic-precision optics High power consumption High power, water, hydrogen consumptions Laser pulse, hydrogen, and collector mirror expenses 45

46 Summary on the Comparison Economy drives 16nm node to EUVL or MEB ML2. EUVL has limited Resolution/MEEF/DOF/Overlay margin for 8nm node. MEB has potential for better CDU and overlay accuracy because of elimination of mask contribution. EUVL needs more source power to compensate for throughput loss per node. MEB needs more parallelism or source brightness to compensate for throughput loss per node. EUVL has higher capital cost and expense. MEB is less developed. 46

47 Litho Decision Tree MEBML2 + CR-DPT Poly CT CT M0 MEBML2 HVM EUVL Feasible yes acceptable CT M0 no End M0 Cost M1 Poly CR-DPT lowest insignificant difference Absolute cost not acceptable Design restriction 47

48 End of Presentation 48