Rad-Hard and Lower RDS(on) Technology for Space Use Power MOSFETs

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1 Rad-Hard and Lower RDS(on) Technology for Space Use Power MOSFETs Masanori INOUE, Humiaki KIRIHATA *) and Satoshi KUBOYAMA **) Fuji Hitachi Power Semiconductor Co., Ltd. *) Fuji Electric Device Technology Co., Ltd. **) JAXA 1

2 Outline Improved SEB Reduction of electric field in a plasma finger Reduction of parasitic npn transistor action Optimization of two step Epi-layers and Δn-length Lower RDS(on) Quasi-Plane Junction Structure Edge Termination with Guard Rings New Products: 100V, 200V, 250V Appearance Target Specification Development Schedule 2

3 Solar Cell Power MOSFETs for Power Supply Quality is our message Load High Efficiency Rad-Hard Lower RDS(on) Trade-off SEB Free 3

4 Improved SEB Reduction of electric field in a plasma finger Reduction of parasitic npn transistor action Optimization of two step Epi-layers and Δn-length 4

5 Normarized RDS(on) Background V Rad-Hard MOSFET New Gen BVDSS [V] 1 st Gen Quality is our message 1 st Generation V SEB /V BR =70% New Generation V SEB /V BR =100% Lower RDS(on) New Gen Rad-Hard Power MOSFETs for Space Use: Lower RDS (on) is realized by breakthrough of RDS(on) vs BVDSS trade-off relationship. 5

6 SEB Mechanism High energy heavy ion irradiation Generation of electron-hole pairs A parasitic npn transistor is operated. The high current density and high electric field generates excess carriers due to a newly found avalanche/tunneling phenomenon near the n - /n + interface. A high-density plasma column is sustained along the ion track. Destruction Reduction of parasitic npn- Tr action Reduction of electric field strength Quality is our message Carrier generation 6

7 Reduction of Electric Field Thick n - base is needed to reduce E. High electric field region Trade-off Lower RDS(on) Solution: Carrier generation region Two step Epi-layers 1 st Epi for BVDSS 2 nd Epi for VSEB 7

8 Reduction of Electric Field Surface Surface st Epi-layer (ρ1, t1) Sub 1 st Epi-layer (ρ1, t1) 2 nd Epi-layer (ρ2, t2) Sub BVDSS or VSEB [V] t1 t2 Total Epi=t1+t2 Measured SEB for single Epi SEB simulation 1st Epi for BVDSS 2nd for VSEB ρ SUB ρ2 ρ Epi Thickness [a.u.] 1 st Epi for BVDSS & Lower RDS(on) 2 nd Epi for VSEB & Lower RDS(on) 8

9 Reduction of Parasitic npn Transistor Action Source (GND) Δn-length heavy Ion Al-Si Gate Lower h fe is needed. P+ + P- n- n+ + n Drain(+) BPSG Poly-Si dipletion layer Solution: Shorter Δn-length Design parameter: 1 p+ window mask size 2 p+ diffusion condition 9

10 SEB Free MOSFET Optimization of two step Epi-layers and Δn-length Quality is our message Ni Ion Energy: [MeV] LET:26.46[MeV/(mg/cm 2 )] Range:46.00[µm] VDS=220V Tow Step Epi-layers Shorter n-length No SEB 1st perk 2nd perk Single Epi No SEB No SEB SEB Collected Charge [pc] SEB free MOSFET is realized. 10

11 Reduction of RDS(on) Quasi-Plane Junction Structure Edge Termination with Guard Rings 11

12 Device Design Quasi-Plane Junction 1 st Generation New Generation Gate Source Gate Source CGD CGD Drain Drain Narrower n - layer Lower RDS(on) Fast switching 12

13 Device Design Edge Termination Quality is our message Conventional: Field Plate BVDSS=0.8xSi_Limit Small active area Surface charge sensitive TD New structure: Guard Ring BVDSS=0.95xSi_Limit Large active area Improved TD Active Area p p Active Area p p p p p p p p p p n- n- n+ n+ D D 13

14 Reduction of RDS(on) New Gen Rad-Hard MOSFET V MOS BVDSS [V] Guard Ring Field Plate TD [Gy] TD Characteristics Normalized RDS(on) V MOS 200V MOS 1 st Gen Rad-Hard 250V MOS New Gen Rad-Hard Silicon Limit General Purpose MOS BVDSS [V] RDS(on) vs BVDSS 14

15 New Products Appearance Target Specification Development Schedule 15

16 Appearance Rad-Hard & Lower RDS(on) MOSFET Chip Package:TO

17 Target Specification 100V Class Company Package Chip Size [a.u.] VDS (V) VGS (V) ID (A) VGS(th) (V) RDS(on) (mω) Fuji TO Fuji --- 1/ Fuji --- 1/ Company A TO V Class Company Package Chip Size [a.u.] VDS (V) VGS (V) ID (A) VGS(th) (V) RDS(on) (mω) Fuji TO Fuji --- 1/ Fuji --- 1/ Company A TO

18 Target Specification 250V Class Company Package Chip Size [a.u.] VDS (V) VGS (V) ID (A) VGS(th) (V) RDS(on) (mω) Fuji TO Fuji --- 1/ Fuji --- 1/ Company A TO

19 Development Schedule Evaluation Samples available... by April 05 QT completion... by March 06 Available in QML... by April 06 19

20 Thank you very mach. Quality is our message Matsumoto Castle Matsumoto, Nagano Pref. 20

Development of n-ch Power MOSFETs (100V to 500V Class) for Space Applications

Development of n-ch Power MOSFETs (100V to 500V Class) for Space Applications Masanori INOUE, Humiaki KIRIHATA, Takashi KOBAYASHI, Naomi IKEDA *), and Satoshi KUBOYAMA *) Fuji Electric Device Technology