Future Challenges and Needs for Nano- Electronics from Manufacturing View Point

Transcription

1 First International Symposium on Nano-manufacturing, April 24-26, 2003 Future Challenges and Needs for Nano- Electronics from Manufacturing View Point Yoshio Nishi Stanford Nanofabrication Facility Department of Electrical Engineering Stanford University Stanford, California

2 Manufacturing To make by hand or esp., by machinery, often on a large scale To work (wool, steel, etc.) into usable form To produce (something) in a way regarded as mechanical To make up (excuse, evidence, etc) Webster's New World Dictionary of the American Language

3 1958: 1st Integrated Circuit Jack S. Kilby

4 1960: First MOSFET by D. Kahng and M. Atalla

5 1959: 1st Planar Integrated Circuit Robert N. Noyce

6 6? m NMOS LSI in 1974 Si substrate Passivation (PSG) Al interconnects ILD (Interlayer Dielectrics) (SiO 2 + BPSG) magnification Field SiO 2 Poly Si gate electrode Gate SiO 2 Source / Drain Layers Si substrate Field oxide Gate oxide Poly Si gate electrode Source/Drain diffusion Interlayer dielectrics Aluminum interconnects Passivation Materials Si, SiO 2 BPSG PSG Al Atoms Si, O, Al, P, B (H, N, Cl)

7 Year of introduction Transistors , , , , , processor , DX processor ,180,000 Pentium processor ,100,000 Pentium II processor ,500,000 Pentium III processor ,000,000 Pentium 4 processor ,000,000

8 Vacuum Transistor IC LSI ULSI Tube 10 cm cm mm 10?m 100 nm 10-1 m 10-2 m 10-3 m 10-5 m 10-7 m In 100 years, the feature size reduced by one million times

9 What conditions made sequential growth of IC manufacturing? Planar technology for precise control of positions in two dimensional plane Ion implantation for vertical control of impurity profiles Film deposition and etching enabling vertical scaling CD control within 10% of minimum geometry Clean technology resulting in defect density control for over 85% yield for 10 9 devices on chip. Every new technology node enabled 30-50% cost reduction per bit or gate over previous node Highly controlled environment for credible statistical data acquisitions

10 Mainframe Moving Power to the Person 1 MIP 10 MIPS 100 MIPS 1000 MIPS Minicomputer Workstation PC Laptop Handheld DSP Systems Enabling Technology 1960 Bipolar TTL Compilers NMOS CISC MPU SC Memory Networks Databases CMOS RISC MPU DSP LAN Graphics Symbolic Computing Submicron CMOS Speech I/O Imaging I/O Global & Mobile Connectivity Visualization Megabit Memories Low-cost DSP Decanano CMOS Ubiquitous Communications Access Mobile Digital Video Virtual Reality Gigabit Memories Super DSP VLIW

11 Microprocessors Trend Past: 1972 (Intel) Lg 10,000 nm Tox 1200 nm f GHz (75 khz) Today: 2002 (Intel) Lg sub-70 nm Tox 1.4 nm f 2.53 GHz P several 10 W Heat Generation 2008 (Intel) Lg sub-25 nm Tox 0.7 nm f 30 GHz P 10 kw N 1.8B 2002? 10W/cm 2 Hot Plate 2006? 100W/cm 2 Nuclear Reactor 2010? 1000W/cm 2 Rocket Nozzle 2016? 10000W/cm 2 Sun Surface P. P. Gelsinger, Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers, Dig. Tech ISSCC, San Francisco, pp.22-23, February, 2001

12 35% 30% % of Semiconductor Revenue PC 25% 20% Communications 15% Estimate In 2000, for the first time, semiconductor revenues in communication exceeded revenues in PC sector. Source: Dataquest

13 Personal Internet Products PDA 2G/2.5G Cellular Phone 3G Cellular Phone I-Video Phone IP Phone Cable Modem DSL Modem Bluetooth Enabled Products Digital Still Camera Digital Camcorder PDA Camera Network Still Camera Home Networking DAB Radio Digital TV Internet Audio Player Digital Video Recorder/Server istb

14 Technology has made systems more personal Minicomputer TTL/Logic PC Microprocessor 1 per Person 1 per Department Internet DSP & Analog MANY per Person! Mainframe Transistors 1 per Company 1960s 1970s 1980s 1990s 2000s 2010s

15 Technology in the Internet Age SOC Integration Strategy for Cell Phones Memory Digital CMOS Analog CMOS Power Mgmt Radio BiCMOS Passives Memory Analog/ Digital Power Mgmt Radio Passives Memory Analog Digital Power Mixed Signal Radio Embedded Non-Volatile Memory Baseband Processor Digital Radio Single Chip Cell Phone Today 200?

16 Technology Innovations for Analog and implications to manufacturing Dennis Buss, 2001 ISSCC Poly resistors: Isolation: Dual-gate CMOS: High-density capacitors: Characterization/modeling: Matching Temperature dependence Non-linearity Noise +1 mask +1 mask +3 masks +1 mask

17 Technology In The Internet Era Analog SOC Integration: #1 Problem Reduced dynamic range: KT/C noise Reduced head room 5 5V 5V 5V High current required for fixed power functions 4 3.3V Low drive current in switches Voltage V 1.8V 1.5V 1.2V 1.0V Gate Length (? m)

18 What does Internet Age imply for silicon-based ICs and Beyond? Moore s Law Scaling principle Law of Economics

19 Moore s Law and Scaling The basic MOSFET structure has not changed, but the structural details and materials have changed for transistor, isolation, and interconnect. Scaling uncovers problems that could be ignored previously. For each generation, available materials and equipment generally set the practical limits (litho is just one example). Improvements in materials and equipment as well as circuit cleverness may permit successful implementation of designs that were previously rejected. 19

20 Lg 30 nm 20 nm 6 nm 3 nm 2 nm 1 nm 0.6 nm Mobile, low cost Low power High performance Production Development (for production) Research (Tr confirmed) Challenge (Unknown ) Ultimate limit

21 Technology Drivers which contributed technology and Manufacturing with Large production volume Strong pull for technology ROI for R&D investment

22 DRAM for most of front-end processings lithography packaging for low cost/small form factor fab engineering High Performance Logic / MPU for transistor performance multi-level interconnect design tools high pin count packaging 22

23 Mobile communication and computing in the Internet Age provide ever increasing challenges, i.e. ultra-low power consumption digital and analog integration including RF cost sensitivity As a new technology driver conflicting requirement for digital and analog for supply voltage on-chip noise management issue 23

24 How far can we go with scaled CMOS for IC manufacturing,i.e. with top down manufacturing methodology?

25 Simplified Cross-Section of MOSFET Transistor Structure Spacer Gate electrode, poly High-k Gate Dielectric Stack L g Upper interfacial region Bulk high-k film Source Si Substrate (or SOI with Si thickness?1/3 L g ) Drain Lower interfacial region P.M. Zeitzoff, R.W. Murto and H.R. Huff, Solid State Technology, July 2002

26 On going efforts to extend the life of silicon based CMOS High K gate stack with metal gate Channel mobility improvement SOI Ultra shallow source and drain junction Low K/Cu for interconnect Continuous shrink with lithography evolutions

27 Ultimate limits? ITRS Roadmap (at introduction) 10 2 Size (? m), Voltage(V) MPU Lg Junction depth Gate oxide thickness Min. V supply Year 10 nm 3 nm 0.3 nm Wave length of electron Direct-tunneling limit in SiO 2 Distance between Si atoms ULTIMATE LIMIT

28 Stated Gate Length (microns) Gate Lengths from IEDM Paper Titles NMOS CMOS SubMicron CMOS DecaNanoElectronics NanoElectronics Super Scaled CMOS Single Electron Devices Nanotubes Resonant Tunneling IEDM Titles IEDM Average 94 SIA & Fit 2001 ITRS MPU Year of Publication (or First Production)

29 High Resolution TEM showing 0.03? m Channel Length Polysilicon Gate Source 1.1nm SiO2 two decades in 10 nm inversion charge electron mean free path Drain 4 layers of Si atoms consumed to create 1.1nm SiO2 4 nm 30 nm Channel Length 78 columns of Si atoms donor atom acceptor atom

30 Needs for Metal Gate Electrodes Elimination of poly silicon depletion for smaller EOT Work function engineering for elimination of channel implant in order to minimize impurity scattering in the channel as well as avoid stochastic fluctuation of the threshold voltage of MOSFET. Needs atomic/molecular level of understandings of interface structure relevant to work function in multi-layer structure

31 Needs for high K dielectrics Larger K without frequency dispersion Minimum channel carrier mobility degradation Allow metal electrode for work function engineering Stable during process integration environment Thickness controllability, Manufacturability

32 Yan et al. (APL 79 [11] 2001) used micro-contact printing of alkylhalosilane self-assembled monolayers on SiO 2 to define ALD-deactivated pattern ZnO ALD of circular dots (T subs = 125?C) Reported near-complete deactivation of SAM-coated oxide surface

33 Needs for smaller geometries 248nm 193nm 157nm Charged beams EUV Nanoimprint/soft imprint Without manufacturing cost increase per gate or bit

34 Amortization of Mask Cost (130-nm) 1000 Cost per Chip [$] E E E E E E+08 Chips Produced A real opportunity for a nano-manufacturing paradigm which is small-lot friendly! Robert Doering, May 12,2002

35 Subset of 2001 ITRS YEAR General lithography (nm) DRAM Memory size (Gb) Chip size (mm 2 ) MPU Gate length, physical/printed (nm) 65/90 37/53 25/35 18/25 13/18 9/13 Equivalent oxide t ox (nm) Gate delay (ps) Transistor/chip (10 6 ) V DD:: High perf Low power (V) Power:High perf Low power (W) Number of wiring levels

36 In fact silicon based CMOS is already in the world of nanoelectronics

37 What s beyond scaling, the world of nanoelectronics? Electrostatic improvement of MOSFET FINFET, Vertical MOS, FDSOI Improvement through materials for MOSFET high K gate, low-k ILD, gate metal work function, higher mobility channel, Ge channel, Schottky S/D New functional materials ferroelectric memory, MRAM, Ovonic/polymer memory, single electron/quantum dots memory Non-silicon 3D solution, nanowire, nanotube MEMS/NEMS integration Optical interconnect/on-chip receiver

38 Will Future Nanoelectronics Technologies Complement or Replace CMOS? Source: 2001 ITRS

39 Double-Gate Transistor Structures Double Gate SOI S G D top gate 100 nm IBM 97 source bottom gate drain S G D Schematic Cross-Section Gate SiO 2 FinFET Simplified view of FinFET (one type of of double-gate double--gate MOSFET) Key advantage: relatively conventional processing, largely compatible with current techniques SiO 2 Source BOX Top View Fin Source Poly Gate SiO 2 Drain Drain T-J. King and C. Hu, UC/Berkeley and Mark Bohr, ECS Meeting PV , Spring, 2001

40 Technology in the Internet Age Embedded Memory Technology Mask Adder to High Perf Logic Process SRAM FLASH DRAM FRAM MRAM OUM Standby Power High NV High NV NV NV Random Access Yes No Yes Yes Yes Yes Area (mm 2 ) for 90 nm node

41 The Ideal MOS Transistor

42 Challenges Facing a Pervasive Replacement of Ultimate Scaled CMOS Cost of less than 0.5 micro-cents per logic gate Greater than 4x10 8 logic gates per cm 2 Greater than minimum-size switches per cm 2 (e.g., SRAM transistors) Cost of less than 50 nano-cents per bit of memory Greater than 30 Gbits of memory per cm 2 Intrinsic switching speed greater than 5 THz Power consumption of less than 6 µw per MOP/sec Reliability of greater than 10 5 hours (~ 10 years) operating lifetime SER of less than a few thousand FITs per Mbit in terrestrial environment Capable of mass production (e.g., > 1 million units /day) Ability to integrate logic, analog, RF, memory (high-speed, high-density, nonvolatile, etc.) Robert Doering, May 12, 2002

43 Opportunity for nano-scale devices Proof of concept Manufacturability demonstrations reproducibility under controlled environment controllability of every parameters, positioning capability with accuracy, Reliability Acceleration mechanism for possible failures based upon thorough understanding of physics and chemistry behind Cost of ownership (COO) competitiveness

44 What conditions made sequential growth of IC manufacturing? Planar technology for precise control of positions in two dimensional plane Ion implantation for vertical control of impurity profiles Film deposition and etching enabling vertical scaling CD control within 10% of minimum geometry Clean technology resulting in defect density control for over 85% yield for 10 9 devices on chip. Every new technology node enabled 30-50% cost reduction per bit or gate over previous node with right technology driver Highly controlled environment for credible statistical data acquisitions

45 New era beyond microelectronics Aggressive introduction of new materials New device structures based upon new materials, as well as new phenomena Research under controlled environment with capability integration New characterization capability coupled with adequate modeling and simulation capability

46 Needs for Paradigm Changes System/architecture level consideration from early stage of device research, Connection between top-down and bottom up approaches Horizontal geometry control, CD and overlay: Limited and costly Should it be horizontal? Vertical geometry control: more precise, e.g. atomic layer deposition Can we build devices vertically? Careful introduction of bottom-up approach?

47 Summary Internet Era drives much more variety of nanoelectronics technology than the previous eras which will serve as system level driver. Silicon-based CMOS technology will remain as the basic platform in the foreseeable future with nanoelectronics devices with new materials and new electrostatic improvements as far as manufacturing cost per function decreases. Top down manufacturing methodology faces tough challenges in terms of further manufacturability improvement New functionality/new devices introduced via nanotechnology/ nanoelectronics will have opportunity if they can be embedded to silicon platform coupled with design paradigm changes. Environment with a variety of materials and processes handling capability coupled with strong characterization capability is a key enabling infrastructure. 47