Single Miller Capacitor Frequency Compensation on Three Stage Amplifier for Large Capacitive Load

Transcription

1 J. Bsic. Appl. Sci. Res., (s6-, 0 0, TextRod Publiction ISSN Journl of Bsic nd Applied Scientific Reserch Sinle Miller Cpcitor Frequency Compenstion on Three Ste Amplifier for Lre Cpcitive Lod Zhr Rnjbr,*, Rhim Ghyour, Hmed Aminzdeh member of Youn Reserchers Club, Fs Brnch, Fs, Irn Interted Systems Lbortory, Electricity enineerin Deprtment, Shirz University, I.R Irn Interted Systems Lbortory, Electricity enineerin Deprtment, Pyme Noor University, I.R. Irn Received: June 0 0 Accepted: July 0 0 ABSTRACT This pper presents the nlysis of sinle Miller compenstion scheme which is used in three-ste opertionl mplifiers. sinle Miller compenstion cpcitor in three-ste mplifiers cn sinificntly reduce the totl cpcitor vlue, nd therefore, the overll re of the mplifiers without influencin their stbility. In this pper we reviewed chievin hih stbility in ddition to wide bndwidth, nd comprin to ll the structures hve been presented, it hs hiher stbility nd bndwidth. The vlue of the compenstion cpcitor is lso reduces sinificntly. There for, firstly we review the mplifier structure nd finlly, brin the Simultion results nd proposed Dimensions. conducted Simultions in this pper ws on 0.5µm for (5-kΩ//0Pf lre lod. KEYWORDS: Stbility, frequency compenstion, three ste mplifier, sinle miller compenstion. INTRODUCTION Opertionl mplifier in netive feedbck rrnement, used widely in nlo circuits such s reultors, filters nd the dt converts for bufferin nd filterin []. Rerdin to the minimum number of trnsistors, one ste opertionl mplifiers hve the best frequency response, nd hve hiher speed comprin to multi ste mplifiers. It my be ble to eliminte the effect of non-liner open-loop system (in closed loop confiurtion sufficiently, but due to the DC open-loop in cn be chieved in these structures, especilly in new technoloies, it is not noticeble. To solve this problem, in most cses, two nd three ste Op Amp re used for frequency compenstion []. Three ste mplifiers re hihly desirble, due to their hih volte in. Unfortuntely, from the point of view of stbility nd bndwidth they re low. So chievin hih stbility in n pproprite bndwidth cn be most efficiently. For lre cpcitive lods of up to three cteories of mplifiers it is inevitble. Therefore, these mplifiers re needed to robust hih frequency compenstion scheme to hve ood stbility of the closed-loop rrnement. Amon the techniques introduced for drivin of lre cpcitive lods in three ste mplifier, Sinle miller cpcitor Compenstion mplifier, hs severl dvntes due to usin one compenstion cpcitor insted of two, such s: Low overll re, reter bndwidth, reter stbility nd smller compenstion cpcitor. In this pper, the desin ws bsed on chievin wide bndwidth in hih phse mrin nd the compenstion cpcitor vlue is reduced s much s possible. Achievin to this im, firstly review different three ste mplifier with lre cpcitor lod nd then, the structure of SMC. Finlly, brin the result of Simultion nd the proposed Dimensions of trnsistors.. Bckround nd pervious work Amon the Frequency Compenstion schemes, Nested Miller Compenstion (NMC re not suitble for lre cpcitive lods. Becuse Its bndwidth is severely limited due to ste incresin[]. The size of compenstion cpcitor lso increse proportionlly with the lod cpcitor. This drwbck led to other compenstion schemes such s Multipth Nested Miller Compenstion (MNMC []. This scheme introduces feedforwrd pth for hih frequencies tht improves the bndwidth of the overll mplifier by pole-zero cncelltion within the pssbnd. pssbnd. Stbility of the NMC is improved by removin the riht hlf-plne (RHP zero. To this end, phse compenstion schemes such s nested Gm-c compenstion (NGCC [4] nd NMC with feedforwrd trnsconductnce ste nd nullin resistor (NMCFNR [5] hve been reported. Smll compenstion cpcitor helps to stbility of much hiher bndwidth. All of the bove compenstion techniques,use miller cpcitor whose size depend on the size of lod cpcitor. For lre lods, the size of the tend to increse Miller cpcitors. For Reducin these problems, nd incresin bndwidth we use some schemes such s: No Cpcitor FeedForwrd compenstion( NCFF [6] nd Active Feedbck Frequency Compenstion (AFFC [7]. NCFF is bsed on pole-zero cncelltion t hih frequencies resultin in hiher bndwidth nd fster settlin time. In AFFC we use n ctive cpcitor which reduce the size of the * Correspondin Author: Zhr Rnjbr, member of Youn Reserchers Club, Fs Brnch, Fs, Irn Rnjbr80@mil.com 6

2 Rnjbr et l.,0 compenstion cpcitor. There re nother compenstion schemes on three ste mplifiers, for exmple Dmpin Fctor Control Frequency Compenstion (DFCFC [8] which uses The dmpin control block on pole complex position, or Dul LOOP prllel Compenstion (DLPC [9] but none of noted technique re suitble for drivin lre cpcitor lods.. Sinle Miller cpcitor compenstion Amplifier (SMC In most three ste mplifier structures were used two compenstion cpcitor to drivin lre cpcitor lods. But the Compenstion presented in this section, only smll cpcitors used for three ste mplifiers. In mplifiers with lre cpcitive lod, lst ste poles re usully very smll nd it is so ner to the dominnt pole which is locted on the first ste, nd should be lower it's effect by One of the most common compenstion. In Usul pole splitin hs been used. In fiure ( you cn see the structure of SMC mplifier. Fiure: Topoloy of sinle Miller cpcitor compenstion mplifier (SMC A lrer bndwidth cn be obtined by usin only one cpcitor for compenstion insted of two. The structure hs three in stes with only one compenstion cpcitor. It hs n dditionl trnsconductnce ste (mf from the output of the first ste to the finl output. This forms push-pull ste t the output tht helps in improvin the trnsient response of the mplifier. sinle Miller compenstion cpcitor(cm is used to split the first pole(p nd the third pole (p. The position of the second nondominnt pole(p is dictted by the in of the second ste, which decides the stbility of the mplifier[0]...smll-sinl Anlysis Smll-sinl nlysis is crriedout with the followin ssumptions..the in of ll stes re much reter thn.. The Prsitic cpcitnces C P,C P nd C PL re much smller thn the Miller cpcitor C m nd lod cpcitor C L.. The trnsconductnce of the feedforwrd ste, mf, is equl to tht of the third in ste, ml. The trnsfer function is iven by (: AV ( SMC C C C C Adc s s VO ( s Vin( s s C C C p C C C C p mf m o m p ( s s m ml m ml C C s C p L ( s L o s GBW m ml m ml ( p mf m o m p ( m ml m ml L o p L ( ( s s db m ml m ml Where AV ( SMC (0 A dc ( m m ml / o o L is the dc in of the mplifier, nd P db ( oo L / m mlc m is the dominnt pole of the mplifier. Hence, the in-bndwidth product is iven 7

3 J. Bsic. Appl. Sci. Res., (s6-, 0 by A dc. db m /. From the trnsfer function, the mplifier hs two nondominnt poles nd two zeros... stbility nlysis The stbility condition of the SMC mplifier cn be determined by nlyzin the closed-loop trnsfer function with unity-in feedbck confiurtion. Since the zeros re locted t hiher frequency, they re nelected. The closedloop trnsfer function is ( A cl ( S M C sc m C L o C P C ( ( L s s m m m L m m L 0 s s s which cn be written s: C p C L C m 0 m m m L C C m o L m m ml C m m Amplifier stbility derived from closed-loop trnsfer function (,which the order of the numertor is less thn thn tht of the denomintor. so, writin down closed loop trnsfer function nd pplyin the Routh Hurwitz stbility criterion on the chrcteristic eqution of trnsfer function (4, it yields 0 0 o (4 m GBW c p c m If nd only if condition (4 is stisfied, the system is unconditionlly stble. For lre cpcitive lods, the stbility nlysis of the mplifier cn be done usin the seprte pole pproch Assumin tht the zeros of the mplifier re locted t hiher frequencies nd hence cn be nelected, the nondominnt poles of the mplifier re clculted s follows. P ( G meff / C L (5 P ( o / C p _( G meff / C L (6 G meff ( m ml / o (7 The vlue of the compenstion cpcitor become C ( m m C L. This represents compenstion cpcitor is A V ml very smll thus,it cn be seen tht by suitble choice of the second-ste in ; Av ( m / o The vlue of the compenstion cpcitor cn be reduced. Note tht, Zeros of the trnsfer function depends on the compenstion cpcitor if the vlue of this cpcitor is too smll, zeros re plced t very hih frequencies[0]. The phse mrin is clculted s follows: GBW GBW GBW PM 80 tn ( tn ( tn (. P P p.. Slew Rte nd Settlin Time ( 8

4 Rnjbr et l.,0 The trnsient response of the mplifier is comprised of the slewin nd settlin behvior of the mplifier in closedloop condition. The slew rte of the mplifier depends on the size of the compenstion cpcitor. The sinificnt increse in the slew rte of SMC s compred to tht of NMC under the sme power constrint is due to the reduction in the size of the compenstion cpcitor. The Settlin time of the mplifier hs two components of Smll sinl nd lre sinl time. Bndwidth chieved in SMC structure, obtined by scrificin bsence of doublet in the pssbnd of the mplifier, There is no trouble in smll sinl time. This prt influenced by bndwidth. In ddition the time of lre sinl is very low rerdin to the smll mount of the compenstion cpcitor nd Slew Rte finlly do not influenced by the compenstion cpcitor..4. Desin Considertions nd Circuit Implementtion A judicious distribution of in mon the three stes is one of the most importnt considertions in the desin of these mplifiers 00dB, the in is distributed such tht A v A v A v. This results in the second nd third pole of the mplifier bein locted t hiher frequencies due to the hih output conductnce of the second nd third stes. This rouhly results in sinle-pole system. In order to chieve this, the first ste uses folded cscode topoloy to enhnce the output impednce. A moderte in t the second ste helps in reducin the required compenstion cpcitor to ret extent. For exmple, 00-dB in from three stes cn be distributed s 60, 0, nd 0 db for the first, second, nd third stes, respectively. thus A v = 0dB resultin in reduction of the required cm by fctor of 0 60 compred to tht of NMC while mintinin stbility. The circuit implementtions of the SMC mplifier is shown in Fis (. trnsistors M -M form the first in ste. 8. The second in ste of the mplifier is comprised of trnsistors M 9-M. The output ste is comprised of feedforwrd Ste mf nd the third in ste ml formin push-pull ste. The third in ste is relized by trnsistor M, wheres the feedforwrd ste is relized by trnsistor M4. The te drin cpcitnce of trnsistor M forms n dditionl Miller cpcitor between the second nd third stes. Since the prsitic cpcitor vlue nd the in of the third ste re smll, it is nelected. 4. Simultion Results Circuit-level simultion results re obtined with 0.5 µm BSIM.5 V models usin HSPICE. All the results bove re with 5kΩ //0-pF lod. In this pper n ttempt hs been done to desin compenstion cpcitor s smll s possible. the vlue of the Miller cpcitor is pf. Tble ( contins the proposed dimension of trnsistors which Simultions hve been performed bsed on them. In SMC our tret ws rechin to Hih phse mrin in wide bndwidth. in ddition, they should hve Hih DC in, nd finlly we rech to 76º phse mrin in 6.MHZ bndwidth, which is optimum nd comprin to previous models is much more better. In fiure ( you cn see, Simultion of frequency response of SMC open loop mplifier. Amon The prmeters of closed loop we cn mentioned settlin time slew rte. Both of them re Importnt prmeters for opertionl mplifiers nd chieved from Trnsient closed-loop system sttus. Since this desin hve hiher bndwidth, it hve hiher speed nd better settlin time nd slew rte comprin to pervious structure. In fiure (4 you cn see closed-loop simultion of desined structures. with the.5-v step input, there is n overshoot for the up-oin sinl. For the low volte nd the hih volte, the opertin points of the trnsistors in the circuit re different, which mens tht the effective pole, zero loctions of the mplifier re different for risin nd fllin sinls. This is the reson why overshoot ppers for upoin sinl, nd not for down-oin sinl. The 0.% settlin time is considered. in tble (, comprison between new desined nd previous models hs been done, then we could prove the superiority of bove desin. Tble : trnsistors proposed dimensions. TRANSISTOR Mb Mb M, M,4 M5,6 M7,8 M9 M0, M M M4 SMC *(.9/0.5 8*(.9/0.5 8*(.8/0. 6*(0.9/0.5 *(0.9/0.5 6*(.8/ *(.8/0. *(.5/0.48 6*(.9/0. *(8/0. 0*(/0. 9

5 J. Bsic. Appl. Sci. Res., (s6-, 0 Fiure: opmp loop-in frequency response of SMC Fiure4: opmp close- loop frequency response of SMC 5. Conclusion In this pper, sinle miller cpcitor frequency compenstion ws presented on three stes mplifiers, nd comprin to previous structures hve better bndwidth nd phse mrin. In ddition, Compenstion cpcitor vlue is decresed sinificntly. Rerdin to settlin time nd slew rte of this system hve pproprite Vlues. Fiure: Schemtic of the SMC mplifier. 0

6 Rnjbr et l.,0 PARAMETER Lod PF/kΩ DC in(db GBW(MHZ Phse mrin Cpcitor Vlue (pf SR+(V/µS SR-(V/ µs +% TS(µS -%TS(µS Technoloy Tble: A comprison between multi-ste mplifiers with lre cpcitive lod. NMC [7] C m=88 C m= µm DFCFC [8].6 4 C m=8 C m= µm AFFC [7] C m= C m= µm DLPC [9] 7 46 C m=4.8 C m= µm SMC [0] C m=7 one µm SMC THIS WORK C m= one µm REFERENCES [] B. Rzvi, Desin of Anlo Interted Circuits, McGrw-Hill, 000. [] H. Aminzdeh, M.Dnie,R.Lotfi Desin of hih-speed two-ste cscode-compensted opertionl mplifiers bsed on settlin time nd open-loop prmeters Elsevier,vlsi journl, 008. [] R. G. H. Eschuzier, L. P. T. Kerkln, nd J. H. Huijsin, A 00-MHz 00-dBertionl mplifier with multipth nested Miller compenstion structure, IEEE J. olid-stte Circuits, vol. 7, no., pp ,Dec. 99. [4] F. You, S. H. K. Embbi, nd E. Sánchez-Sinencio, Multiste mplifier topoloies with nested G -C compenstion, IEEE J.Solid-Stte Circuits, vol., no., pp , Dec [5] K. N. Leun nd P. K. T. Mok, Nested Miller compenstion in low power desin, IEEE Trns. Circuits Sys. II, vol. 48, no. 4, pp.88 94, Apr. 00. [6] B. K. Thndri nd J. Silv-Mrtinez, A robust feedforwrd compenstion scheme for multiste opertionl trnsconductnce mplifiers with no Miller cpcitors, IEEE J. Solid-Stte Circuits, vol. 8, no., pp. 7 4, Feb. 00. [7] H. Lee nd P. K. T. Mok, Active-feedbck frequency compenstion technique for low power multiste mplifiers, IEEE J. Solid-Stte Circuits, vol. 8, no., pp. 5 50, Mr. 00. [8] K. N. Leun, P. K. T. Mok, W.-H. Ki, nd J. K. O. Sin, Three ste lre cpcitive lod mplifier with dmpinfctor control frequency compenstion, IEEE J. Solid-Stte Circuits, vol. 5, no., pp. 0, Feb [9] H. Lee, K. N. Leun, nd P. K. T. Mok, A dul-pth bndwidth extension mplifier topoloy with dul-loop prllel compenstion, IEEE J. Solid-Stte Circuits, vol. 8, no. 0, pp , Oct. 00. [0] X. Fn, C. Mishr, nd E. Snchez-Sinencio, 'Sinle Miller Cpcitor Frequency Compenstion Technique for Low-power Multiste Amplifiers,' IEEE J. Solid-Stte Circuits, vol. 40, no., pp ,Mr. 005.