Robust Full On-Chip CMOS Low Dropout Voltage Regulator with Active Compensation

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1 obust Full On-hip MOS ow Dropout Volte eultor with Ative oenstion Zred Kml Eletril Enineerin Deprtment Fulty of sienes nd tehnoloy Fez, Moroo Qjid Hssn Deprtment of Physis Fulty of sienes Dhr El-Mehrz Fez, Moroo Zouk Mouhine Eletril Enineerin Deprtment Fulty of sienes nd tehnoloy Fez, Moroo Abstrt This pper present full on-hip nd re effiient low dropout volte reultor(do), exploitin the nested miller oenstion with tive pitor (NMA) to eliminte the externl pitor nd tive feedbk resistors to redue the hip re. The externl pitor is removed llowin for reter power system intertion for system on-hip pplitions. The ide hs pplied to stbilize.6 V, 50 ma ow dropout reultor. Usin the proposed tehniques the reultor DO works with supply volte s low s.8 V nd provides lod urrent 50 ma with dropout volte of 00 mv nd output vrition 4 mv when full lod step 0-50 ma is pplied. It desined in 0.8 µm MOS tehnoloy. Keywords ow dropout, MOSAP, NMA, Ative feedbk, MOS oenstion, low-volte reultors, system on hip, reultors. I. INTODUTION Over the lst dede, power mnement in interted iruit hs beome n inresinly iortnt desin onsidertion for numerous produts, espeilly those relyin on bttery power. olitin the power mnement sitution, s more fetures et interted into produts, the number of required volte supplies inreses. power mnement utilizin multiple lol on-hip volte reultors is very promisin pproh in system-on-hip development [][]. The ltest enertion of DOs offer the optimum nswer for powerin iruitry in mny of the portble devie pplitions suh s ell phones, PDAs, pers, notebooks, mers nd other hndheld portble systems where hih performne power supply iruits re required. In ft, they n provide reulted nd urte supply voltes for noise sensitive nlo bloks, nd they re often rrned in series to swithin reultors to remove the inherent noise produed by the swithin tivity[4][7]. These dvntes mkes DO widely used in portble systems, espeilly in F iruitry To inrese bttery-life nd to hieve better power effiieny. Unfortuntely, the trdeoff between stbility nd dropout volte of liner reultors mkes unoensted DOs potentilly unstble. The onventionl DO lotes the dominnt pole t very low frequeny t the output to hieve the frequeny oenstion nd provide ood dynmi performne, lre off-hip pitor t DO output, enerlly bout 0.47 µf to 4.7 µf for 00 ma DO [],[3][8]. The lre off-hip pitor oupy lre hip re, nd it is diffiult to interte multiple DOs on sinle hip. In order to desin full on-hip DO reultor, the number of oenstin pitors must be minimized[3] [5],[7]. Different methods hve been introdued reently to irove the performne of full on-hip DO. In [4], the proposed DO utilize din-ftor ontrol frequeny oenstion. The reultor is bsed on multiste lifier, nd provide n output volte of.8 V, mximum output urrent of 50 ma nd 08 mv of line reultion. however, the overshoots t the output of DO proposed in [4] is too lre (900 mv), nd the settlin time is bout 5 µs., it is not eptble for So pplitions. In [6], the proposed struture irove ood stbility, hih d loop in, but problems still remin in this desin. The overshoot is bout 350 mv, the PS t KHz is db. Moreover the olited Miller frequeny oenstion is needed [4-6]. The nested Miller /3/$ IEEE

2 oenstion (NM) tehnique presented in [3] hs trde off the d loop in nd din ftor. In [8], the proposed full on-hip DO exploits the miller effet throuh urrent lifition, nd need 00 pf in the network oenstion, whih onsumes lre re on-hip DO. In [7], smll onhip pitor (30 pf) stbilizes the proposed desin with ood phse mrin, but t the expense of the low d-in nd low PS. To void these onstrints, one of the possible solutions is the use of MOS pitor[5]. In this pproh the te oxide is thin nd ored to MIMs, MOS pitors lled MOSAPs hve lrer pitne per unit re[5][6]. The min problem in lrely exploitin MOSAPs in nlo pplitions is due to linerity issues. This is beuse of different reions MOSFET experienes when its te-bulk volte vries. For smll bis voltes, the trnsistor is workin in depletion reion, thereby levin the pitor funtion of the te-bulk volte. This derdes overll performne nd mostly dds olexity to the desin of nlo iruits [5],[6]. In the sturtion reion of MOS trnsistor, the vrition pitne of the MOSAP with V BS 0 is neleted[6]. In this pper, we will present novel NM with MOSAP nd resistor(nma) tehnique to ontrol the din ftor nd redue the required Miller pitne without influenin stbility nd relize the full on-hip pitor DO. Moreover, the tive resistor feedbk is used to redue, more hip re nd irove the effiient urrent. I. STABITY OF DO USING THE NM TEHNIQUE The DO usin the NM tehnique nd equivlent smllsinl model is shown in Fis. nd b respetively. In Fi., the DO is oosed of two stes, power PMOS trnsistor, the output pitor nd its ssoited resistne ES. The feedbk resistor network onsists of the resistors, F nd F. In Fi. b m,, re the trnsondutne of the first in ste, the seond in ste nd the power PMOS trnsistor, respetively. o, o, pr, pr re the output resistnes nd prsite pitnes t the outputs of two in stes, respetively. m nd re the NM oenstion pitnes. is the equivlent output resistne, Op ( F F ) where is the lod resistne nd op, is the output resistne of the power PMOS trnsistor. To nlysis the tehnique NM, the followin ssutions re resonbly mde. m o, o, >> >> m,, m >> Pr, >> pr, >> m, () Thus, the smll-sinl loop in is expressed s () s T () 0 s ( s ) _ s ES T s s p 3dB s Where the d loop in is iven by T m ES ( 0) ( F ) And the dominnt pole is t F F () (3) m o o p 3dB (4) o o m The seond-order polynomil the denomintor s in () is rewritten s Where p( s) ζ s s p p p And the din ftor m (6) m (5) m ζ ES (7) In this pproh, the D dopts the sinle-pole system within the unity-in frequeny. Thus, to ensure the loop stbility, the in bndwidth(gbw) is pled to be less thn / of olex pole(p ). tht is m F m F F With the tehnique NM, the pitor m lotes the dominnt pole t the output of the first in ste insted of the output of the power PMOS trnsistor. Hene to relize low dominnt pole, lre m required. Moreover the nd ES re not needed to stbilize the system but there re iortnt to relize n pproprite din ftor. For this struture to hve lre d loop in of the DO, tht is, is inresed nd lre is needed, too. It mens tht there is trde-off between the din ftor nd d loop in. From the smll sinl loop in in eq. (5), the numertor hs three zeros. From eq. (), nd the followin ssutions ~ μ F, m, m ~ pf (9) (8)

3 Vref Alitude / db Aop Aop m f f PMOS Fiure. DO usin the NM tehnique Frequeny / Hertz P-3dB DO usin NM tehnique VIN out ES P-3dB V IOAD onventionl DO m 0m 00m 0 00 k 0k 00k M 0M 00M G Fiure. frequeny response of the onventionl DO nd the DO usin NM tehnique Z HP Z ES ES 4 m m m, 4 m m Z (0) HP m From eq. (0), the three zeros our t very hih frequenies even muh hiher thn the non dominnt poles, thus, the stbility is not ffeted. Fi. shows the loop frequeny response of the onventionl DO nd the DO usin NM tehnique. For onventionl DO, lre output pitor is required to lower the dominnt pole. However lre is diffiult to interted on sinle hip. For the DO usin the NM tehnique, the output pitor ontributes to the non dominnt pole, nd the off-hip pitor n be lowered to redue the re nd ost. In the low lod, the non dominnt poles re lose to the unity-in frequeny. Hene to dopts the sinle pole system within unity-in frequeny, lre vlue of m is needed. In the hevy lod, the non dominnt poles inrese, too nd smll din ftor my be our if the output pitor is smll enouh. To hve n pproprite din ftor, lre is needed nd lre re is needed on hip. II. POPOSED DO A proposed solution to ontrol the din ftor nd redue the re of the oenstion pitor on-hip, is the NM tehnique with tive pitor nd resistor, it is lled n NMA DO. This tehnique n resolve the trde-off between the d loop in nd the din ftor, notieble in the DO usin the NM tehnique. The shemti of the proposed DO is shown in Fi. 4(), this DO is oosed of two in stes, power PMOS trnsistor nd the feedbk resistor network. First ste is the error lifier(ea), seond is hih in ste. m, re the on-hip Ative MOS pitnes. The proposed struture of the MOS tive pitor s shown in Fi. 3. f nd f onstrut the tive feedbk resistive network. nd model the equivlent lod resistne nd lod pitne t the output of DO. is the interonnetion lines prsiti pitor, nd typilly up to 00 pf. The n-well resistor hs hih vlue for its volte oeffiient, whih ffet the ury in the Is. Wek inversion reion MOS trnsistors re used s feedbk network resistor insted of onventionl n-well resistors in order to lowers quiesent urrent nd sve silion re. A. Error Alifier The desin of error lifier(ea) is more olex, When hih performne requirements is demnded, to urntee the stbility nd trnsient response speifi topoloy is neessry. To move the dominnt pole t the output of E.A to low frequenies low output iedne is desined. To hre rpidly the pitne seen t the te of pss trnsistor (my be s lre s 50 pf), EA must provides suffiient output urrent [8],[9]. On the ontrry, the EA itself should provide very low power dissiption, nd its bis urrents must be kept s low s possible. In this pper the proposed EA is the folded sode lifier whih offer iroved performnes suh s hih in, enouh lod urrent to drive the power trnsistor PMOS nd irove the PS hrteristi of DO. B. MOSAP oenstion network In the full on-hip DO, the lod pitor modeled t drin of pss trnsistor is determined by the interonnetion lines nd typilly up to 00 pf. This pitive vlue is too smll to set dominnt pole t the output node of on-hip DO [8],[0]. Therefore the oenstion must be hieved throuh the miller effet. In [5] the Miller oenstion tehnique is pplied to oenste two-ste Op A. As result the dominnt pole is pled t the output of first ste by the Miller effet on the oenstion pitor nd moved to the low frequenies. The seond pole is moved wy from oriin of the olex frequeny plne. Due to the feedforwrd pth throuh the Miller pitor undesirble zero ours on the positive rel xis of the olex frequeny plne. Another tehnique used in [5] to remove the zero resultin from feedforwrd throuh the oenstion pitne is to insert nullin resistor in series with Miller pitor. In this tehnique the nullin resistor must be set equl to the inverse of output trnsondutne of the seond ste to remove the HP zero.

4 onsequently the dependene of nullin resistor to the lod urrent llow the ontrol of the output pole. The problem is while fst vrition in output lod urrent it is diffiult to desin neltion tehnique of the HP zero. With this pproh to ensure phse mrin bout 60, the output pole must be pled bout. times hiher thn GB. As result the rtio of lod pitor nd oenstion pitor must be reter thn 0.. These pprohes require lre oenstion pitor nd hih in of seond ste to inrese in fbrition ost. Furthermore, lthouh vilble metl lyers in mixed-sinl tehnoloies n be utilized for MOM(metl-oxide-metl) pitors, due to the reltively lower slin rte of the oxide between these lyers, the oupied physil re is notieble []. To void these onstrints, one of the possible solution is to eloy MOS-te juntions s pitor Fi. 3. The MOS pitors lled MOSAPs hve lrer pitne per unit re, with hih rtio of desired pitne to prsiti pitne. The problem to exploitin MOSAPs in nlo pplitions is due the linerity issues[3].this is beuse of different reions V V b I b I V od V od DD out K K MP V MP V TP V W DD MP TN TP B I TN B I bis, W K V V out, bis ( W ) K ( W ) MP V V () ensure the stbility. Moreover it is diffiult to interte lre pitor on-hip DO. In the reent desin of the system on-hip pplitions it is very desirble to interte the nlo portion of lre mixedsinl system in stndrd diitl MOS tehnoloies with no nlo fetures. However, in order to ilement onstnt pitors for nlo pplitions, seond poly or extr metl lyers re introdued into the proess, resultin in sinifint MOSFET experienes when its te-bulk volte vries. In the proposed struture the vrition is not drops under 0.9V. the MOSAP is workin in the umultion reion. In [4] the umultion reion is defined s V b >0.9V. In this reion the pitne is not dependent of the te bulk volte. The D potentil t the te nd bulk of MOSAP re iven by, bulk MOSAP Gte Fiure 3. Ative pitor with p-hnel MOSFET Where V TP, V TN re the threshold volte of PMOS nd NMOS trnsistor. B is the urrent in of urrent mirror, I bis is the strtup urrent of the iruit nd V V out. In the worst se, when Iod inreses instntneously from eq. (), the te volte of pss element drops in time or the lod pitor dishrers to supplies the extr urrent demnded t the output. As result the urrent in of urrent mirror M8 nd M5 is dereses nd the bulk volte of MOSAP is lso drops verify ondition of the te bulk volte Vb>0.9V to workin in the umultion reion. The problem of this tehnique is remin when the supply volte drop under V.. Frequeny response The oenstion tehnique used in this struture ples the dominnt pole t the low frequenies nd move the prsiti poles to hih frequenies when the HP zero reted by the oenstion pitne iroves the phse mrin in time or the HP is pled t hih frequenies. M6 M7 M M3 M4 M0 M IBIAS M6 M8 M4 M6 M9 M4 M M3 M OIN M3 VBG M7 OIN O M9 M5 M8 M0 M M8

5 V V m /m Vout mvfb o p V o p V b Fiure 4. ) proposed DO usin NMA b) equivlent smll sinl model onsiderin the equivlent smll sinl in Fi. 4(b) of the proposed DO nd ssumin tht m << m, the smll sinl loop in is iven by. T T () () ( bs bs ) s T 0 * s ( S S ) p 3dB ( 0) ( F ) F F () (3) m o o Where the dominnt pole is t And p 3dB m o o m b, b m m m, m (4) (5) Assumin tht m is smll nd the non dominnt poles re widely sped, then the roots of the seond-order polynomil in the denomintor in eq.(8) re rewritten s P nd m m pnd (6) In the NMA DO, the dominnt pole is unhned, but the non dominnt poles re pushed to hih frequenies. From the polynomil in the numertor of eq. () nd ssumin tht the pproximtion in eq. (5). m Z HP, Z HP (7) mm m Inresin the lod urrent, the HP zero nd non dominnt pole formed t the output of DO move to hiher frequenies, while the HP zero is independent of the lod urrent. Similrly, s three zeros our t very hih frequenies even muh hiher thn the unity-in frequeny, their effets n be neleted s shown in Fi. 5 From Eq. (, 5), the din ftor is derived s ζ (8) m In the NMA DO, smll m enhnes the din ftor without influenin the d loop in nd without inresin. the din ftor is ontrolled by m insted. III. DO DESIGN The proposed reultor hs been desined for supply volte intervl of [.8V-3.6V] nd provide n output volte of.6v. the pss trnsistor is sized of µm/0.7 µm to provide n output urrent of 50 ma with volte drop of 00mV. In this desin the non-dominnt pole t the output system depends the lod urrent. t low lod derese the non-dominnt pole in Eq. (5) moves to low frequenies, smll is needed to keep this pole hiher thn GB. The EA

6 is desined in this pper to provide the requirement performnes. The input ste struture is folded sode nd the strtup urrent is mirrored nd lify to the pir differentil lifier. When V FB is less thn V BG the output urrent is inresed by sode mirror. Furthermore the sode urrent mirror is lso inrese D-in of the EA nd drive the PMOS to provide mximum urrent in the hih lod. The urrent follow t the output (~60 µa) of EA is enouh to hre rpidly the pitor t the te of power PMOS. In the desin of DO the iortnt hrteristis re tkes in ttention suh s od reultion nd line reultion. In lod reultion, when the lod urrent suddenly steps from zero to its mximum vlue the powerless of the pss trnsistor to provide demnded urrent fore the lod pitor to supplies the extr urrent nd the pitor volte drops. The tive feedbk trnsfers this drop in output to the EA whih in turn down the te volte of the pss element thus inresin V SGP nd providin the output urrent by lod iedne. Sine the oenstion pitors forms the feedforwrd pth to injet hres in the lod pitor nd dereses the output volte overshoot. When the lod urrent deresed instntneously, the over urrent from the output of the power PMOS hres the output pitor to the over nominl output volte. In the line reultion, the ripple on the power supplies is trnsmitted to the output of onventionl DO oensted by miller pitor nd te drin prsiti pitor. In the proposed desin, the tive trnsistor M inreses the iedne t the te of PMOS trnsistor nd turnin off the miller pitor pth from te to output of DO s in[7][8]. As result the unique pth n trnsmits the ripple in the supplies volte to the output is the te-drin prsiti pitor of PMOS trnsistor. IV. SIMUATION ESUTS The proposed reultor hs been relized in 0.8 µm MOS proess. The simultion ws hieved in dene Pltform. The loop-in simultion with totl oenstion pitor of iruit totl 6 pf is shown in Fi. 5. In the proposed DO is stble with pitne rne (0 pf to uf), s shown in Fi.5 the prsiti poles re pled t hih frequenies with phse mrin 76. The I hs been desined to work with for supply volte from. to.8 V. The externl bis urrent, IBIAS flowin throuh trnsistor M6, hs been set to µa. The dropout volte t output urrent of 50 ma is 9 mv, the mximum round urrent 5 µa. The reultor ws subjeted to 30 ma lod trnsient with 0.5µs rise nd fll times, s shown Fi. 6 )nd b), positive overshoot sty below 69 mv, the litude of netive rinin is bout 59 mv while the response time, T tkes bout 0.4µs(n). Moreover, the proposed DO lso stble when n off-hip pitor is used. The D vrition of the proposed DO when the supply volte VIN hnes.4 V to 3 V is bout mv s shown in Fi. 7 ) nd b) the vrition of the output when the lod urrent hnes from ma to 50 ma is bout.5 mv s shown in Fi. 8. b). Fiure 5. Simulted of the open loop in nd phse responses of the proposed DO with NMA

7 Fiure 7. mesured of ) A lod reultion, b) A line reultion b b Fiure.8 mesured of D () line reultion VIN to 5.5V (b) od eultion Ilod0 to 50 ma TABE I. PEFOMANES AND OMPAAISON WITH OTHE WOKS Prmeter [7] [9] [8] This work Tehnoloy µ 0.35µ 0.3 µ 0.35 µ VIN (V) V (V).5.6 Drop-out 3 mv 00 mv 00 mv 00 mv 4 pf pf Imx 50 ma 50 ma 50 ma 50 ma IQ 40 µa 45 µa 0 µa 5 µa ΔV 9 mv 70 mv 300 mv 5 mv PSS db -60 db V. ONUSION In this pper full on hip MOS DO usin novel tehnique hs been presented. The DO proposed is pble of providin 50 ma with drop-out volte of 9 mv when powered t.6 V. The stbility is hieved by usin the MOSAP oenstion bsed on the seril oenstion depletion mode. The proposed reultor is minly used s the reulted power soure for wireless pplitions, FID nd hre pu in P. EFEENES [] G.A. ino-mor nd P.E Allen Optimized frequeny-shpin iruit Topoloies for DO s IEEE trns. iruits sys.ii, Vol. 45, no. 6, Jun 998, pp [] Si Kit u, Philip K.T.Mok nd K Nn eun A ow-dropout eultor for So With Q-edution IEEE Journl Of Solid-Stte iruits,vo.4, NO.3, MAH

8 [3] Gbriel A. inon-mor, Phillip E. Allen A ow-volte, ow Quiesent urrent, ow Drop-Out eultor, IEEE Journl Of Solid-Stte iruits,vo.33, NO., JANUAY 998. [4] W.-J. Hun S.-I. iu pitor free low dorpout reultors usin nested Miller oenstion with tive resistor nd -bit prormmble pitor rry IET iruits Devies Syst., 008, Vol. 3, pp [5] obert J. Milliken, Jose Silv-Mrtínez Full On-hip MOS ow- Dropout Volte eultor, IEEE Trnstions On iruits And Systems I: eulr Ppers, Vol. 54, No. 9, September 007. [6] M Hifen, Zhou Fen Full on-hip nd re-effiient MOS DO with zero to mximum lod stbility usin dpttive frequeny oenstion Journl of Semiondutors, Vol. 3. No. Jnury 00. [7] -. Wn, -. Hun, nd U. F. hio A liner DO reultor with modified NMF frequeny oenstion independent of offhip pitor nd ES Anlo Inter ir Si Proess (00) 63: [8] Ginlu Giustoli, Getno Plumbo, nd Ester Spitle. A 50 ma - nf ow Volte ow Dropout Volte reultor for So Applitions. ETI journl, Vol. 3, Nunber 4, Auust 00. [9] K. N. eun nd P. K. T. Mok, A pitor-free MOS low-dropout reultor with din-ftor-ontrol frequeny oenstion, IEEE J. Solid-Stte iruits, vol. 37, no. 0, pp , Ot [0] Si Kit lu, Philip K.T. mok nd K Nn eun, A ow-dropout eultor for So With Q-edution IEEE Journl of Solid-Stte iruits, VO. 4, NO. 3, Mrh 007. [].-. hen W.-J. Hun nd S.-I iu MOS low dropout reultor with dynmi zero oenstion Eletronis letrres 5 th July 007 Vol. 43 No. 4. [] Go eishen, Zhou Yumei, Wu Bin, nd Jin Jinhu. A full on hip MOS low dropout volte reultor with VS oenstion. Journl of Semiondutors, Vol. 3, No. 8 Auust 00. [3] Milliken,. J., Silv-Mrtinez, J., & Snhez-Sinenio, E. (009). Full on-hip low-dropout volte reultor. IEEE Trnstions on iruits nd System, 54(9), [4] H. Aminzdeh,. otfi, nd K. Mfinezhd Are-Effiient ow- ost ow-dropout eultors Usin MOS pitors IEEE /08/$ [5] Philip E. Allen, Douls. Holber MOS Anlo iruit Dedin, seond edition, 0 8

High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications

High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications Interntionl Journl of omuter litions (0975 8887) Volume 7 No.8 June 03 Hih PSRR Full On-hi MOS ow Droout Volte Reultor for Wireless litions Zred Kl Eletril Enineerin Dertment Fulty of Sienes nd Tehnoloy