2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media,

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1 005 IEEE. Personl use of this mteril is permitted. Permission from IEEE must be obtined for ll other uses, in ny current or future medi, including reprinting/republishing this mteril for dvertising or promotionl purposes, creting new collective works, for resle or redistribution to servers or lists, or reuse of ny copyrighted component of this work in other works.

2 Inter-ircuit Fults nd Distnce Relying Of Dul ircuit Lines D. J. Spoor, nd J. hu, Senior Member, IEEE bstrct-- The min sources of error nd other difficulties ssocited with the distnce protection of dul circuit trnsmission lines is well known. However, the design or selection of protection schemes usully fils to consider some of the more extrordinry fult occurrences tht do occur. This pper considers the observed impednces tht result from inter-circuit fults on simulted dul circuit trnsmission line, where vritions in the phsing, nd the impednce rtios hve been considered. The simultions performed with the lternte Trnsients Progrm show tht inter-circuit fults my be undetectble in the instntneous protection zone depending on the scheme dopted nd the impednces of the surrounding network. The observed under-reching hs the potentil to led to loss of mjor lods, ml-opertion of single pole tripping schemes nd even system instbilities bsed on the criticl clernce requirements. Index Terms-- Inter-circuit fult, distnce protection, dul circuit, distnce scheme, phse selectivity, under-rech I. INTRODUTION he distnce protection of dul circuit lines presents vrious Tdifficulties, which re result of the well known error sources for multi-circuit lines. These rise from fult resistnce, the pre-fult lodflow conditions, the mutul coupling tht exists between the circuits nd the vriety of fults tht cn occur on such lines. Mutul coupling is often considered to be the min concern when protecting dul circuit lines with distnce relys. The resulting errors re gretly ffected by the topology of the line nd vlues of the zero sequence source impednces present t ech terminl. This cn produce severe under-reching nd over-reching errors for distnce relys. In some cses, distnce relys my see less thn 50% or fr more thn 00% of the line, depending on the infeed nd coupling conditions experienced []. Due to the nture of the zero sequence coupling tht exists between the circuits, the sttus of the prllel line cn produce the most noticeble effect. The distnce elements will overrech when both lines re in service nd under-rech will be experienced if the line is out of service nd erthed t either end []. The definition of immunity distnce hs been provided in D. J. Spoor is with Trnsgrid, New South Wles, ustrli (e-mil: J. hu is with the Deprtment of Electricl Engineering, University of Technology, Sydney, ustrli (e-mil: [] s rtio of the terminl zero sequence source impednces. In such cse, the loction t which the coupling contributions cncel will be the sme for ny under-rech or overrech. It is lso well known tht the pre-fult lod together with ny fult impednce cn modify the rel coverge of distnce element due to the conversion of the fult resistnce into n observed rectnce []. However, on dul circuit lines these effects re generlly not s severe s those presented by mutul coupling. Severl solutions re employed to llow for these impednce errors. The one nd one reches re often reduced nd incresed respectively in ccordnce with set of system studies. This gurntees the correct opertion of the rely under ll system opertion conditions. n lterntive pproch is to djust the residul compenstion vlue such tht either the under-reching or overreching errors re minimized, while experiencing greter over-rech or underrech respectively []. dptive zone reches hve lso been pplied in mny references, including [3]. These commonly chnge set of bsic prmeters when the network topology chnges, possibly incorporting neurl networks. These systems re often very complex nd re not presently common in most trnsmission systems. n lterntive to the bove techniques is to dopt new protection philosophies to overcome existing sources of error in protection relying [4]. The conductor geometry in dul circuit lines mkes them prone to multi-circuit fults, of which the erthed crosscountry fult is the most common. Nevertheless, unerthed inter-circuit fults crete unusul problems for the protection engineer due to the under-rech nd the zero sequence currents present in the circuits themselves. These currents do not extend beyond the busbrs, nd consequently the terminl zero sequence source impednces hve little impct [5]. Such fults hve significntly high probbility of occurrence, s result of bushfire ctivity, conductor glloping or broken conductors on prticulr circuit. The under-rech is creted by the pprent trnsition between double-phse-to-erth to single-phse fult s the fult loction is vried long the circuits. Inter-circuit fults nd close-in erth fults re lso known to result in loss of phse selectivity for single-pole tripping schemes due to n introduction of zero sequence currents [,6]. This cn be serious problem on importnt circuits where system stbility is concern.

3 The nlysis in this pper considers the impct of intercircuit fults on dul circuits under vrious line nd source impednce configurtions. The consequences of inter-circuit fults re often not considered in conventionl design philosophies nd the filure to observe such fult cn hve serious consequences. = 00 = 3 = = 0 (3) II. LINE ND FULT LOOP IMPEDNES For short dul circuit line, the trnsverse voltges nd line currents cn be defined by the trnsmission line impednce mtrix s following: V V V = V X V Y V X Y X Y X Y X X X X YX X Y Y Y XY Y Y I Y I I = X I X Y IY I D I I I I X I Y I where V φ nd I φ re the phse voltges nd currents, nd φ nd φφ the self nd mutul impednces of the phse conductors, respectively. s is the cse for single circuit under blnced conditions, the mtrix is digonlly symmetricl (ll the self nd coupling impednces re identicl). Similrly, for n unblnced circuit the impednce mtrix will remin digonlly symmetricl lthough the self nd mutul impednce terms differ. This mtrix cn be derived from the well-known rson s equtions [3] nd cn lso be divided into four sub-mtrices, s shown bove. nd D contin the self nd mutul impednce terms for the two circuits. However, the prmeters within nd D describe the inter-circuit coupling between the lines. Generlly, the line sequence impednces cn be obtined from the self nd coupling prmeters of the circuit s shown below: 0 = S + S = ( + + ) M = = S M M 3 = 6 ( ) where 0, nd re the zero, positive nd negtive sequence impednces, respectively. However, s most lines re not symmetricl, the ctul impednces observed t prticulr loction will lso depend mrginlly on the combintion of the fulted conductors nd the line geometry. Nevertheless, unblnced circuits result in coupling between the sequence prmeters. These coupling prmeters my be ignored on the ssumption tht they re smll reltive to the self impednces of the conductors, lthough this results in sequence impednces which re n verge of the ctul individul phse impednces. The ctul self nd coupling impednces in the sequence domin cn be found using the following reltionship: () () where = e j0. These vlues cn lso be rrnged in the digonlly symmetricl sequence mtrix. This conversion cn be pplied to phse domin,,, nd D mtrices defined bove to find the impednce vlues for dul circuit line comprised of circuits nd s shown below: E G F H Dul circuits represented in the sequence domin re similr to those in the phse domin, whereby the mtrices E nd H re the self nd coupling impednces in the sequence domin for circuits nd respectively, while G nd F re the coupling impednces between the circuits.. ircuit onstruction Different line configurtions will result in considerble vritions in the phse nd sequence impednces. Footing resistnce, erth resistivity, system frequency, trnsposition, the presence of erth wires nd coupling conductors re some of the gretest influences on this overll line impednce [7]. When there is more thn one circuit within n esement or on the sme supporting structures it is known tht the overll line impednce will vry in ccordnce to the phsing techniques used [7]. Low Rectnce Phsing High Rectnce Phsing Fig. Phsing geometry used in construction of dul circuit lines Fig. illustrtes two phsing geometry commonly used in construction of dul circuit lines. High rectnce phsing, s suggested by its nme, results in n overll circuit impednce which is greter thn tht observed for low impednce phsing, lthough low rectnce phsing is lmost lwys dopted on dul circuits. Erth wires lso ffect the self nd mutul impednces of trnsmission circuit. The self impednce is reduced proportionlly to the coupling between the phse nd erth conductors s well s the self impednce of the erthing conductor [7]. ssuming no tower footing resistnce, the self impednce S of phse conductor cn be expressed s [7]: (4)

4 3 S = E EE E (5) sizes, resulting in positive sequence line impednces for n untrnsposed cse of Ω nd residul compenstion fctor (RF) of Similrly, the mutul impednce M between phses nd under the presence of single erth wire cn be represented by [7]: E E M = (6) onsequently, there is reduction in both the self nd mutul coupling prmeters for the trnsmission circuit. In the sequence domin, this results in very smll nd lrge reduction in the positive nd zero sequence impednces respectively. ircuit trnsposition lso ssists by reducing the overll line impednce s well s the mismtch in the conductor loop impednces. There re generlly three trnspositions per circuit, which divide the line into sections of equl length. Generlly the loop impednce is reduced s the distnce between the two conductors decreses, nd when the presence of erth is neglected. Incresing the erth resistivity or the equivlent tower footing resistnce results in smller reductions in the zero sequence impednce of the circuit. Furthermore, nonhomogeneous tower erthing resistnce nd vritions in the substtion erth grid resistnces produce non-uniform zero sequence line impednces. Tble shows three simple dul circuit line configurtions of equl length. The line impednces were determined using the Line onstnts progrm within the lternte Trnsients Pckge (TP), showing tht the overll positive sequence loop impednce fluctutes with regrd to the phsing nd trnsposition scheme used. It should be noted tht only the phse-phse loop impednces hve been clculted in this simple cse, s considertion of the zero sequence impednce requires knowledge of dditionl vribles including the erth resistivity. TLE FULT LOOP IMPEDNES FOR VRIOUS IRUIT PHSING ND TRNSPOSITION ONFIGURTIONS WITH DUL IRUITS EE Fig. Simple dul circuit line topology exmined This scenrio ws then investigted using TP with distributed prmeter line model, nd four-wire sequence component equivlent or the source impednces. Defining the Source Rtio (SR) s the rtio of the positive sequence source impednces ( -Source / -Source ),.5 ws initilly chosen to identify ny resulting dependencies. The boundry forwrd rech setting hs been defined in [5] s the impednce vector normlized ginst the rely chrcteristic trip boundry. ll the pplied fults hve ssumed zero fult impednce. Subsequent studies hve demonstrted tht t EHV trnsmission voltges the rc impednce between two consecutive conductors results in miniml vrition to the following impednce plots. For ech of the following scenrios the fult position ws vried nd the boundry forwrd rech setting ws computed for ech of the distnce elements bsed on n idel offset mho chrcteristic with 00% forwrd rech.. Vritions in Dul ircuits pplying n phse (of line ) to phse (of line ) intercircuit fult to this dul circuit line will result in considerble under-rech for the phse elements, s shown in the impednce plot of Fig. 3. This lso shows the effects of inter-circuit fults on high nd low rectnce coupling (High, nd Low ). Such fults re unlikely on high rectnce lines due to the conductor geometry, s shown in Fig.. However, the clcultions hve been provided for comprison. The under-rech t the remote busbr for these high rectnce circuits is lso result of the coupling between the fulted conductors on one circuit reinforcing the fult loop on the prllel line. Un-trnsposed ircuit Trnsposed Loop Impednce Low Rectnce Phsing High Rectnce Phsing Low Rectnce Phsing - Fult Fult Fult III. INTER-IRUIT FULT NLYSIS To ssess the impct of inter-circuit fults on dul circuit lines, bse scenrio ws chosen s shown below. The simulted dul trnsmission circuits, shown in Fig., were 7 km in length nd ssumed low rectnce construction. This lso pplied to the conductor geometry nd Fig. 3 Phse element impednce plot for n un-trnsposed line Fig. 4 depicts the erth impednces with respect to offset mho erth elements set with forwrd t 00% of the line positive sequence impednce ( ). Nevertheless, with this

5 4 chrcteristic the rely erth elements will lso under-rech for these fults. It must lso be noted tht only one of the two circuits willl observe the impednces within the mho chrcteristic, s shown below. coverge when using mho elements. Fig. 7 onsidertion of erth impednce loci Fig. 4 Erth element impednce plot for n un-trnsposed line The line impednce is reduced when these circuits re trnsposed, lthough the only vritions when compred to the un-trnsposed cse pper to be fluctutions in loop impednce due to the symmetricl nture of the fulted sections s shown in Fig.5. Fult impednce ws considered in this nlysis. Due to the conductor geometry nd the resulting reltively low rc impednces present, no significnt chnge ws observed in the impednce plots. However, the erth impednce loci move further wy from the trip region of the mho chrcteristic.. Source Impednce onsidertions The effects of source impednce vrition on the phse elements cn be observed s shown in Fig. 8, where the fult position hs been vried long the line. Fig. 5 Phse element impednce plot for trnsposed line Similrly, the erth impednce with respect to the sme offset mho cn be seen in Fig. 6. gin the erth elements on only one of the two circuits will observe the impednces shown. Fig. 8 Impednces observed by phse elements for source impednce (SR) rtios of : nd :. Similrly the impednce loci result in greter under-rech t the weker source terminl for both the phse nd erth elements, when the source impednce is incresed bove unity, s shown in Fig.9. Fig. 6 Erth element impednce plot for trnsposed line Fig. 7 depicts the phse nd erth impednce loci for vritions in fult position, ginst two offset mho chrcteristics with forwrd rech of 00% nd 0% respectively. The mximum under-rech experienced by the phse elements occurs t pproximtely 80% of the line length. The erth elements, however, provide very little extr Fig. 9 Impednce loci observed from the weker source terminl However, the opposite occurs for the relying elements t the terminl with the stronger positive sequence source. The

6 5 under-rech mgnitude is reduced for the phse elements while the erth elements observe impednces similr to tht obtined with : SR, s illustrted in Fig.0. to the source impednce, the mximum phse element underrech remins fixed despite the generl under-reching mgnitude incresing for other fult loctions s shown in Fig.3. Fig. 0 Impednce loci observed from the stronger source terminl This is further portryed in Fig., which shows the erth impednces normlized ginst the idel mho chrcteristic trip boundry (the element is ssumed to hve 00% line forwrd rech). Fig. 3 Phse element impednce for : SR with vrition in the line impednce. Nevertheless, the erth elements observe fult impednces tht re more resistive thn those observed on long line, reltive to the line positive sequence impednce, s illustrted in Fig.4. Fig. Erth element impednce plot for mho rely with 00% forwrd rech. Similrly, Fig. considers the mgnitude of the phse element under-rech for vritions in the source impednce rtio. With lrge SR, the fult current is supplied predominntly from the strong source, which results in the distnce relys observing double phse to erth fult. onversely, the rely t the remote busbr must contend with the fult current infeed from the strong source thus producing lrge observed impednce. Fig. 4 Erth element for : SR with vrition in the line impednce. This pprent increse in fult resistnce cn be offset slightly when using fully cross-polrised mho erth elements. However, the dditionl resistive rech provided by such polristion remins smller thn the rte t which the erth impednce ppers to move from the origin of the impednce plot. D. Uncoupled Topologies ssuming hypotheticl cse whereby the previous dul circuit with n SR of.5 hs no mutul coupling between the respective circuits, the mgnitude of the under-rech observed by the phse elements is incresed gretly s shown in Fig.5. Fig. Mximum phse element under-rech observed for vritions in the source impednce rtio.. Line to Source Impednce Rtios In sitution where the line impednce is reduced reltive Fig. 5 Under-rech experienced by hypotheticlly uncoupled circuit

7 6 This rises questions with regrd to some common dul circuit topologies where two predominntly uncoupled circuits re intermittently strung on the sme structures. simple scenrio is shown in Fig. 6 where coupled circuits exist for substntil distnce from busbr, fter which different line esements re followed. Such cses my require specil protective techniques ginst inter-circuit fults on the coupled section. Fig. 6 Prtilly uncoupled dul circuit topology IV. PROTETION ONSIDERTIONS Detection of these fults using permissive under-reching scheme would require the fult to be observed by t lest one rely in one. onsequently t lest one of the impednce curves in, sy, Fig. 8 must exist below the one rech t ll loctions for the line to be dequtely protected. Similrly, neither of the impednce plots my extend beyond the one rech. one reches re usully set to 80% of the lowest impednce tht cn be observed for fults on the remote busbr. This my occur when the prllel circuit is out of service nd erthed t either end, resulting in one settings between 60-75% of the line impednce. onsequently, two permissive under-reching schemes re indequte for most dul circuit lines, s inter-circuit fults t mny loctions will not be observed. Permissive over-reching or blocking schemes require the fult to be observed within the one rech of the relys t ech line terminl. These one reches re commonly configured to 0% of the mximum impednce observed to the remote busbr. This my occur when both lines re in service producing overll zone reches of more thn 40% of the line impednce. However, inter-circuit fults on dul circuit with equl source impednces would require one rech of 50% or more for permissive overreching or blocking schemes. The required rech lso increses s the source impednce rtio shifts from unity. On long lines, the erth elements my be used for fult detection through the use of qudrilterl relys, however this cn only be chieved on circuits where the lod current is low. Since the resistive rech of such relys is usully limited to 3.5 times the rectnce vlue [8], this my provide little benefit on shorter circuits s the pprent erth fult impednce is extended further from the origin of the impednce plot. Generlly, protection implementtions designed to detect inter-circuit fults should only rely on the observtion of the phse impednce due to the bsence of ny erth return currents. Thus the one reches must consider the prospective worst-cse inter-circuit fult impednce, which is function of the positive sequence source impednce. urrent differentil schemes pper to be the only relible pproch to detecting these fults when pproprite one settings cnnot be obtined, or when single pole tripping is required. This cn be overcome by using t lest one current differentil scheme in conjunction with logic tht will trip the fulted phses only. Otherwise, ll six voltge nd current signls should be nlyzed by single rely to determine the fult condition, s is proposed in [9]. V. ONLUSIONS onventionl philosophies directing the use of distnce protection schemes for dul circuit lines my not enble the detection of unerthed inter-circuit fults in the instntneous zone of opertion. This is n essentil requirement in mny cses, including network interconnectors or lines crrying hevy or sensitive lods. To detect inter-circuit fults, t lest one permissive overrech or blocking scheme is required with one rech lrge enough to extend over the pprent impednces observed from ech line terminl. urrent differentil protection should be considered on t lest one of the circuits in situtions where n inter-circuit fult is deemed credible risk nd the source impednce rtio between the line termintions is significntly lrger thn unity, or if single pole tripping is employed. VI. KNOWLEDGMENT The uthors cknowledge the ustrlsin ommittee for Power Engineering, nd the mngement of Trnsgrid. VII. REFERENES [] Jongepier.G, vn der Sluis L, dptive Distnce Protection of Double-ircuit Line, IEEE Trnsctions on Power Delivery, Vol. 9, No 3, July 994, pp89-97 [] grsr M, Uriondo F, Hernández J.R, Evlution of uncertinties in double lines distnce relying. globl sight, IEEE Trnsctions on Power Delivery, Vol., No 4, July 998, pp [3] Glover S, Power System nlysis & Design, PWS Publishing ompny, oston 994 [4] Spoor D, hu J, Selection of distnce relying schemes when protecting dul circuit lines, ustrlsin Power Engineering onference, hristchurch, New elnd, 8 September October 003. [5] grsr M, Uriondo F, Hernndez J.R, lvrez R, useful methodology for nlyzing distnce relys performnce during simple nd inter-circuit fults in multi-circuit lines, IEEE Trnsctions on Power Delivery, Vol., No 4, October 997, pp [6] Turner S, est M, Wtnssirioch S, n ppliction in rely-to-rely logic communictions for single pole tripping, Proceedings of the 4 th interntionl conference on dvnces in power system control, opertion nd mngement, PSOM-97, Hong Kong, November 997, pp [7] lrke E, ircuit nlysis of - Power Systems Volume Symmetricl nd Relted omponents, John Wiley & Sons, Inc. New York 96 [8] Domzlski M.J, Nickerson K.P, Rosen P.R, ppliction of mho nd qudrilterl distnce chrcteristics in power systems, Developments in power system protection, onference Publiction No. 479, IEE 00, pp [9] McLren P.G, Fernndo I, Dirks E, Liu H, Swift G.W, Enhnced Double ircuit Line Protection, IEEE Trnsctions on Power Delivery, Vol., No 3, July 997, pp00-08

8 IOGRPHIES Drren Spoor ws born in Sydney, ustrli, in 978. He grduted from his undergrdute electricl engineering degree in 00 from the University of Technology, Sydney (UTS). urrently, he is completing his PHD studies t UTS, with strong focus in the res of protection nd fult loction for trnsmission circuits. 7 Dr. Jin Guo hu is n ssocite Professor nd director of the enter for Electricl Mchines nd Power Electronics t University of Technology, Sydney (UTS), ustrli. He received his E in 98 from Jingsu Institute of Technology, hin, ME in 987 from Shnghi University of Technology, hin, nd Ph.D in 995 from UTS, ustrli. His reserch interests re: electromgnetics, mgnetic properties of mterils, electricl mchines nd drives, power electronics, nd renewble energy systems.

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