Control and Implementation of a New Modular Matrix Converter

Transcription

1 1 ontrol nd Implementtion of New Modulr Mtrix onverter S. ngkititrkul nd R. W. Erickson olordo Power Electronics enter University of olordo, oulder oulder, O , US ngkitis@colordo.edu bstrct Implementtion of new modulr mtrix converter nd its control system re described. The converter consists of mtrix connection of cpcitorclmped Hbridge switch cells. The output of ech switch cell cn ssume three voltge levels during conduction. Input nd output threephse wveforms re synthesized from pulsewidth modultion of the D clmp cpcitor voltges. The spcevector modultion pproch cn be dpted to control this converter. control lgorithm is described tht cn be reduced to n equivlent Dlink converter. This controller is implemented using progrmmble logic devices nd flshmemory lookup tble. Opertionl wveforms re presented. I. INTRODUTION Multilevel conversion hs ttrcted significnt ttention, s wy to construct reltively highpower converter using mny reltivelysmll powersemiconductor devices [1 3]. This pproch hs the dvntges of reduced switching loss nd reduced hrmonic content of output wveforms. The pek voltges pplied to the semiconductor devices re clmped to cpcitors whose D voltges cn be controlled vi feedk, nd totl switching loss is reduced. When the input nd output voltge mgnitudes differ significntly, it is lso possible to reduce the conduction losses using multilevel techniques; this property cn improve the energy cpture of vriblespeed wind power systems. lthough multilevel conversion requires lrger pckging nd prts count, the totl silicon re cn in principle be reduced becuse of the reduced device voltge rtings. Thus, higher performnce is ttined t the expense of incresed control nd complexity. s the number of levels is incresed, the bus br structures of multilevel Dlink converter systems cn become quite complex nd difficult to fbricte. Severl uthors hve suggested solution to this problem through the use of voltgeclmped switch cells [4, 5], in which the voltges pplied to the semiconductor devices re loclly clmped to voltge sources. The difficulty with this pproch is tht the voltge sources of ech switch cell must generte the verge power supplied by the inverter, nd hence floting sources of D power re required. To ddress these issues, new fmily of modulr mtrix converters ws proposed in [6]. Voltgeclmped switch cells This work ws supported in prt by the DOE Ntionl Renewble Energy Lbortory under contrct no. XX re connected in mtrix configurtion s illustrted in Fig. 1. Ech switch cell consists of n Hbridge with D cpcitor whose voltge is controllble. The bus br structures of this modulr pproch re reltively esy to construct. The use of mtrix configurtion elimintes the need for D voltge sources tht supply verge power, nd hence the voltge sources re replced by simple D cpcitors. n i i i Threephse c system 1 b c i i b i c Threephse c system 2 Fig. 1: New modulr mtrix converter. D 1 D 2 Q 1 Q 2 D 3 D 4 Q 3 Q 4 Fig. 2: Hbridge switch cell with cpcitor. The new modulr converter is fundmentlly different from the conventionl mtrix converter [7, 8], s well s from the multilevel Dlink converter, in severl respects. It is cpble of both incresing nd decresing the voltge mgnitude nd frequency, while operting with rbitrry power fctors. The pek semiconductor device voltges re loclly clmped to D cpcitor voltge, whose mgnitude cn be regulted. The semiconductor devices re effectively utilized. Multilevel switching cn be used to synthesize the voltge wveforms N

2 TLE I: omprison of conventionl mtrix converter with new modulr mtrix converter. onventionl mtrix Proposed new modulr converter mtrix converter Voltge conversion uck: uckoost: rtio V out/v in V out.866v in V out < Switch oordintion of 4 Simple trnsistor plus commuttion qudrnt switches freewheeling diode us br structure omplex Modulr nd simple Multilevel opertion No Possible Filter elements cpcitors nd Inductors inductors t both the input nd output ports of the converter; switch cells cn be connected in series in ech brnch of the mtrix to increse the voltge rting of the converter. Switch commuttion is simpler thn in the conventionl mtrix converter. The new modulr mtrix converter nd the conventionl mtrix converter re compred in Tble I. The converter is cpble of incresing the number of level of opertion by connecting more thn one switch cell in series. For exmple, when two switch cells re seriesconnected in ech brnch s in Fig. 3. The converter cn operte with threend fourlevel switching. TLE II: Nineteen combintions of linetoline voltge, for the bsic converter configurtion. Threephse vribles DQ vribles V b V V c V d V q V cp V cp V 3 cp 2 V cp V cp 3 V cp V cp V 3 cp V cp V cp V cp 3 2 V cp V cp 3 V cp V cp V cp 3 2V cp V cp V cp 2V cp V cp V cp 2V cp V cp 3Vcp V cp 2V cp V cp V cp 3Vcp 2V cp V cp V cp 2V cp V cp V cp 2V cp V cp 3V cp V cp 2V cp V cp V cp 3V cp 2 2V cp 2V cp 2V 3 cp 4 2V cp 2V cp 3 2 2V cp 2V cp 2V 3 cp 2V cp 2V cp 2V cp V cp 2V cp 3 2V cp 2V cp 2V cp 2 3 n i i i Threephse c system 1 i Threephse c system 2 b N c proch cn be dpted for control of the proposed new modulr mtrix converters. For the bsic configurtion of Fig. 1, the instntneous linetoline voltges 2V cp, V cp,, V cp or 2V cp cn be produced, where V cp is the D cpcitor voltge of the switch cells. This leds to nineteen combintions of vlid blnced threephse linetoline voltges, s shown in Tble II. The linetoline voltges re trnsformed into dq vribles by the following eqution. [ vd (t) v q(t) ] = 2 3 [ cos() cos(12 ) cos(24 ) sin() sin(12 ) sin(24 ) ] vx(t) v y(t) v z(t) (1) i b qxis Fig. 3: onverter contining two switch cells in ech brnch of the switch mtrix. This pper documents lbortory prototype converter, long with mesured wveforms nd dt. control lgorithm is described tht is bsed on n equivlent Dlink converter. Pulsewidth modulted linetoline voltges re synthesized by switching the D cpcitor voltges of the switch cells. This lgorithm is implemented using progrmmble logic devices nd flshmemory lookup tble. The prototype switches t 5 khz, using hrdswitched 6 V IGTs. The switch modules re ssembled on printed circuit bords. II. PROPOSED ONTROL STRTEGY. Spce Vector Modultion The spce vector modultion pproch is wellknown technique for control of threephse converters [7]. This p i c (,4V cp /Ö3) (V cp, Ö3V cp ) (V cp,ö3v cp ) (2V cp, 2V cp /Ö3) (,2V cp /Ö3) (2V cp, 2V cp /Ö3) (V cp, V cp /Ö3) (2V cp, ) (V cp, V cp /Ö3) (2V cp, ) dxis (V cp, V cp /Ö3) (V cp, V cp /Ö3) (2V cp, 2V cp /Ö3) (,2V cp /Ö3) (2V cp, 2V cp /Ö3) (V cp, Ö3V cp ) (V cp, Ö3V cp ) (,4V cp /Ö3) Fig. 4: Nineteenspce vector generted by proposed converter

3 Figure 4 shows the corresponding spce vectors of ll nineteen combintions in the dq plne. These spce vectors hve four different mgnitudes:, 2V cp / 3, 2V cp nd 4V cp / 3. The inner ring of six lowmgnitude vectors, the first group in Tble II, nd the null spce vector cn be employed for twolevel switching. The outer ring of medium nd high mgnitude vectors cn be used for threelevel switching; however, in the bsic converter configurtion threelevel switching is restricted to voltge conversion rtios less thn 57% or greter thn 173%. This occurs becuse genertion of medium or highmgnitude spce vector on one side of the converter forces the other side to the null spce vector [6]. dditionl spce vectors re possible when multiple modules re plced in ech brnch of the mtrix. V d l V l d k V k f V k v ref V l 6 o Fig. 5: Spce vector modultion. The reference spce vector cn be expressed s liner combintion of three djcent spce vectors, two low mgnitude spce vectors nd the null spce vector, s illustrted in Fig. 5. It cn lso be described by the following eqution: v ref(t) =d k V k d l V l d V (2) where d k, d l nd d re duty cycles of V k, V l nd V, respectively, nd d k d l d =1 (3) y solving Eq. (2) nd (3), we obtin d k = V ref V k sin6 sinφ = 2 V ref 3 V k sin φ = V ref sin φ = M sin φ V cp d l = V ref V l sin 6 sin(6 φ) = = V ref sin(6 φ) =M sin(6 φ) V cp d =1 d k d l =1 Msin(6 φ) M = V ref V cp 2 3 V ref V l sin(6 φ). Singlepcitor ontrol Scheme When the converter synthesizes the input nd outputside voltges, there exist dditionl degrees of freedom tht cn be used to control the D cpcitor voltges. when the converter opertes with twolevel switching, only one cpcitor is needed in ech switching period. This pproch is optimized in sense of minimizing circulting current mong cpcitors. n extr degree of freedom tht cn be used to control the cpcitor voltge is the pttern of spce vectors in ech modultion period. To chieve the singlecpcitor control (4) Input side Output side Subintervl d _out TS d _in mx(d k_in, d l_in ) min(d k_in, d l_in ) mx(d m_out, d n_out ) min(d m_out, d n_out ) Fig. 6: The ordering pttern of input nd output spce vector for twolevel opertion. scheme, the pttern of Fig. 6 hs been used. onsider the cse where the input reference spce vector lies between spce vectors V k in nd V l in, nd the output reference spce vector lies between spce vectors V m out nd V n out. The spce vector modultion technique involves modultion mong inputside spce vectors V k in, V l in nd V in, with duty cycles of d k in, d l in nd d in respectively. Likewise, the outputside involves modultion mong output spce vectors V m out, V n out nd V out with duty cycles of d m out, d n out nd d out respectively. In ech switching period, for both the input nd outputsides, the pttern strts with the null spce vector then follows with the ctive spce vector tht hs mximum duty cycle, nd then ends with the ctive spce vector tht hs less duty cycle. This spce vector modultion control requires tht the switching period be divided into five subintervls. For ech combintion of input spce vector nd output spce vector, different set of cpcitors cn be employed. With the ordering pttern of input nd output spce vector, s in Fig. 6, there exists one cpcitor tht cn be employed to synthesize terminl voltges throughout the switching period. onsider the exmple in which the input reference spce vector lies between spce vectors V 3 in nd V 4 in nd the output reference spce vector lies between spce vectors V 1 out nd V 6 out, s shown in Fig. 7. The pttern of input nd output spce vectors in one switching period is shown in Fig. 8, nd the sets of cpcitors tht cn be employed for ech subintervl re lso shown. Notice tht cpcitor, from the switch cell tht is connected between input phse nd output phse, cn be employed throughout the switching period. Figure 9() summrizes how the converter (V cp, V cp /Ö3) V 3 fin Input reference voltge spce vector V 4 (V cp, V cp /Ö3) InputSide Spce Vector Digrm qxis V 2 V 5 V V 1 dxis V 6 V 3 V 4 OutputSide Spce Vector Digrm V qxis V 2 V 5 fout (V cp, V cp /Ö3) V 1 Output reference voltge spce vector dxis V 6 (V cp, V cp /Ö3) Fig. 7: ontrol exmple, t n instnt when the input nd output side reference spce vectors lie s shown.

4 Single cpcitor control Equivlent D link Linetoline voltges INPUT SIDE V = V V = V Phse V = V V = V Phse OUTPUT SIDE V b = V V c = V V = V rnch V c = Vcp V = V v v T s V cp V cp t V = Vcp V = Vcp Phse V = Vcp V = Vcp Phse V = Vcp V = V Phse V = Vcp V = V V = Vcp V c = Vcp V c = V V c = V V = Vcp () (b) (c) Fig. 9: Single cpcitor control technique () switch combintions of ech subintervl, (b) equivlent Dlink circuit, (c) the resulting input nd output wveforms. v v b v v c V cp V cp V cp V cp T S Input side Input V _in d Ts Input V 4_in d 4 Ts Input V 3_in d 3 Ts V 2 _c Output side Output V _out Output V 1_out Output V 6_out d Ts d 1 Ts d 6 Ts c c Subintervl Possible cpcitors tht cn be used c b b b c b c c b c V 3 _b b b b c V 1 _ Fig. 8: Ordering pttern of input nd output spce vectors with switch cell cpcitors tht cn be used in ech subintervl. is configured for ech subintervl. Figure 9(b) illustrtes the connections in n equivlent D link converter tht genertes identicl spce vectors. The instntneous input nd output linetoline voltges for both converters re illustrted in Fig. 9(c). Selection of the switchcell cpcitor to be employed during given switching period is bsed on the directions of the reference spce vectors, s well s reltive vlues of the duty cycles for the input nd outputside null spce vectors. Figure 1 summries the result, for the cse d out <d in. different switchcell cpcitor is selected for every 6 of the outputside line cycle, nd for every 12 of the inputside line cycle. The sitution is reversed when d out >d in.it should be noted tht, when the reference vector coincides with V 4 _ c V 5 c c _c b b b V 6 _b Fig. 1: Summry of switchcell cpcitor choice, for the cse of d out <d in. The lrge (outer) spce vector digrm represents the output side, with 6 segments. When the 6 segment is shded, then the positive side of V cp is pplied to the respective output terminl. The smller superimposed spce vector digrms represent the input side, with 12 segments. The cse d out >d in is symmetricl, with the input nd output sides interchnged.

5 one of the converter spce vectors V 1, V 2,..., V 6, then the corresponding linetoneutrl voltge v n, v cn, v bn, v n, v cn, v bn, ttin their pek vlues. Thus the singlecpcitor control scheme employs the cpcitor from the switch cell tht is connected between the input phse nd output phse tht hve the lrgest opposite polrity linetoneutrl voltges. For exmple, suppose tht d out is less thn d in. If v ref out (t) lies within ±3 of the converter spce vector V 3, nd hence the outputside linetoneutrl voltge v bn (t) is within ±3 of its pek positive vlue for the output line cycle. Therefore we choose one of the three cpcitors connected to the output phse b: either b, b or b. Next, the input side is exmined. To nrrow the choice to single cpcitor, we select the phse hving the lrgest negtive vlue, of opposite polrity to output side. Three of the six converter spce vectors led to negtivepolrity input spce vector: V 2, V 4 nd V 6 correspond to negtive v N, v N nd v N, respectively. The converter spce vector tht lies closest to (within ±6 ) of the input reference spce vector is selected. For instnce, if the inputside reference spce vector lies between converter spce vectors V 4 nd V 5, then it is closest to converter negtive spce vector V 4, nd so input phse exhibits the most negtive linetoneutrl voltge. Therefore, cpcitor b is employed.. Eightpcitor ontrol Scheme For comprison, the eightcpcitor control scheme is lso described. In this control scheme, ll nine brnches conduct currents t ny given time nd cpcitors re llowed to be V = V V = V V = Vcp V = Vcp V = V V = V Phse V = V Phse V = V V = Vcp Phse V = Vcp Phse V = Vcp Phse V = Vcp V b = V V = V V = V V = V V = Vcp V = Vcp V c = V V c = Vcp V c = Vcp V c = V V c = V Fig. 11: onfigurtion tht used multiple cpcitor connected in prllel. connected in prllel during ech subintervl of Fig. 6. The redundnt switch combintions re employed in such wy tht the number of conducting cpcitors is mximized. In one switching period, the converter employs eight of nine cpcitors (three, four or five cpcitors re employed in ech subintervl). This modultion scheme is relted to the singlecpcitor control scheme of Figs. 8 nd 9 in tht the subintervls, spce vectors, nd instntneous linetoline voltge wveforms, re identicl. The voltges cross the nonconducting brnches of Fig. 9() re determined; those brnches blocking zero volts re switched to the shorting stte, while those brnches tht block voltge ±V cp re turned on with their cpcitors connected with the correct polrity. The switching pttern of Fig. 11 is obtined. lose exmintion of Fig. 11 revels tht the cpcitor of brnch b is never employed. With this modultion pproch, exctly eight of the nine cpcitors prticiptes during ech complete switching period. To the extent tht the cpcitor voltges remin blnced, this scheme cn improve efficiency by distributing the currents over ll nine brnches. It lso hs the dvntge tht the effective cpcitnce is incresed, nd hence cpcitor voltge ripple is reduced, nd lso tht the cpcitor voltge control is reduced to single control loop. The disdvntge is tht high pek currents cn occur if the cpcitor voltges re unblnced. Efficient opertion of this scheme requires tht the mechnisms tht drive cpcitor voltge imblnces (primrily from the energy stored in stry inductnces of the interconnections between switch cells) be minimized. III. IMPLEMENTTION block digrm of the control system is shown in Fig. 12. The input nd output voltges nd currents re sensed by Hll effect devices, nd re digitized using nlogtodigitl converters (D). The microcontroller trnsforms these into dq coordintes, s in Eq. (1). The D cpcitor voltges of the nine switch cells re lso mesured using differentil mplifier circuits, nd digitized using D s. The microcontroller performs the spce vector modultion, Eq. (4), nd chooses the cpcitor for the singlecpcitor control scheme. The microcontroller is interfced to the switch cells through complex progrmmble logic devices (PLDs). The PLDs re ddressble by the microcontroller, nd store the current sttes of ll switches. In ddition, the sttes of ll switches during the next subintervl cn be loded into the PLDs. The PLDs implement the functions of timing nd pulsewidth modultion. The cpcitor nd spce vector dt re decoded by lookup tble to generte the stte of ech switch cell. These dt re further decoded by other PLDs into the gte signls for the IGTs. To void crossconduction of the IGTs during their switching trnsitions, which would led to momentry shorting of the D bus voltges through the IGTs, the turnoff trnsitions of the IGTs occurs first. In other words, those IGTs tht were previously on, but will be turned off, re switched first. fter controllble dely, the turnon trnsitions re triggered (i.e., the IGTs tht were previously

6 } } Voltge nd current sense circuits / onverters 4 MHz Microproceesor updte dt every 1 msec Lod vlues of four duty cycles per sw period Lod vlues of spce vectors for ech of 5 intervls pcitor # lock 25 MHz Timer (PLD) 4 ns resolution for ech intervl Dt buffer (PLD) ode representing present intervl ompenstes for ltency of flsh memory Dely Lookup tble (Flsh memory) onverters spce vectors to switch sttes Lookup tble (Flsh memory) onverters spce vectors to switch sttes Sets ded time to ensure nonoverlpping conduction Delys implemented within timer PLD Turn off Dely Turn on Switch cell control (PLD) Switch cell control (PLD) To optoisolted gte driver To optoisolted gte driver Phse Highlevel control lgorithm Spcevector control of converter currents Fieldoriented control of genertor 19 bit dt bus representing present input nd output spce vectors nd cpcitor # Lookup tble (Flsh memory) onverters spce vectors to switch sttes Switch cell control (PLD) Decoding logic rek before mke logic lternting conduction logic To optoisolted gte driver Fig. 12: lock digrm of the control system. off, but will be turned on, re switched). The gte signls from the PLDs re sent through optoisolted gte driver circuits to the IGTs in power stge. IV. EXPERIMENTL RESULTS prototype ws constructed to demonstrte the vlidity of the control strtegy. The prototype ws connected to the 6 Hz utility, nd trnsferred power to resistive lod. The input linetoline voltges re sensed nd used s the reference input spce vector. The output spce vector ws progrmmed in the microcontroller. The converter operted t switching frequency of 5 khz. Figures 13 to 15 show the wveforms for opertion with the singlecpcitor control scheme. The converter ws progrmmed to produce n output frequency of 3 Hz, with Fig. 14: Wveforms from singlecpcitor control scheme: cpcitor voltge nd 3 Hz output voltge Fig. 13: Input nd output wveforms for the singlecpcitor control scheme. Trce 1: 6 Hz linetoline voltge t input terminl. Trce 2: 6 Hz input current. Trce 3: 3 Hz linetoline output voltge. Trce 4: 3 Hz output current. Fig. 15: Wveforms from singlecpcitor control scheme: cpcitor voltge nd filtered 3 Hz output voltge.

7 input modultion index, M in = V ref in /V cp, of.94 nd output modultion index, M out = V ref out /V cp, of.87. Figures 16 to 18 show the wveforms when the converter operted with the eightcpcitor control scheme. The converter ws lso progrmmed to produce the sme operting point s in the singlecpcitor control scheme cse. Fig. 16: Input nd output wveforms for the eightcpcitor control scheme. Trce 1: 6 Hz linetoline voltge t input terminl. Trce 2: 6 Hz input current. Trce 3: 3 Hz linetoline output voltge. Trce 4: 3 Hz output current. Fig. 17: Wveforms from multiplecpcitor control scheme: cpcitor voltge nd 3 Hz output voltge V. ONLUSION The lbortory experiment proves tht the proposed new modulr mtrix converter is vlid nd opertes s climed. Spce vector control of both the input nd output side hs been implemented, to convert given threephse input into threephse output of given desired frequency, mgnitude, nd phse. With both the singlecpcitor control scheme nd the multiplecpcitor control scheme, it ws observed tht the cpcitor voltges nturlly remined blnced nd stble. The converter operted with n IGT switching frequency of 5 khz. REFERENES [1]. Nbe, I. Tkhshi, nd H. kgi, New NeutrlPoint lmped PWM Inverter, IEEE Trns. on Industry pplictions, vol. I17, pp , Sep./Oct [2] P. hgwt nd V. Stefnović, Generlized Structure of Multilevel PWM Inverter, IEEE Trns. on Industry pplictions, vol. I19, pp , Nov./Dec [3] L. M. Tolbert nd F. Z. Peng, Multilevel onverter for Lrge Electric Drives, IEEE pplied Power Electronics onference, vol. 2, pp , [4]. Lin, Y. hien, nd H. Lu, Multilevel Inverter with Series onnection of Hridge ells, IEEE Interntionl onference on Power Electronics nd Drive Systems, pp , Jul [5] F. Z. Peng, J. S. Li, J. McKeever, nd J. Vnoevering, Multilevel VoltgeSource Inverter with Seprte D Sources for Sttic VR Genertion, onf. Rec. of IEEE IS nnul Meeting, vol. 3, pp , Oct [6] R. W. Erickson nd O.. lnseem, New Fmily of Mtrix onverters, IEEE Industril Electronics Society nnul onference (IEON 1), vol. 2, pp , Nov./Dec. 21. [7] L. Huber nd D. orojević, Spce Vector Modultion ThreePhse to ThreePhse Mtrix onverter with Input Power Fctor orrection, IEEE Trns. on Industry pplictions, vol. 31, Nov./Dec [8] J. Oym, T. Higuchi, E. Ymd, T. Kog, nd T. Lipo, New ontrol strtegy for Mtrix onverter, IEEE Power Electronics Specilists onference, pp , Fig. 18: Wveforms from multiplecpcitor control scheme: cpcitor voltge nd filtered 3 Hz output voltge.