Hierarchical Extreme-Voltage Stress Test of Analog CMOS ICs for Gate-Oxide Reliability Enhancement*

Transcription

1 Hierarhial Extreme-Voltage Stress Test of Analog MOS Is for Gate-Oxide Reliability Enhanement* hin-long Wey Department of Eletrial Engineering National entral University hung-li, Taiwan M. A. Khalil Department of Eletrial and omputer Engineering Mihigan State University East Lansing, MI Jim Liu Department of Eletrial and omputer Engineering Mihigan State University East Lansing, MI Gregory Wierzba Department of Eletrial and omputer Engineering Mihigan State University East Lansing, MI ABSTRAT Yield and reliability are two fators affeting the profitability of semiondutor manufaturing. High-temperature burn-in and extreme-voltage stress tests are two urrent industrial standard methods to speed up the deterioration of eletroni devies and weed-out infant mortality. Extreme-voltage stress test aims at enhaning both quality and reliability without performane the high-ost burn-in test proess. Our reent stress tests of analog/mixed signal MOS Is for gate-oxide reliability enhane. This paper presents a ontrol flow model for analog MOS iruits and uses it to develop a iruit partition sheme. A pratially large analog iruit an be partitioned into many smaller sub-iruits so that the developed stress vetor generator and stressability analyzer an onformably handle in term of omputational omplexity. In addition, a struture-based stress vetor generation proess is also developed. Stress vetors are generated based on the iruit topologial struture without performing iruit simulations. The performane improvement proposed in this study an signifiantly redue the omputational omplexity so that the developed stress test system an handle pratially large analog MOS iruits. ategories and Subjet Desriptors B..3 [Reliability and Testing]: Built-in tests, Test generation and Testability. General Terms Reliability. Keywords I Reliability. *This work is supported in part by the National Siene Foundation under the grant number R-9853, and in part by the National siene ounil, Taiwan, under the grant number 9-8-E-8-8. Permission to make digital or hard opies of all or part of this work for personal or lassroom use is granted without fee provided that opies are not made or distributed for profit or ommerial advantage and that opies bear this notie and the full itation on the first page. To opy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speifi permission and/or a fee. GLSVLSI 4, April 6-8, 4, Boston, Massahusetts, USA. opyright 4 AM /4/4...$5... INTRODUTION Yield and reliability are two fators affeting the profitability of semiondutor manufaturing[]. In the manufaturing proess of modern VLSI semiondutor devies, plasma is often used to deposit or remove material on wafers[,3]. The plasma may ause destrutive harges to be built on the wafers. If the harge buildup is large enough, and the harge has no other leakage path to substrate, a urrent flows through the onneted transistor gate oxide, ausing degradation of the gate oxide. The damaged gate oxide may result in performane degradation of the affeted transistor and ause reliability failures. Thus, oxide defets have been found as one the major auses for the reliability problems for MOS Is[4-]. Stressing testing is a tehnique used to weed-out infant mortality by applying higher than usual levels of stress to speed up the deterioration of eletroni devies. The onept of this sreening proess id to aelerate the lifetime of devies suh that they begin operation with a failure rate beyond the infant mortality region. The industry standard methods for sreening have been high-temperature burn-in [8-] and high-voltage sreening [- 4]. Burn-in is effetive in varying degrees for almost all iruits and assembly auses of premature failure. Burn-in sreening dereases failure rate of a produt during the early life, where overall ost and turn around time are of onerns. The added manufaturing ost may range from 5% to 4% of the total produt ost, depending on the burn-in time, qualities of Is, and produt omplexity. High-voltage sreening, or referred to as extreme-voltage sreening, aims at improving the quality level of MOS Is without performing the high-ost burn-in proess. Extremevoltage sreening has been implemented to enhane gate-oxide reliability of digital MOS Is. Reently, the sreening tehniques have been suessfully developed and applied for endangering reliability of analog iruits [3,4]. omputational omplexity is always a major onern for large analog iruits, but an be handled using hierarhial approah. In this study, a iruit-partitioning sheme based on a ontrol flow model of MOS iruits is used to develop the hierarhial approah. Analog only systems and analog portion of mixedsignal systems are not generally haraterized by having a large number of iruit elements. However, the optimization of the analog design using the basi iruit elements (amplifiers, filter networks, omparators, et.) is muh more speialized and requires a great deal experiene and knowledge. Therefore, most designers use whether possible predesigned ommerially 3

2 available iruit elements for the system design. For suh ases, eah iruit element an be applied in a hierarhial fashion. Based on the stress test generation and stressability analysis proesses developed in [4], Setion presents the struturebased stress vetor generation proess, while the hierarhial approah is disussed in Setion 3. Finally, a onluding remark is given in Setion4.. Struture-based Stress Vetor Generation This study employs a simple ontrol-flow model for the development of the struture-based stress vetor generation proess. The model is used to partition analog MOS iruits. In order to demonstrate the effetiveness of the struture-based generation proess, the following operational transondutane amplifier (OTA) iruit, as shown in Figure, is used as an example. Based on the iruit simulation-based generation proess, the stress vetors, stress time, stressability analysis results, and overage harts of that iruit an be found in [4]. M6 n M M n5 M8 M Figure. The OTA iruit.. ontrol-flow Model For a MOS network, the drain iruit and gate voltage are two major parameters in its D analysis. A MOS network an be desribed by a flow graph and a ontrol graph, where former represents the urrent flow of the iruit, while the latter desribes the gate ontrol voltage. More speifially, the flow graph is P Vin- P M3 VBias P3 Vin+ M5 M4 Vout M9 Level Level Level onstruted by onverting eah three-terminal MOS transistor in a MOS iruit network into a two-terminal devie, where the gate onnetion of eah transistor is removed, as shown in Figure (a) fro the OTA iruit. A valid path is defined as a path that travels form V dd to V ss. Both V dd and V ss are referred to as terminal nodes and the others are primary modes. A simple path-partitioning sheme is developed to partition a flow graph using the following simple rules: Rule: Any valid paths, whih share at least, a primary node will be in the same partition. Rule: A valid path forms a partition if it does not share a primary node with others. The iruit in Figure (a) ontains four valid paths, and, by both rules, it an be divided into three partitions, namely P, P, and P3. A primary node of a partition is alled a ontrolling node if it onnets to at least one gate of a transistor in the other partition, e.g. node in P, nodes n5 and n in P. The flow A B: in the flow graph, as shown in Figure (b), means a ontrolling node in Partition A onnets to the gate of the transistor in Partition B. A primary partition is the one, whih is not ontrolled by any other partitions, e.g., P. Note that bias generator iruits are often used in analog iruit. The iruits take no primary inputs, but their outputs are preditable and referred to as primary-like inputs. A partition inluding the primary and/or primary-like input is also referred to as a primary partition. A sequene level is assigned to eah partition. The primary partitions are labeled as Level. A partition is labeled as in Level k if the highest level of its inputs is Level (k-). For example, as shown in Figure (b), the primary partition P is in Level. The partition P3 has two inputs and n5, whih ome form P (in Level ) and P(in Level ). Thus, P3 is in Level. Figure () shows the iruit partitions resulted from the original iruit in Figure.. Stress Vetor Generation Proess For simpliity of disussion, we first onsider a simple iruit with a single valid path, as shown in Figure (a), onsisting of r asaded transistors TR s, i=,,,r, and eah transistor, NMOS i P P P3 n M6 n M M M8 n n5 Vout P P P3 Vou n Vin- M3 Vin+ n5 M4 n5 nx Vout Vbias (b) n5 M Vbias M5 M9 (a) Figure : OTA iruit: (a) Flow Graph; (b) ontrol Graph; and () iruit Partitions. () 33

3 or PMOS, has an input IN j, j=,,,r. A primary node PNj is loated between two transistors TR j and TR j+. Without loss of generality, the primary nodes are lined up and labeled in an asending order, where let PN = V ss and PN r = V dd. Thus, the transistor TR j is loated between nodes PN j and PN j. This iruit an be viewed as a number of NMOS or PMOS swithes onneted in series. The following property onludes. Property. (a). The voltage at node PN is j V ss if the transistors TR i, i=,,,j, are all ON and at least one TR i,i=j+,,r, is OFF. (b). The voltage at node PN j is V dd if the transistors TR i, i=j+, r, are all ON and at least one TR i, i=,,,j is OFF. Note that an NMOS transistor is turned ON and OFF by applying V dd and V ss to the gate terminal, respetively. Similarly, a PMOS transistor is turned ON and OFF by applying V ss and V dd to the gate terminal, respetively. Diode-onneted transistors are very often used as a resistor in analog iruits, where a diode-onneted transistor onnets its gate to its drain or soure terminal. Property also holds when the partition ontains some diode-onneted transistors. andidate Vetors IN4 IN3 TR4 PN3 TR3 Regions IN IN3 IN4 GS(TR) x x GB(TR) x x onsider the ase that a iruit ontains a single valid path with a diode-onneted transistor, say, TR r, whih takes no other input to its gate terminal. To properly stress the GS region of TR r, its gate voltage at node PNr- must be V dd and its soure voltage at node PNr-3 is V ss. By property (a), the voltage at node PN r 3 is V ss if all TR i,i=,,,r-3, are ON, and either TRr or TR r is OFF. By property (b), the voltage at node PNr- is V dd if both TR r and TR r are ON, and at least one TR i, i=,,,r-3, is OFF. As a result, both onditions are onfliting to eah other. It is virtually impossible to make PN r = V dd and PN r 3 = V ss due to the diode-onneted struture. However, when all transistors TR i s, i=,,,r-,r-,r, are ON, the maximum urrent of that iruit ours. This results that the diode-onneted transistor has the maximum voltage aross its gate and soure terminals. The following property results. Property onsider a iruit ontaining a single valid path with diodeonneted transistors, the regions GS (or SG) and GD (or DG) of a diode-onneted transistor are fully stressed if all non-diodeonneted transistors in the valid path are turned ON. Stress onditions Derived Vetors Regions IN IN3 IN4 PN PN PN3 IN IN3 IN4 GS(TR) PN GD(TR) x GB(TR) IN TR PN TR x GS(TR) GD(TR) GB(TR) (a) GD(TR) x x x GS(TR3) GS(TR) GB(TR) Primary Vetors GB(TR3) x x GD(TR) IN IN3 In4 (b) GD(TR3) GS(TR4) x x GB(TR4) x x GD(TR4) () Figure 3: Stress Vetor Generation: (a) Example iruit; (b)stress onditions & Derived Vetors, ()Valid Vetors; and (d) Primary Vetors. x x GS(TR3) GB(TR3) GD(TR3) GS(TR4) GB(TR4) GD(TR4) 34

4 Both Properties and are used to generate the primary stress vetors for the iruits with a single valid path. onsider a iruit with a single path shown in Figure 3(a), where the iruit ontains 4 transistors, 3 primary nodes, and 3 inputs. TR is a diode-onneted NMOS transistor. By property (a), the voltage at node PN is V ss if TR is ON, i.e., V IN = V dd, and either TR 3 or TR 4 is OFF, i.e., V IN3 = V ss or V IN 4 = V dd. Similarly, the voltage at node PN 3 is V dd, by Property (b), if TR 4 is ON, i.e., V IN 4 = V ss, and either TR or TR 3 is OFF, i.e., V IN = V ss or V IN3 = V ss. The first step of the stress vetor generation proess is to tabulate the required onditions for fully stressing the regions of all transistors in that iruit. The first olumn in Figure 3(b) lists all regions of the transistors in Figure 3(a). The next step is to define the stress onditions for eah region. The stress onditions ontain two parts, one for the inputs and the other for the primary nodes. More speifially, to fully stress an NMOS transistor, the node voltages are ( V D, V G, V S )=(,,). Similarly, ( V D, V G, V S )=(,,) for a PMOS transistor. Note that the V y =() means that V y reahes the maximum (minimum) D voltage of the node y= D, G, S [4]. For example, to fully stress the region GD of the NMOS transistor TR, the required onditions are V G = V IN = and V D = V PN =. Similarly, for the regions GS of TR 3, the onditions are V G = V IN3 = and V S = V PN =. Note that no stress onditions are onsidered for both GS (or SG) and GD (or DG) regions of the diode-onneted transistors, suh as TR. One all stress onditions are defined, the next step is to derive the required stress vetor(s) from those for the primary nodes using Properties and. Note that the derived ondition must agree with those generated from the inputs. In other words, a derived ondition is invalid if it onflits to a ondition generated from the inputs. For example, for the region GD of TR, the stress ondition is V G = V IN = and V D = V PN =. By Property (a), we an obtain V D = V PN = by setting TR to be ON, and TR 3 or TR 4 to be OFF, i.e., V IN = and ( V IN3, V IN 4 )=(,),(,),or (,), or ( V IN3, V IN 4 )=(,x) or (x,), where x means don t are and an be either or. Similarly, the stress ondition for the region GS of TR 3 is V G = V IN3 = and V S = V PN =.The ondition V S = V PN = results that V IN =, and ( V IN3, V IN 4 )=(,),(,), or (,). However, the derived vetors ( V IN, V IN3, V IN 4 )=(,,) and (,,) have V IN3 = that onflits the generated ondition V IN3 =. Thus, only the stress vetor ( V IN, V IN3, V IN 4 )=(,,) is valid. Finally, for the region GS( TR ), by Property, the valid stress vetor is ( V IN, V IN3, V IN 4 )=(,,). The table in Figure 3() lists the valid stress vetors for all regions of the transistors in Figure. The stress vetors are referred to as the andidate stress vetors. One the andidate stress vetors for all regions of the transistors in a iruit are derived properly, the final step is to minimize the set of stress vetor, i.e., the primary stress vetors. The minimal set of stress vetors guarantee to fully stress all regions. Simple rules in the minimal overing problem an be used to derive the minimal set. Figure 3(d) illustrates the set of 3 primary stress vetors. The resultant primary stress vetors are exatly the same as those generated by the simulation-based approah [4]. The struture-based stress vetor generation proess an also be generalized for the iruits with more than one valid path. Basially, if a iruit ontains more than one valid path, only one valid path is ativated at a time and the remaining paths are disabled. Thus, the iruit is equivalent to ontaining only one valid path. Figure 4 illustrates the resultant stress vetor generation for the partitions P, P, and P3 of the OTA iruit. Primary Vetors n Output (a) P (b) P Primary Vetors Output n5 nx Primary Vetors () P3 Figure 4: Primary Vetors and Assoiated Outputs. Outputs Vbias Vin- Vin+ n5 n 3. Hierarhial Approah A iruit partition sheme using the ontrol-flow model was introdued in Setion 3. to partition an analog MOS I into a number of smaller partitions, whih an be omfortably handled, by both stress vetor generator and stressability analyzer. This setion presents both hierarhial stress vetor generation and stressability analysis proesses. 3. Hierarhial Stress Vetor Generation Realled that a primary partition is the one, whih is not ontrolled by any other partitions. The primary inputs are the inputs to the original iruit, and a primary-like input is the output 35

5 Vbias Vin+ Vin- 3 4 Number of regions olumn stress time : M_DG; :M_GS, M_GB 3:M6_SG,M6_BG;M6_DG. (a) P Vbias Vin+ Vin- 3 Number of regions olumn stress time :M_DG,M_DG; :M5_GS,M5_GB; 3:M5_Gd; 4:M3_GB; 5:M4_GB; 6:M3_GS; :M4_GS; 8:M_SG,M_BG,M3_GD; 9:M_SG,M_BG,M4_GD. (b) P of a module that takes no inputs. Therefore, a primary partition takes either the primary inputs or the primary-like inputs as its inputs, and a non-primary partition may take either the primary inputs, or the primary-like inputs, or others, referred to as the nonprimary inputs, as its inputs. Based on the distribution of the primary inputs, two ases an be identified:(a).all these inputs are distributed to the primary partitions; and (b). Some of these inputs are onneted to the nonprimary partitions. For the former ase that all the primary inputs are onneted to the primary partitions, the primary stress vetors of the original iruit will be the ombinations of those for the primary stress vetors for the primary partitions. Therefore, we need only to generate the primary stress vetors for the primary partitions. onsider the OTA iruit in Figure, it is deomposed into three partitions P, P, and P3, as shown in Figure (). Aording to the ontrol graph in Figure (b), P is the primary partition and it takes all the primary inputs. Thus, we need only generate the primary stress vetors for P. Figure 4(b) shows the primary stress vetors of P and they are also the primary stress vetors of the OTA iruit. For the later ase that some of the primary inputs are onneted to the non-primary partitions, the primary stress vetors for the original iruit is derived from the ontrol graph. More speifially, without loss of generality, assume that the highest level of the non-primary partition, whih takes the primary Vbias Vin+ Vin- 3 3 Number of regions 3 3 olumn stress time :M9_GS,M9_GD,M9_GB; 3:M8_SG,M8_DG,M8_BG. () Vbias Vin+ Vin- Number of regions olumn stress time =+; =;3=3;4=4;5=5;6=6;=; 8=+3;9=8+3;=9+3;=4. (d) Figure5: Stressability Analysis for the OTA: (a)-() for Partitions; and (d) for Entire iruit. input(s), is in Level k. These partitions are referred to as L(k)- partitions. In this ase, we only need to generate the primary stress vetors for those partitions whose level is less than k, and for L(k)-partitions. A bakward traking proess is used to ombine the primary stress vetors for the original iruit. The bakward traking proess starts with the primary stress vetors of the L(k)- partitions. Based on these primary stress vetors in Level k, i.e., the output of the partitions in the Level(k-), we trak the required inputs for the partitions in Level (k-). The bakward traking proess is ontinued to Level (k-). The proess is repeated to Level and results the primary stress vetors for the original iruit. Aording to this bakward traking proess, for those partitions whose level is less than k, but their outputs do not ontribute to L(k)-partitions, we don t need their primary stress vetors and thus we don t need to generate their primary stress vetors. 3. Hierarhial Stressability Analysis Based on the seleted stress vetors, the stress time alulation proess [4] is employed for all partitions. The stress times of the primary partitions in Level are first alulated, and the remaining partitions are proessed in the sequene of their levels in the ontrol graph. However, the partitions in the same level an be proessed simultaneously. 36

6 For example, we first apply the primary stress vetors of the OTA iruit to the primary partition P, the stressability analysis results are tabulated in Figure 5(a). the iruit simulations are onduted for the primary stress vetors with the normal and stress supply voltages, respetively, for the stress time alulation. Similarly, the stressability analysis results for P and P3 are shown in Figure 5(b) and 5(), respetively. The stressability analysis result of the original iruit an be obtained by merging those for all its partitions. More speifially, tow olumns will be merged if they have the same olumn data and stress time. For example, in Figure 5(a), the olumn for P and for P have the same olumn in Figure 5(d) and the number of the regions are aumulated. Similarly, olumn for P and 3 for P3 are merged as 8 in Figure 5(d). As a result, Figure 5(d) is the stressability analysis result for the original OTA iruit. 4. onlusion This paper presents a ontrol flow model for analog MOS iruits and uses it to develop a iruit partition sheme. A pratially large analog iruit is partitioned into many smaller sub-iruits so that the developed stress vetor generator and stressability synthesizer an omfortably handle in term of omputational omplexity. This paper also presents a struturebased tehnique for stress vetor generation. The primary stress vetors are generated from the iruit struture without performing iruit simulations. Both hierarhial approah and struture-based stress vetor generator an signifiant redue the omputational needs for stressing analog iruits. 5. REFERENES [] T. Kim and W. Kuo, Modeling Manufaturing Yield and Reliability IEEE Trans. On Semiondutor manufaturing. Vol., No.4 pp , November 999. [] P. Simon, J. M. Luhies, and W. Maly, Identifiation of Plasma-Indued Damage onditions in VLSI designs IEEE Trans on semiondutor manufaturing. pp.36-44, vol. 3, no. May. [3] T. Brozek, V. R. Rao, A. Sridharan, J. D. Werking, Y. D. han, and. R. Viswanathan, harge Injetion Using Gate- Indued-Drain-Leakage urrent for haraterization of Plasma Edge Damage in MOS Devies IEEE Trans. On semiondutor manufaturing, pp.-6, vol., no, May 998. [4] E. R. Hnatek, Integrated iruits Quality and Reliability Marel Dekker, In., 995. [5]. F. Hawkins and J. M. Soden, Eletrial harateristis and Testing onsiderations for Gate Oxide Shorts in MOS Is Pro. International Test onferene, Philadelphia, PA, pp , 985. [6]. F. Hawkins and J. M. Soden, Reliability and Eletrial Properties of Gate Oxide Shorts in MOS Is Pro. International Test onferene,, pp , 986. [] M. H. Woods, MOS VLSI Reliability and Yield Trends Proeedings of IEEE, vol. 4, pp.5-9, Deember, 986. [8] T. Barrette, ET. Al., Evaluation of Early Failure Sreening Methods International Workshop on IDDQ Testing, Washington, D, pp.4-, 996. [9] R. Kawahara, O. Nakayama, and T. Kurasawa, The Effetiveness of IDDQ and High Voltage Stress for Burn-in Elimination International Workshop on IDDQ Testing, pp.9-3, 996 [] A.W. Righter,. F. Hawkins, J. M. Soden, P. Maxwell, MOS I Reliability Indiators and Burn-in Eonomis Pro. International Test onferene, pp.94-3, 998. [] T. Y. J. hang and E. J. Mluskey, SHOrt Voltage Elevation(SHOVE) Test for Weak MOS Is Pro. VLSI Test Symposiums, pp , 99. [] T. Y. J. hang and E. J. Mluskey, SHOrt Voltage Elevation (SHOVE) Test, IEEE International Workshop on IDDQ Testing, pp.45-49, 996. [3] M. A. Khalil and. L. Wey, High-voltage Stress Test Paradigms of Analog MOS Is for Gate-Oxide Reliability Enhanement International VLSI Test Symposiums, pp ,. [4] M. A. Khalil and. L. Wey, Extreme-Voltage Stress Vetor Generation of Analog MOS Is for Gate-Oxide Reliability Enhanement International Test onferene, September. 3