Digitally Demodulating Binary Phase Shift Keyed Data Signals

Transcription

1 Digitally Demodulating Binary Phase Shift Keyed Signals Cornelis J. Kikkert, Craig Blakburn Eletrial and Computer Engineering James Cook University Townsville, Qld, Australia, Abstrat This paper desribes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By inorporating both I and Q data in the demodulation proess, a signifiant improvement in performane is obtained. Computer simulation shows the Bit Error Rate (BER) performane versus Reeived Carrier to Noise Ratio (CNR) is virtually idential to the theoretial performane of a differential phase shift keyed (DPSK) detetor. This paper also desribes the realisation of the speial PLL required, to reover the data lok. This PLL uses an EPLD, a DAC, a onventional loop filter and a onventional VCO. 1. Introdution The transmission of data from the GMS weather satellite is a BPSK signal, at a arrier frequeny of GHz with a 66 kbit/se data rate. Beause of the > db free spae loss of the transmitted signal, the reeived CNR is only a few db above the minimum value required to demodulate the data with aeptable error rates. To reeive these signals, a low ost BPSK demodulator is required, whih an aurately demodulate BPSK signals at these low arrier to noise ratios. The reeption of Binary Phase Shift Keyed (BPSK) signals has traditionally been diffiult. The arrier has either a degree or a 18 degree phase shift depending on the data and the arrier amplitude is zero during the data transitions. As a result, a onventional Phase Loked Loop (PLL) demodulator annot be used. Differential detetion of BPSK signals is easy in theory, but diffiult in pratie. A Costas Loop [1] or a Phase Loked Loop (PLL) with speial phase detetors[], an be used to reover the arrier. That arrier is then used to synhronously demodulate the reeived signal. From theory, synhronous demodulation of BPSK data gives the best BER performane. In pratie a Costas Loop will only perform aurately at a high Carrier to Noise Ratio (CNR). At a low CNR the loop will tend to loose lok. The BPSK demodulator desribed here remains loked under noisy onditions. The new BPSK demodulator uses digital tehnology, resulting in a lower prodution ost and simpler hardware than the Costas Loop.. Pratial BPSK demodulator BSPK Input Delay of One Bit Communiation texts [3] suggest the use of differential phase detetion, based on the blok diagram of figure 1. However these texts do not mention the strit synhronisation requirements. If the input waveform is a arrier: X(t) = Sin(ω t) The delayed signal will be: Y(t) = Sin (ω t + θ) Eqn. 1a Eqn. 1b where θ is the phase shift of the delayed waveform with respet to the present waveform. The output from the multiplier will then be: Sin( ω t + θ ) dt = Sin ( θ ) Sin( θ ) 1 1 = [1 Cos(ω t)] θ ) Sin(ω t) θ ) For a typial BPSK system, there are many arrier yles per data period. For ideal operation θ is or 18 and then the seond term an be ignored, leaving a DC omponent plus a large ripple..1 Realisation Over One Bit Figure 1. Differential BPSK demodulator. The signal at the multiplier output in Figure 1 and shown in equation must be used as the input for the data lok reovery iruitry. This large ripple auses problems, with the stability of the lok reovery hardware. Using In-Phase (I) and Quadrature (Q) omponents as shown in Figure, removes most of the ripple. The Analogue to Digital Converter (ADC) digitises the input arrier waveform of equation 1a. The digital delay line then delays this waveform by one data bit. The signals at the tapping points 1 and 16 then orrespond to those that are multiplied in figure 1. The delay line is loked Demodulated Eqn.

2 1. Input ADC EPLD Delay Line 17 bit long, 8 wide Ripple I Out I Ripple Figure. New BPSK demodulator. with the sampling lok that is also used for the ADC. The sampling frequeny is hosen suh that one sampling period delay orresponds to 9 phase shift of the arrier waveform. If a sine waveform is present at tapping point 1, then a osine waveform is present at tapping point. The signals at tapping points 1 and 16 will thus be In- Phase (I) omponents and those at tapping points and 17 will thus be Quadrature (Q) omponents. At the adder in figure, the following waveform will thus be present: X(t) = Sin(ω t) Sin(ω t+θ)+cos((ω t+φ) Cos(ω t+θ+φ) Eqn. 4. Where θ is the phase shift of the arrier over one data bit period, inluding the BPSK modulation and φ is the variation from the 9 phase shift. In pratie φ will be zero, and θ will be either or 18 depending on the BPSK data. The resulting waveform at the adder will thus be either: X(t) = Sin (ω t) + Cos (ω t) = 1 or X(t) =- Sin (ω t) - Cos (ω t) = -1 Eqn. 5. depending on the value of the BPSK data. Note that the ripple at ω has been removed ompletely. The resulting waveforms are shown in Figure 3. By alulating the variation of θ and φ resulting from the BPSK arrier frequeny and the sampling frequeny being not orretly related, the tolerane of this BPSK demodulator an be plotted as shown in figure 4. Using both the I and Q tapping points, doubles the output signal and results in a minimal ripple. For an IF frequeny shift of 5% of the data rate, the ripple is less than 1% and the data output is more than 7% of the ideal output voltage. For hardware realisation of the BPSK demodulator, one an thus have a frequeny shift of 5% Amplitude I Q I I + Q Q Time Figure 3. Demodulator Waveforms % 5% 1% 15% % 5% 3% 35% 4% 45% 5% of 66 khz, or ±165 khz of the MHz BPSK arrier for a 3 db drop in output. This frequeny stability requirement is quite feasible, even for down onversion from a GHz satellite signal. By adding two more multipliers and an adder to the blok diagram of Figure, the tehnique an be extended to demodulate QPSK signals as well, as shown in Figure 5. A phase loked loop (PLL) is required to reover the 66 khz data lok. The 1.56 MHz sampling frequeny for the ADC and delay line is 16 times the 66 khz data lok and is produed by this same PLL.. Hardware Frequeny Error wrt Frequeny Figure 4. Frequeny Tolerane of BPSK demodulator. 1 EPLD Delay Line 17 bit long, 8 wide Figure 5. QPSK Demodulator. Deision Logi An 8 bit ADC is used as this has been demonstrated by omputer simulation to give a satisfatory performane. The delay line is thus 17 bit long and 8 bit wide. This requires 136 flip-flops and is programmed into a Lattie isplsi13 EPLD. The multipliers shown in figure need to be able to multiply two 8 bit numbers inside the 94.7 ns period of the 1.56 MHz sampling lok. This is ahieved by using a 51 kbyte EPROM as a look-up table. The 16 EPROM data inputs are formed by the two 8 bit inputs to be multiplied. Sine the multiplied I data is the same as the multiplied Q data one lok pulse later, only one EPROM is required if the EPLD is used to store and delay the multiplied value for one lok period. Q I

3 The whole blok diagram shown in figure is thus realised using two low ost EPLDs, one EPROM a low ost ADC and a low ost DAC. Figure 6 shows the resulting hardware. The left board is the BPSK demodulator and the right board is the Phase Loked loop desribed later. Figure 7 shows the binary input data, the BPSK data and the demodulated output obtained with this hardware. The top trae is the binary data, the seond trae is the differentially enoded signal, whih is then modulated with a arrier. The bottom trae is the demodulated output. The system performs very well, even under noisy signal onditions. Figure 6. BPSK Demodulator Harware. in Differential data BPSK 1.E+ Baseband Simulated 1.E-1 Baseband Theoretial IF Simulated 1.E- BER A seond isplsi13 EPLD is used to add the I and Q multiplier outputs and to perform the integrate and dump data detetion using an adder for the integrator. The added I and Q multiplier output is the raw digital data output required for the data synhronisation PLL. This signal is turned into an analogue signal using a Digital to Analogue onverter (DAC), the output of whih is then filtered to provide some smoothing. This filtered raw demodulated data is then used as referene input to a PLL, to reover the 66 khz lok and hene the 1.56 MHz sampling lok. 1.E-3 1.E-4 1.E-5 1.E Eb/No Figure 8. Frequeny Tolerane of BPSK Demodulator..3 Error performane Sine the system has to operate under poor Carrier to Noise onditions, the performane of the system under noisy onditions must be investigated. Figure 8 shows the error performane obtained from a omputer simulation of the system, desribed above. There is an exellent agreement between the theoretial results [3] for the ideal differential deoder and the omputer simulation of the atual system. The alulated error performane for an IF simulation, inorporating the hardware filters used in the simulation, shows a slight degradation in the error performane due to more noise being passed by the non-ideal IF filter. The bandwidth of the IF filter indiated, is that of an ideal filter with the same total noise output. The noise spetral density (N) indiated in Figure 8 is the total noise, obtained from the omputer simulation, divided by this bandwidth. The simulated performane of the system at a BER less than 1-4 has a larger error tolerane, as a very large omputer simulation is required in order to have suffiient errors for the results to be statistially valid. In the omputer simulation, the effets of the finite length and width of the EPLD delay line and the realisation of the multipliers using EPROMs was inluded. A slightly worse, but satisfatory performane was obtained, even with a 4 bit wide delay line and multipliers. For 4 bit wide multipliers, both multipliers an be inluded in one EPROM. The adder of Figure an then also be inluded in the EPROM as part of the look-up table, reduing the ost even further. Sine the ost of the 8 bit wide realisation is small, and there is an improvement in performane, an 8 bit wide realisation is used in the hardware. 3. Phase Loked Loop 3.1 Phase Detetion out Figure 7. Frequeny Tolerane of BPSK Demodulator. The demodulator requires that the ADC and Digital Delay line lok frequeny is exatly 16 times the data rate. A PLL is required to reover the data lok and generate the 1.56 MHz ADC sampling frequeny. To minimise hardware prodution osts, a omplete digital realisation of this phase detetor is required.

4 Clok This will our 5% of the time on average, whih is suffiient to keep the PLL phase loked. Sine the analogue Phase Detetor is produed by a DAC, no drift ours in-between Phase Detetor updates Period/Phase 64 Phase Det O/P Figure 9. Waveforms for Phase/Frequeny Detetor. The binary data has a time between zero rossings that varies in multiples of µs. Sine the zero rossings do not our every data bit, a onventional phase detetor annot be used. One of the authors [4] has developed an analogue phase detetor, whih is suitable for this appliation. This phase detetor will however only lok if the free running frequeny of the PLL is very lose to the 66 khz data rate. That annot always be guaranteed. To ensure reliable operation of the reeiver system, frequeny detetion is required to ensure that the PLL always loks. Figure 9 shows the waveforms used in the Phase/Frequeny detetor developed for the Clok reovery. The Clok is the 66 khz data lok, whih is derived from a MHz voltage ontrolled osillator (VCO) by dividing by 18. The data signal is the raw binary data, obtained by digital to analogue onversion and filtering of the adder output of Figure (). At a transition of the data, a Phase and Period is set to zero. The MHz VCO inrements that ounter and its output ramps up as shown. When the falling edge of the Clok ours, the ontent of this ounter is lathed and transferred to the Phase Detetor. This Phase Detetor is onverted to an analogue voltage, the filtered value of whih ontrols the VCO. If more than one ones or zeros are being transmitted in suession, there will not be a seond transition µs after the first one and the ounter simply keeps ramping up until the maximum ount of 19 is obtained, where the ounter limits. If this happens, the Phase & Period ontents are not transferred to the Phase Detetor. The next data transition will then reset the Phase and Period bak to zero. The phase detetor will thus only produe a phase output when two transitions in the data are produed µs apart. 3. Frequeny detetion The time interval between zero rossings of the data is obtained from the Phase and Period ounter shown in Figure 9 and is a measure of the frequeny differene between the input data and the VCO. The ounter ontains the data period, just before the ounter is set to zero. For the hardware desribed here, the data period should be 18 lok pulses of the MHz VCO. The ounter ontents an thus be used as a frequeny indiation and used to provide frequeny loking. Sine on average one quarter of the number of data bits have transitions µs apart, the VCO frequeny is ontrolled often enough to ensure proper loking of the VCO. Figure 1 shows the resulting blok diagram of the PLL. The output of the frequeny ontrol ounter and the phase detetor output are added in the orret proportions to provide the input to a DAC, whih provides the analogue voltage of the VCO after filtering. For the hardware realisation the Phase detetor produes 18 different levels for a 36 range of operation. In order to produe a good overlap between the frequeny detetor and the phase detetor, the frequeny step size is 64 times larger than the phase step size. The MHz VCO has a 1 MHz tuning range. Sine a 16 bit DAC is onneted to this ontrol ounter, eah ounter step is thus 15 Hz, whih is well within the frequeny tolerane required as shown in Figure 4. The Phase Frequeny detetor and the VCO frequeny dividers an be realised using one EPLD. The right hand board shown in figure 6 ontains the Phase/Frequeny detetor, VCO and loop filter. The seond EPLD on that board is for further proessing of the reeived data. 3.3 Stability This phase/ frequeny detetor has some interesting stability problems. If we onsider the phase detetor only, the gain of the analogue iruit and the orner frequeny 66 kbps Clok 66 khz Phase & Period Period Phase Detetor Threshold Detetion 8 Bit Adder 15 Bit Frequeny Control 16 Bit Lath Divide by 16 DAC Loop Filter Divide by 8 VCO MHz 1.56 MHz Figure 1.Phase/Frequeny Detetor and PLL Blok Diagram.

5 of the RC filter used at the output of the DAC are arefully ontrolled to ensure the orret damping fator and natural frequeny of the PLL. Sine digital hardware of 8 bit preision in some parts and 16 bit preision in other parts is used, a slightly onservative damping fator needs to be used in the design, to result in a stable system. The PLL loks easily with the phase detetor only. As expeted, the lok-in range is however limited.. When the frequeny detetor is used by itself, the resulting Frequeny Loked Loop works very well and quikly adjusts the frequeny of the VCO to within 66kHz of the required frequeny, when the frequeny ontrol stops providing further frequeny orretion. This is a oarse frequeny ontrol. Using nonlinear tehniques, whih are beyond the sope of this paper, the phase detetor provides a fine frequeny orretion,whih ensures that the PLL aquires lok. The EPLDs an simply be reporgrammed on-board to hange the phase and frequeny detetor to different onfigurations during development. The use of EPLDs is thus very onvenient for the development of new systems like this. When the phase detetor and frequeny detetor are ombined, there an be an interation between them, whih together with the finite preision used in the digital hardware, an ause instability. This instability manifests itself as small amplitude limit yles. These limit yles an be removed using areful design of the phase/ frequeny detetor parameters and areful seletion of the loop filter parameters. In order to be able to selet the orret phase/frequeny detetor parameters and the orret loop filter, the PLL inluding all its nonlinear and quantisation effets needs to be simulated using MATLAB or an Exel spreadsheet. Figure 11 shows the transient phase error response obtained from this Exel simulation of the Phase/Frequeny detetor. The transient inludes a 5 MHz initial frequeny error, to permit the operation of both the frequeny and phase detetor to be demonstrated and to show that the PLL will lok regardless of the initial onditions. Three operating regions an learly be seen. The first part up to.35 ms onsists of region where the frequeny error is large and frequeny orretions are made every µs measurement interval shown in Figure 9. The seond region is from.35 ms to.88 ms where the phase detetor is ontrolling the frequeny ounter to ensure that the PLL aquires lok. During this time the operate at the exat frequeny. The third region from.88 ms onwards shows the PLL in lok. For a 5 MHz initial frequeny error, the PLL loks within 1 ms. Figure 1 shows the eye diagram and the reovered data lok. It an be seen that the PLL loks aurately. The reovered data lok is used to drive the timing for the integrate and dump filter in the BPSK phase detetor, thus ensuring that the transmitted data is reovered with the maximum likelihood and the minimum error. 4. Conlusion A BPSK detetor and its assoiated Clok reovery iruitry is realised using low ost digital hardware. The BPSK detetor performs well and loks reliably to the data, even in high noise onditions. A novel type of Phase/ Frequeny detetor is presented, whih ensures a reliable lok reovery of random binary data using predominantly digital hardware. This reovered data lok permits the reovery of the reeived data using an integrate and dump filter, thus ensuring the optimum detetion of the BPSK data. 5. Referenes Phase Error (degrees) Figure 1. BPSK Demodulator Eye Diagram Time (ms) Figure 11. PLL Phase Error for 5 MHz Frequeny Step. [1] Costas, J. P. Synhronous ommuniations proeedings of the IRE, Vol 47 pp 58-68, [] Piper B. and Kikkert C. J. The hardware design for the reeption of GMS SVISSR Weather Satellite Signals. Workshop on Appliations of Radio Siene, Canberra, June [3] Roden, M. R. Digital Communiation System Design, Book, Prentie Hall, [4] Kikkert C. J. Appendix 1 of D. A. Puknell, Fundamentals of Digital Logi Design: with VLSI Ciruit Appliations, Book, Prentie Hall, 199.