ESE-2019 PRELIMS TEST SERIES Date: 7 th October, 2018 ANSWERS. 67. (d) 68. (b) 69. (d) 70. (c) 71. (b) 72. (b) 73. (a) 74. (b) 75. (a) 76.

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1 ESE-9 PRELIMS TEST SERIES Date: 7 th Otober, 8 NSWERS. (). (a) 45. () 67. (d) 89. (d). (d). (b). (b) 4. (d) 46. (a) 68. (b) 9. (). (b) 4. (b). () 5. (a) 47. (b) 69. (d) 9. (b). (b) 5. (b) 4. (d) 6. () 48. (d) 7. () 9. (d) 4. (d) 6. (d) 5. (d) 7. (b) 49. (d) 7. (b) 9. () 5. () 7. (d) 6. (b) 8. () 5. (d) 7. (b) 94. (a) 6. () 8. (a) 7. (d) 9. () 5. (d) 7. (a) 95. (b) 7. (d) 9. () 8. (a). (a) 5. (b) 74. (b) 96. (b) 8. () 4. (a) 9. (a). (b) 5. (b) 75. (a) 97. () 9. (b) 4. (a). (d). () 54. (a) 76. (b) 98. (). (d) 4. (b). (d). (a) 55. (b) 77. (b) 99. (d). (b) 4. (a). (a) 4. (a) 56. (a) 78. (b). (a). () 44. (d). () 5.. () 57. () 79. (b). (b). (a) 45. () 4. (d) 6. (b) 58. (b) 8. (). (b) 4. (d) 46. (d) 5. (d) 7. (b) 59. (a) 8. (). (b) 5. (b) 47. () 6. (a) 8. (d) 6. (a) 8. (b) 4. () 6. (b) 48. (b) 7. (d) 9. (b) 6. (b) 8. (b) 5. () 7. (d) 49. (d) 8. (b) 4. () 6. (a) 84. (b) 6. (a) 8. (d) 5. () 9. () 4. (b) 6. (b) 85. (b) 7. (b) 9. (). () 4. (a) 64. () 86. (d) 8. (b). (a). (a) 4. () 65. (a) 87. (d) 9. (d). (). (b) 44. (b) 66. (a) 88. (). (a). (d)

2 () nalog Eletronis + Computer Fundamental + Digital Eletronis. () mplifiation in inverting amplifier is given by v v v v i v v R R i R vi R vi v v v. (b) % %.5V R R vi R R v i K I I k v i + I.5.5m V (.5) (5).5V i L. () v.5.5m k using KCL at v node I + i i L I i L I.5.5 I.75 m k i L v IES MSTER Given iruit is summing amplifier for output to be symmetrial about V, d part of equation should be zero.5 v I.5 v I v I 4. (d) v. Transfer harateristi of the Shmitt Trigger is as shown below V TH V TL 5. (d) V V TL R R R V L R R R V H V H V V Hysteresis width :V HL V TL 5 R i L 5 V v i I v i R x + R 5V V TH 5 5V R R 4 V R R R R R R 4 VI 4 vi 4 vi using given input signal V sin t v I 5 4 V [ + sin t ].5 v I Considering general iruit for the given ases. v x (virtual ground) I i R i vi v x vi R R vi R I i

3 [EE], ESE Prelims Test Series Test - 7 th Otober 8 () 6. (b) R i R k (for all three ases R is same) R ia R ib R i Using virtual ground onept I i v i V k k v i (I i)()k R i 7. (d) 8. (a) 9. (a) vi I i k k Ciruit ats as inverting and non-inverting amplifier both. Hene, V K V K K i Vi K K K K V V Vi Vi V i i The low frequeny gain of the low pass filter V s V s for + j d log 4 d For sustained osillation gain v 9 R R 9 R. (d) x(t) R k IES MSTER f tos t fˆ tsin t f t, hene, ˆf t Envelope of x(t) f t Using bionomial expansion Envelope of x(t). (d) y(t) S(t) (t) S f f S f f y(f) spetrum of y(f) will be: y(f) f t f t +f(t) where f 4 KHz KHz 9 f (in KHz) KHz KHz will not be present.. (a) M signal is given by s(t) [ + K a (m)(t)] os f t. () m(t) Here, m (t) sin f t m To avoid distortion of M signal K mt a K a Ka Maximum value of K a.5 Operation of multiplying a signal with sinusoidal signal is alled Mixing or Heterodyning m(t) os t Envelope of os sin Envelope of x(t) f t f t fˆ t 4. (d) os t

4 (4) nalog Eletronis + Computer Fundamental + Digital Eletronis Here, m(t) 4 os 4 t and (t) 6 5 os t f m 4 khz, m 4 V, 5 V andwidth of M f m 4 khz 8 khz Now, Total power b P P T b Modulation Index mplitude sensitivity (K a ) and be is not given, then b is alulated as : 4 b m.8 5 lso arrier power P 5.5 W R.8 P T.5.65 W 5. (d) Peak Envelope Power R.M.S.Value of max imum amplitude Resistane 6. (a) max max 5 R R 6 PEP 87.5 W S(t) 4.4os 4 t.8sin t os 8 t IES MSTER V, m.4, m.8 m m.8 Power P T m m.4.8 m m P R P T.8 7 W 7. (d) balaned Modulator/Produt Modulator is used to generate DS-SC signal. The iruit diagram is given below : m(t) 8 Phase Shift M Mod- M MOD (t) (b) The iruit given is a Envelope Detetor iruit whih an be used to demodulate M signals with m without distortion. s(t) The harging time onstant must be small for C to be harged to peak value in a short time. Hene, RSC f Disharge time onstant should be large enough so that C does not disharge too muh between the positive peaks of arrier but small enough to be able to follow the maximum rate of hange of message signal. Hene, RLC f W RLC takes an of the shape of envelope W as m(t). 9. () Synhronous Detetor/Coherent Detetor an be used for any modulation index. Ciruit is omplex due to synhronisation of signals. Signal to Noise ratio improves at low signal levels.. () Single Sideband Suppressed Carrier (SS SC) is not affeted due to Quadrature Null Effet. (a) Let y(t) s(t) (t) m(t)osf t os f t y(t) m(t) m t os 4 f t os When y(t) is passed through a Low Pass Filter with bandwidth that of m(t), the term of y(t) ontaining f will be bloked. Hene, output of LPF will be :

5 [EE], ESE Prelims Test Series Test - 7 th Otober 8 (5) x(t) m(t) os Pos Power of output signal 4 P is power of m t signal. (b) In general SS-SC signal is given by:. (a) ˆ s(t) m t os f t m t sin f t Where is for US and + is for LS. Power saved PT 4m m % Power saving Power saved 45 9% Total Power 5 4. (d) Hilbert Transform iruit is used in Phase Disrimination Method. 5. (a) 4 s(t) 9 ost os t Comparing with standard M signal, modulation index of s(t) is m m>, synhronous detetor an be used. Square low demodulator and envelope detetor an be used for demodulating M signal with m. Costas reeiver is used for reovering arrier frequeny. 6. () SS-SC signal is represented by: 7. (b) 8. () IES MSTER ˆ s(t) m t os f t m t sin f t Here, ˆm t is 9º out of phase to m(t) whih is generated using Hillbert Transform. Hene, it ontains quadrature. In FM, message signal voltage variations are stored as arrier signal frequeny variation so, it is alled as voltage to frequeny onverter. If m(t) is message signal used to modulate a arrier C os( ft), the FM signal is given by s(t) 9. (). (a). (b). (). (a) 4. (a) 5. () 6. (b) 7. (b) os ft K f m t dt The iruitry needed in the TDM system is muh simpler than required in FDM system. We have, In PCM S 6n.8 Nq d when n is inreased by, improvement in S N 6 db q In DPCM, a simple FIR digital filter, generally known as transversal filter used as preditor to obtain linear ombination of previous sample values. ompanding is used in PCM system to keep quantization noise low for low amplitude signals. Sample and hold method of sampling is most ommonly used. SK has maximum probability of error. The Guassian probability density funtion is defined as f x (x) e x The Power Spetral Density (PSD) of white noise has onstant value N o / for all frequenies. Sine, the area under PSD urve is equal to total average power, hene average power of white noise proess is infinite. In delta modulation when signal variation is within step size, the reovered waveform is like a square wave (like d) whereas the original signal is not like a square wave, resulted distortion is known as Granular noise.

6 (6) nalog Eletronis + Computer Fundamental + Digital Eletronis 8. (d) 9. (b) 4. () 4. (b) 4. (a) 4. () 44. (b) 45. () original signal resulting signal DPSK modulator onsists of logi iruit (XNOR gate), multiptier and a delay iruit. PCM uses quantization proess and hene quantization noise is present in PCM only. dvaned form of digital transmission assigned audio tones of Hz and 4 Hz to represent the digital ones and zeros that omprised the SCII serial data stream to transmit spaeraft telemetry information. This form of modulation is known as udio Frequeny Shift Keying. PWM signal is generated by applying trigger pulses to ontrol the starting time of pulses from a monostable multivibrator. Here, step size 75 mv stepwidth (T s ).5 ms The maximum slope the stairase an trak 75 T s.5 Ts 5 V/se. In DM, the step size is hanged in aordane with the message signal. So, the requirement of omparators in the enoder is large. IES MSTER ( ).... ubbled NOR gate X X 46. (a) X Therefore, (y De Morgan s theorem) ubbled NOR gate is equivalent to an ND gate. P P P its,,5,7 (i.e. P ) must have even parity, so P must be a its,,6,7 (i.e. P ) must have even parity, so P its 4,5,6,7 (i.e. P 4 ) Must have even parity so P 4 Thus, 47. (b) 48. (d) P, P, P 4 Gray to binary inary equivalent is (4) 8 4 Gray to binary onversion + + G n n (+)G n n n (+) G n n n G Therefore 4 inary number

7 [EE], ESE Prelims Test Series Test - 7 th Otober 8 (7) 49. (d) For signed binary number 7 in sign magnitude form sign bit sign bit magnitude 9 in s omplement form magnitude note that s omplement of 5. (d) 5. (d) 5. (b) 5. (b) 8 in s omplement form sign bit magnitude ( in s omplement of ) In ase, digits to 9 are possible In ase 6, digits to F are possible In ase 5, digits to 4 are possible In ase, digits to are possible so in, digits whih is not possible if base is. Memory ddres Register speifies the memory word seleted. The information transfer to and from registers in memory and the external environment is ommuniated through one ommon register alled the memory buffer register (MR). When the memory unit reeives a write ontrol signal the internal ontrol interprets the ontents of the buffer register to be the bit onfiguration of the word to be stored in a memory register. ROM are nonvolatile i.e. information does not get lost when power is swithed off. Data stored in ROM an only be Modified slowly, with diffiulty. or not at all. Therefore, it is mainly used to store firmware (software that is losely tied to speifi hard ware, and unlikely to need frequent updates) or appliation softwares. DRM IES MSTER Redued power onsumption Larger storage apaity Slower Less expensive Need refreshing periodially i.e. periodially reharging. SRM Easier to use and has shorter read and write yles hene faster 54. (a) 55. (b) Smaller storage apaity Comparatively expensive Need ontinuous power supply NOR and NND are universal gates as any type of gate an be made by using these gates. OR gate with bubbled input x y ubbled output ND gate x y y DeMorgan s therorem (xy) ' x' + y' 56. (a) 57. () Cumulative law of addition x + y y + x F x + y ssoiative law of multipliation (x.y).z x.(y.z) F (xy) k-map is an abstrat form of Venn diagram organized as a matrix of squares. Let us take two variables x and y then k-map xy xy x y x xy xy y xy xy xy xy oolean expressions for 6 funtions of two variables.

8 (8) nalog Eletronis + Computer Fundamental + Digital Eletronis Operator oolean funtions Name Comments Symbol 6 F Null inary Constant 4 F xy x.y ND x and y 5 F xy x / y Inhibition x but not y f xy Transfer x F x y y / x Inhibition y but not x F y Transfer y F xy x y x y Exlusive OR x or y but not both F x y x y OR x or y F x y x y NOR Not OR Equival F9 xy x y x y x equals y ene * F y y Complement Not y F x y x y Impliation If y then x F x x omplement Not x F x y x y Impliation If x then y F xy x y NND Not ND 58. (b) 59. (a) 6. (a) 6. (b) F Identity inaryons tan t Equivalene is also known as equality, oinidene and exlusive-nor In F (x+y) (x'+z) (y+z) term (y+z) is redundant, therefore F (x+y) (x'+z) x(x'+z) +y (x'+z) xx' + xz + yx' + yz x'y + xz + yz xy xy CD x y xy xy IES MSTER 6 (deimal) inary value of The output is only for the input ombinations,,,, f(,,c,d) m,,5,7,9 y k-map: f CD 4 8 f D CD 6. (a) 6. (b) 5 9 D 7 5 y k-map of two variables F F( ) m,, f C C C.C y Dermorgan s theorem C C DeMorgan s theorem C 6 4 C C C C CC C CC C C as CC C C as + or f + C f 64. () as Combining don t are onditions to obtain simplified expression F 'C'D' + CD' + CD' + ' CD' + 'C'D 'C'D' + CD' ( + ) +'CD' + 'C'D

9 [EE], ESE Prelims Test Series Test - 7 th Otober 8 (9) 65. (a) F DE C 66. (a) 67. (d) 68. (b) 69. (d) F 'C'D' + CD' + 'CD' + 'C'D D' ('C' + C + 'C) + 'C'D D' ( 'C' + C ( + ')) + 'C'D D' ('C' + C) + 'C'D D' (('+C).(C' + C)) + 'C'D D'(' + C) + 'C'D 'D' + CD' + 'C'D 'D' + CD' as 'C'D is don t are ondition. y k-map for 5-variables D F DE C C E F DE + 'C'E' + ''C E D ssembly language falls under seond generation of language (GL). ll other statements are orret. The two proessor an be used simultaneously in a multiproessor system with appropriate iruitry. The wordlength does not determine the length of address bus. So we annot say anything about address bus. C IES MSTER RISC is mostly used in appliations with a dediated number of taks. printer and lift ontroller has a speifi number of funtions to perform while a Gaming PC and a router has large number of general operations whih an be handled muh better by a CISC. 6 bit wide address bus i.e. total address an be 6 address for eah byte 6 K 4 4 let n be number of memory hips 7. () 7. (b) 7. (b) 7. (a) n KLIP (Kilo Logi Inferene Per Seond) is often used to indiate the reasoning power of I mahine. The data transfer rate of a CPU is always muh larger than that of the peripherals onneted to it. Thus it is the data transfer rate of the peripheral whih limit the overall transfer rate between the CPU and peripheral. Routing data traffi is a very speifi task whih does not ame under signal proessing appliations. Thus a DSP might not be suitable for this. Cahe memory is the fastest memory. The other options are examples of seondary storage. 74 (b) DRM offers redued power onsumption and address generally by segmented program is alled physial address. SRM requires onstant power supply. It onsumes more power whereas DRM onsumes less power as the information is stored in apaitor fastest and most flexible ahe organisation uses assoiate memory not ontent addressable memory. ssoiative memory is more expensive than RM beause eah all must have an extra storage apability as well as logi iruits formating it s ontent with external arrangement. 75. (a) The above program is used to divide FEH by H. The remainder is 4H 4H. 76. (b) Program Counter In a miroproessor, program ounter (PC) holds the address of the next instrution whih is to be fethed. 77. (b) 78. (b) CPU, ingeneral, onsists of LU, umulator, Control unit and register set. Memory is a part of a omputer whih is external to CPU.

10 () nalog Eletronis + Computer Fundamental + Digital Eletronis 79. (b) Miro program is a set of instrutions for primitive operations in a system. Letters () 8. () 8. (b) 8. (b) 84. (b) 85. (b) Z 9 a 97 b 98 z SCII Code Overflow ours during addition of two numbers if the two numbers are of the same sign. b + a Thisisasmaller numbers b a b a overflow may our overflow will not ours Total Compiler onverts high level language (HLL) to low level language/mahine language/objet ode. IES MSTER ssembler onverts assembly language to objet ode Operating System is not a ode onverter. f 9 is equivalent to f f 9 Loader is used to load objet program from seondary memory to main memory. Disadvantages of immediate addressing are : When immediate operand hanges, the program should be reassembled. In ase of other 86. (d) 87. (d) 88. () 89. (d) 9. () 9. (b) 9. (d) 9. () addressing - operand is stored in some memory loation. To hange operand in the program, we need to hange only the ontent of that memory loation, not every where in program as in ase of immediate addressing. Size of operand should not be more than the word length of omputer. No flags are affeted during data transfer. ssembly language program runs faster than high level language. eause onversion from ssembly language to mahine language (binary) is faster than that from HLL to mahine language. Resident ssembler - It produes objet ode for the same omputer on whih it runs. Cross ssembler - It runs on a omputer other than that for whih it produes mahine ode. One-pass assembler - It reads assembly language program only one. -mahine yles: I st to feth opode of instrution IN nd to feth address of input port from memory. d to read data from input port TRP pin has the highest interrupt priority. MOV, M The ontents of memory at the loation speified by HL pair is to be transfered into aumulator. Indiret addressing mode. IN The address of port is diretly speified as. Therefore this is a diret addressing mode. miroproessor an be broughtout from a HLT state using an interrupt or reset. The reset pin is labelled as RESET IN. Therefore logi Low is used to reset a miroproessor. LXI Load immediate data, requires two operands one-register or memory to whih data is to be

11 [EE], ESE Prelims Test Series Test - 7 th Otober 8 () 94. (a) 95. (b) 96. (b) 97. () 98. () (MS) (LS) stored seond-immediate data value. CMC Complements the arry status. ll other instrutions involve the aumulator. The POP instrution takes three yles to exeute. The ontrol word for above definition of ports is 88H. One 859 an be used to entertain 8 I/O devies upto 64 devies an be onneted using two bit weighted resistor type DC: D D D D o 99. (d). (a) R R 4R 8R + R f V out Given that MS resistor i.e. R kg then the LS resistor is 8R 8 k Resolution MV i.e. one step is equivalent to MV.86 If input is steps IES MSTER SC always produes a final output, that is, at the step below the analog input. Therefore for V input.86 V, the digital result would be 95 Flash type DC is fastest. Conversion time ns or less as onversion is performed simultaneously through a set of omparators. Counter type DC n Maximum onversion time TCLK for an n-bit DC. (b). (b). (b) Suessive approximation type DC Conversion time n T Dual slope type DC CLK n Conversion time N TCLK Thus orret order is Flash type > Suessive approximation type > Counter type > Dual slope type The dual-slope type /D onverter is one of the slowest onverter but it is relatively inexpensive as it does not require preision omponents suh as a DC or VCO. It has low sensitivity to noise and to variation in its omponent values aused by temperature hanges. eause of its large onversion time, the dualslope type DC is not used in any data aquisition appliations. The major appliations are in digital voltmeters, multimeters et. W here slow onversion are not a problem. In the Moore Model, the output depends only on the present state of the flip-flops. While in Mealy Model, the output depends on the both present state of the flip-flops and the inputs. y State table fter pulses State Q Q Q Q Pr eset Presetting Thus there are states MOD- ounter

12 () nalog Eletronis + Computer Fundamental + Digital Eletronis 4. () To divide the frequeny by 4, a MOD-4 ounter is needed. For MOD-4 ounter 5. () N 4 N 6 flip-flops are required. The output frequeny of MOD-N synhronous ounter is f /N or 6. (a) 7. (b) f 6 N MHz The JK flip-flop forms a MOD- ounter Therefore the output frequeny is given by f out 6 6 MHz For a n-bit ripple ounter, total propagation delay nt pd where t pd propagation delay in eah stage. To avoid the ount skip f nt pd Therefore, for a ount skip the minimum value of t pd an be obtained by or (t pd ) min f or tpd min n t pd nf min IES MSTER 6 nano seonds 8 seonds Dynami shift register is one in whih the storage is aomplished by ontinually shifting the bits from one stage to the next and reirulating the output of the last stage into the first stage. These registers are made up of MoS inverters. On the other hand stati shift register is one in whih eah of the memory elements used to build the register an retain the data bit indefinitely. shift register made up of flip-flops is alled stati shift register. 8. (b) 9. (d). (a) Truth Table DC set DC Reset Flip flop PRE CLR Re sponse Not used Q Q Cloked operation Full adder : C in Sum C out Half adder C in Half adder in ( )C lternate iruit : Half adder Half adder Redrawing the iruit + C out Sum S C in C ( )C out + Thus, X (y Demorgan s theorem) Y ( ) in X Y

13 [EE], ESE Prelims Test Series Test - 7 th Otober 8 (). (d). (b) Y Thus, the given iruit is half adder with Y sum and X arry y k-map for five variables C DE C DE D 9 E E D The simplified expression is E + 'DE' 6 E (9,,, 5, 5, 7, 9, ) M 7 and M 9 are don t are 'DE' (, 6, 8, ) M is don t are C IES MSTER Three minterms are to be don t are Noise margin (V) : TTL.4 V ECL.5 V MOS.5 V CMOS 5 V IIL.5 V. (b) 4. (d) 5. () 6. () 7. (d) 8. () C Power dissipation per gate (mw) TTL mw ECL 5 mw CMOS. mw IIL. mw So, the orret order is ECL > TTL > IIL > CMOS Number of oolean expressions having n variables Here, n then n DC.8 H Using Karnaugh map, for the given expression. C C C C C Output, Y C Y C C Y C Y

14 (4) nalog Eletronis + Computer Fundamental + Digital Eletronis 9. (b) Y C C So, total number of NND gates 5 F if i.e. F if 4. (d) Q, Q, Q () (5) The given iruit is a Mod-5 ounter beause after the ounter state is, the ounter resets and starts ounting again from. PIPO mode is not done by a shift register.. (d). (b). (). (a) F if i.e. F if So, F F F P Q I I I I 4 MUX S S P Q Output, F an be written as F PQ PQ P Q XNOR (P,Q) y F IES MSTER D an be written as D output, f an be written as f D. D.C DC So, f C C C Counter, flip-flop & shift registers have a memory storage element. Therefore, they are sequential iruits. Only adder is a ombinational iruit. To reset all the flip-flops 5. (b) 6. (b) 7. (d) 8. (d) For 8 multiplexer : S S S For the output Y to be a opy of input I 5, S, S and S. 8 bit serial-in/serial-out shift register, So, four lok pulses are required for output to be Q. time delay, t d 4T Y I I I I I 4 I 5 I 6 I 7 4 se se 6.67s In a 885 miro proessor, On reeiving an interrupt from an I/O devie, the CPU ranhes off to the interrupt servie routine after ompletion of urrent instrution. Diret memory aess (DM) is a feature of omputerized systems that allows ertain hardware subsystems to aess main system memory independently of the entral proessing unit (CPU). Without DM, when the CPU is using programmed input/output, it is typially fully oupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DM, the CPU first initiates the

15 [EE], ESE Prelims Test Series Test - 7 th Otober 8 (5) 9. (). (a). () transfer, then it does other operations while the transfer is in progress, and it finally reeives an interrupt from the DM ontroller when the operation is done. This feature is useful at any time that the CPU annot keep up with the rate of data transfer, or when the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. DM is the fastest mode of data transfer. The reason for having virtual grounding is beause Op-mp possess very high gain. Non linearity leads to variable gain, whih leads to amplitude distortion with variation of over wide range distortion may be high whih results in limited bandwidth usage. Total power in M Where P used R Total sideband power modulation index m PT P P onstant for the arrier m P hanges with Total power of transmitter inreases with inrease in modulation index.. (d) Too small value of disharge time onstant (R L C) will make output spikey (saw tooth ripple on the top). IES MSTER If disharge time onstant is very large. Capaitor will disharge very slowly and disharge urve will be relatively flat. Due to this the output will not follow the envelope of message signal.. (b) SS-SC modulation is pratially possible only for Wide and Gap signal e.g. Voie signal ( Hz to.5 KHz). Phase Disrimination method uses Hilbert transform iruit whih is not an easy iruit to realise for multi tone signals. 4. (b) The method of demodulation of SS assumes perfet synhronism between loal osillator at reeiver and transmitter whih an be met by 5. (b) 6. (d) 7. (d) 8. (a) 9. () 4. (a) 4. (a) adding a low power piltor arrier to the SS signal. lso, due to phase error introdued by loal osillator of the reeiver there is phase distortion whih gives rise to Donald Duk voie effet. Component of message signal. The vestige of unwanted sideband in VS is retained with the desired. This enables to make a pratial sideband filter. In FM, figure of merit FOM f and bandwidth m as.w. of FM inreases, inreases and hene FOM inreases. This enables a higher output signal to noise ratio. s.w. inreases noise performane is inreased. one pass assembler is faster as it goes through the program only one. oth are different notions. Statement II explain multiprogramming orretly. Multitasking is alloating CPU to different tasks in a sequential manner. Operating system onsists of all the programs required to run the peripherals of a omputer. monitor is a peripheral of the omputer. ll instrutions are of same length. Statement: This annot be true in general. There are some CISC omputer faster than RISC and vie versa is also possible. Call by referene - tual parameters are not diretly passed in the funtion, but the address of atual parameters are passed. Call by Value - tual parameters are diretly passed to the funtion. It has less overhead as ompared to that in all by referene as no stak operation is involved. In writing C programs, do while is less frequently

16 (6) nalog Eletronis + Computer Fundamental + Digital Eletronis 4. (b) 4. (a) 44. (d) 45. () 46. (d) used beause it is more natural to test the onditions at the beginning rather than at the end of the loop. For (; ;) or while ( ) statements are generally used. oth are true, but R is not the orret explanation of. Carry look-ahead adder is fast as ompared to ripple arry adder. This is beause the arry lookahead adder generates the sum and arry bit diretly. De-mux an be used as deoder. Selet lines of De-mux an be used as input to deoder. Output of De-mux will be output of deoder and input to De-mux an be used as enable input of deoder. De-mux has n -input and -output Deoder has n-input lines and maximum ( n ) output lines. ny one output of deoder is seleted depending upon the oded input. arry look ahead adder is a fast adder as it improves speed by reduing the amount of time required to determine arry bits. It alulates one or more arry bits before the sum whih redues wait time to alulate result of larger value bits. parallel arry adder generates sum digits from input digits and generated arry. demultiplexer is a data distributor. It has input data line, n selet lines and n output lines. demultiplexer an be used as a deoder. deoder has n input lines, -enable line and n output lines. Deoder IES MSTER De-MUX enable input ats as input data line in De- MUX. n-input lines ats as n seletion lines n -output ats as n outputs of De-MUX. De-MUX iruitry is built of ND gates. 47. () 48. (b) 49. (d) 5. () In synhronous sequential iruit, the external lok pulse is onneted to the first flip flop only. The suessive flip-flops are triggered by the output of previous flip flop. In asynhronous sequential iruit, lok is absent and state hange ours aording to delay times of the logi. Due to this they are more diffiult to design. ssertion is true, reason is false. Master Slave flip flop is used to prevent Rae round Condition when inputs J K. It uses two JK Flip flops - one Master and other slave. During the positive half of the lok Master responds and during negative half of the lok, slave output opies the Master Output. Ring ounter have following disadvantages : (i) The ring ounter an enter into any one of the invalid state due to noise without returning to main ounting sequene. (ii) Ring ounter is not Self Starting. Hene, onventional synhronous binary ounter or self orreting ring ounter is more reliable. Ring ounter are self deoding and does not require deoding logi iruit unlike sequential ounter whih requires deoder gates. ssertion is False. Reason is true. Synhronous ounter has higher speed of operation than ripple ounter. eause synhronous ounter has one lok for eah flipflop, ut in the ase of ripple ounter there is a different lok for different flip-flop. So the time taken by the ripple ounter is greater than the synhronous ounter, hene they are slow.