New Approach in Gate-Level Glitch Modelling *

Transcription

1 New Approah in Gate-Level Glith Modelling * Dirk Rae Wolfgang Neel Carl von Ossietzky University Oldenurg OFFIS FB 1 Department of Computer Siene Esherweg 2 D Oldenurg, Germany D Oldenurg, Germany Dirk.Rae@Informatik.Uni-Oldenurg.DE Neel@offis.uni-oldenurg.de Astrat An gate-level glith model for logi simulation is presented. This new approah an e used to enhane logi simulation auray and power estimation at little additional omputation osts. The simulation algorithm is ompatile with ommon event driven simulation models for glith-free ases. Only if a possile glith is deteted the simulation is modified y our model. The model is ased on ommon timing haraterization data and a few additional onstant values. The features of the model are sheduling of glith events and predition of glith peak voltages, whih are essential for preise power estimation. 1. Motivation Modern IC-prodution lines offer deep sumiron tehnologies. With the ever shrinking strutures new possiilities arise for higher degree of funtional integration, more omplex appliations in more handsome ases. For marketing, environmental and reliaility reasons a low power onsumption is gaining importane. For portale appliations the time of attery operation is limited y its energy onsumption. With the inreasing power onsumption of omplete hips ooling prolems arise whih dramatially influene the pakaging and its osts. The power redution of an appliation an e ahieved y tehnology improvements, voltage saling [1] and design deisions for low power [2]. Beause of the high demands on lowering energy onsumption all possiilities must e exploited. Within design for low power the power onsumption of a ertain design solution needs to e evaluated. The power * This work has een partly funded y the JESSI projet AC8 onsumption of urrently used stati CMOS tehnologies is dominated y dynami power onsumption (exept for very low-voltage supplies), i.e. the iruit ativities need to e analysed. Preise simulation tools on iruit-level (like SPICE) an not handle the omplexity of large iruits and huge numer of possile patterns. For this reason the power alulation is ased on iruit ativity analysis at logi level. In order to preisely alulate energy onsumption the logi node transitions must e examined arefully. It is important to note that multiple transitions within one lok yle and glithes signifiantly (typially around 15-2% ut in arithmeti units up to 65%[8]) influene power onsumption [4,5]. This influene strongly depends on the arhiteture. Within this paper a glith is defined as a pair of two or more olliding output waveforms whih are so lose together that the orresponding voltage waveform neither reahes V SS nor V DD in etween (f. fig. 1). A voltage [V] m. -5.m. 5.p input a 1.n 1.5n input Figure 1: Example for a glith at a NAND2-gate glith might even have a peak voltage whih is less than the ommon logi threshold voltage (typially around 5% V DD ). A dynami glith initially starts at V SS (V DD ) and ends at V DD (V SS ). The energy onsumption of a glith is usually less than that of the underlying omplete transitions and hene must e alulated differently. The new glith 2.n output a 2.5n 3.n 3.5n 4.n time [s] EURO-DAC 96 with EURO-VHDL /96 $ IEEE

2 model, whih is the sujet of this paper, inludes the determination of essential data to onsider glithes within the energy alulation. In the next setion the alulation of power onsumption of stati CMOS iruits on gate-level is explained. In setion 3 the new glith model is introdued and evaluated. A omparison with existing glith models is investigated in setion Power alulation of stati CMOS The average power onsumption of a single CMOS gate an e divided into three parts: P = P leakage + P short-iruit + P Cap The power onsumption due to leakage urrents is muh smaller than the other two dynami omponents and hene it is often negleted within power alulation. This is true exept for very low voltage supplies and as a onsequene for very low threshold voltages [2]. During swithing a onduting path through the pullup- and pulldown-network of a gate is present and as a onsequene a short-iruit urrent is ourring. The third omponent is the apaitive omponent whih takes into aount the apaitive loading of swithed apaitors. The alulation of the short-iruit power onsumption is done y I short-iruit V DD. The short-iruit urrent itself is hard to determine as it also depends on the apaitive urrent waveform [3,11]. Two omplete transitions (one from 1 and one from 1 ) result in a apaitive energy onsumption of 2 2 C L V DD. The energy 1 2 C L V DD is assoiated with eah transition. This later term does not stritly hold for single transitions eause the voltage supply only delivers power when the apaity is harged (i.e. not when it is disharged). But in this ase the assumption that the output apaity is lumped towards V SS doesn t hold either [1]. However for average power estimation the typial operation is foused on and therefore the total numer of transitions is quite high. I.e. that eah rising transition (exept maye the last transition within the sope) is followed y a falling transition (and vie versa) so that the total energy onsumption is alulated orretly. If an inomplete transition ours instead of a omplete transition its energy onsumption is: E Glith = 1 2 V DD Q Cap (1) = 1 2 V DD C L V This equation also holds for omplete transitions with V=V DD. The apaitive power alulation is straight forward: V 1 i P Cap = -- V (2) 2 DD C L lim i T T The sum V i an e otained y logi simulation over a suffiient time interval [9] using the proposed glith model. Equation 2 holds for all kind of glithes. As an example a dynami glith whih onsists of three ramps is illustrated in figure 2. voltage [V] m. -5.m 1.n 1.5n Figure 2: Example for a dynami glith Modelling aspets of ell ased stati CMOS iruits have een dealt with in [1] in detail. However a glith model was not inluded. 3. The proposed glith model 2.n It is often not onsidered [7], that for preise power estimation glithes may not e treated as two omplete transitions ut to predit the glith peak voltage even on gatelevel [6]. Using ommon logi simulation whih is ased on a transport or an inertial delay model does neither take glith peak voltages nor the orret event sheduling in ase of a glith into aount. To improve the event sheduling a dynami delay model was proposed in [7] whih unfortunately does not ontain information aout glith peak voltages. In [6] a model to predit glith peak voltages is proposed. This model laks dynami sheduling as in [7]. The proposed glith model within this paper takes oth into aount: orret sheduling and predition of glith peak voltage and hene delivers etter preision (f. setion 4). The aurate predition of glithes on gate-level relies on a good knowledge of delays. As the interonnetions are tending to dominate the total load of a gate and therefore its delay, a akannotation step is gaining importane for glith predition. Generally the proposed model an e used for any timing model whih ontains slope information. But the preision of the simulation results is strongly influened y the delay auray. V 2 V 1 2.5n 3.n V 3 time [s] 3.5n

3 A glith is typially generated y two olliding output ramps with opposite diretions whih are aused y two different input pins or a hazard at one input pin (i.e. a omplete falling ramp followed y a omplete rising ramp). This generated glith might e propagated through onseutive gates. It is important to note that the output of the andidate gate through whih the glith might e propagated must e sensile to the input at whih the glith arrives. I.e. the proaility of glith propagation dereases with the numer of gates in series (exept for an inverter respetively EXOR hain). Therefore the preision requirements on the model are muh higher for glith generation and propagation at the first ompared to the onseutive levels. It also should e emphasized that glithes tend to vanish or to e amplified to omplete transitions during propagation whih the model needs to take are of. The asi idea is to represent a glith y two or more linearly approximated ramps (f. fig. 3). The ramps an e a generation propagation Figure 3: Representation of glithes y linear approximated ramps easily derived from delay and slope information. A pair of a (olliding) setting and resetting ramp always represents a glith or part of it (in ase of more omplex glithes). If a glith is deteted, the seond ramp - defined as resetting ramp - is sheduled into the event queue differently than for a glith free ase. The reason for this is that the resetting ramp doesn t start from VDD (resp. VSS) for whih the gate delay is haraterised in the datasheets. The different sheduling of resetting glith ramps has a signifiant impat on the propagation of the generated glith. The remaining question is how to shedule a resetting ramp and how to predit the glith peak voltage. From the physial point of view, the voltage waveform s derivation is zero when the glith peak is reahed, i.e. no fanout apaity is either harged or disharged and the gate is in an equilirium state. Hene at this instant the gate s dynami operation point (V resetin, V setin, V(1 * )) (f. fig. 4) is approximately equal to the respetive stati operation point, whih leads to the idea to use stati harateristis for glith modelling. It is important to note, that stati harateristis neither depend on a gate s input slope nor on its fanout load. d Within the new model four harateristi voltage values are introdued for eah input-to-output-pin omination (f. fig. 4): V in (a)=v setin V in ()=V resetin V VF V TF V V setting input ramp resetting input ramp 3 * 4 * 1 * 2 * t 1 * real glith (from iruit-level simulation) 2 * non-olliding resetting output ramp (i.e. V in (a) = V DD ) 3 * dynamially sheduled resetting output ramp 2 * 4 * non-olliding setting output ramp (i.e. V in () = V DD ) - also refered to as V setout Figure 4: Glith model and its harateristi voltages for a NAND2-gate (f. fig. 3) V TF : Voltage of falling input slope at time point when glith peak is reahed at output of stage V VF : Voltage of falling input slope at time point when glith peak voltage of linearly approximated non-olliding setting output ramp is reahed V TR : same as V TF exept that the input slope is rising V VR : same as V VF exept that the input slope is rising Eah ell needs to e haraterized with respet to these voltages. The V TF - and V TR -values are used for sheduling the resetting ramp at the gate output. It is sheduled in suh a way that it rosses the setting output ramp when the resetting input ramp reahes V TF resp. V TR and the real glith (1 * ) its maximum V. The glith is represented y the two ramps for possile glith propagation. The V VF - and V VR -values are used to predit the glith peak voltage whih is needed to alulate the orresponding glith power onsumption (f. equation 2). The effet, that the setting (non-olliding) output ramp (4 * ) and the real glith (1 * ) diverge the more the resetting t t

4 input ramp takes ontrol of the glith, is modelled y taking different values for V V (V VF resp. V VR ) and V T (V TF resp. V TR ). Due to the diverging waveforms of the real glith and the non-olliding setting output ramp neither (V resetin =V V, V setin, V setout ) at the instant when the resetting input ramp rosses V V nor (V resetin =V T, V setin, V setout ) at the instant when the resetting input ramp rosses V T exatly are the same as the triple of the real glith reahing the equilirium state. Hene the parameters do have a small dependeny on the gate s output load and its input slope. This dependeny has een analyzed y means of iruitlevel simulation for various single stage gates. As a typial example a NAND2-gate of an industrial.5µm-cmos lirary (V DD = 3.3V) is disussed here. It was analyzed within the testenh shown in fig. 5. An inverter is used to get realisti input slopes at the inputs A and B of the GuT (gate under test). The input slopes of a and are modified y additional loads of the inverters. The apaitor etween and V SS represents the GuT s load. For various ominations of apaities glithes with different peak voltages were generated y varying the input skew. The simulation results are shown in figure 6. The ordinate 1V V VF 2.6V Figure 5: Investigation of harateristi voltage values V skew glith-generation Figure 6: V VF of a NAND2-gate for different iruit onfigurations axis ontains the values for V VF and the oordinate axis the a GuT real glith peak-voltage 3.5V glith peak voltage. The different urves orrespond to a variety of different apaitor onfigurations. Small glithes result in smaller V VF -values than igger ones. This harateristi ehaviour an e explained from the gate s stati operation urve (V over V with V a =V DD ). The impat of the setting input ramp (at a) is very low as it has reahed a voltage level lose to V DD for most ases when the glith reahes its peak. The few urves whih are not within the urve undle elong to very small loads at node and slow setting input ramps of the GuT. For these ases the voltage of the setting input ramp is omparatively small when the glith reahes its peak. However, the affeted glithes result in very little power onsumption and are no andidates for glith propagation as the load is smaller than the smallest fanin apaity of a gate within the lirary. For gate-level simulation purposes an approximation of the harateristi values (V VF, V TF,...) y a onstant average value is proposed. However, for improving the simulation preision the harateristi values dependeny on the glith peak an e onsidered y alulating the glith terms from the following equations: (V resetin (t), V setout (t)) = (V V (V setout ), V setout ) resp. (V resetin (t), V setout (t)) = (V T (V setout ), V setout ). The simulation results of V TF of the NAND2-gate are aout.4v elow those of V VF and their harateristi urve waveforms look similar. The values of V VR and V TR for a NAND2-gate an only e determined y applying a hazard or a glith to one input pin. The glithing ehaviour strongly depends on the harateristi non-linearity of eah CMOS stage. Hene glith simulation should e done stage y stage. It is important to note that for power estimation purposes of glith-free ases transitions at stage output nodes whih are internal nodes of a gate annot neessarily e monitored at the gate output terminals. If a stage y stage simulation is not feasile the harateristi glith values (V VF, V TF,...) annot e used as for single stage gates. On the ost of auray the proposed model an e adapted to multi stage gates y introduing an initial time-shift of the resetting input ramp. 4. Evaluation of proposed model The proposed model is ompared to the models presented in [6,7] with respet to iruit-level simulation y using a small enhmark iruit (f. fig. 7 - the driving inverters for signal a and are not shown). For the proposed model also non onstant parameters V V and V T were analyzed (this model is referred to as proposed model ). The following parameters were varied: skew: in steps of 6ps two different slopes at input a two different slopes at input four different loads at

5 a generation 2 nd propagation 1 st propagation Figure 7: Benhmark iruit for evaluation of glith model four different loads at d four different loads at e For glith analysis at node six further slopes for oth inputs a and and four further loads at were investigated. Only ases whih produe glithes for at least one of the models at the respetive level (, d and e) were onsidered. In total approximately 178 different ases were examined. The delays and the slopes were diretly determined y iruit-level simulation for eah ase (i.e. the fous is on glith modelling and not on delay modelling of non-glithing transitions). The harateristi glith parameters (V VF, V TF,...) for the proposed model and the model presented in [6] were determined efore. Model [7] is asially not intended to predit glith peak voltages. We extended the model y reading the voltage of the setting output ramp when the glith peak is predited. The setting output ramp is therefore onstruted y the following two points (f. fig. 8): V(a) 1 d e the glith peak time (fig. 11: mean value), the relative numer of ases resulting in no transition within iruit-level simulation and a hazard (i.e. two omplete transitions) for the logi model (fig. 12), the amount of glithes on iruit-level whih are deteted as glithes y the respetive logi model (fig. 13). Glith Peak Voltage Error [V] Figure 9: Mean value of glith peak voltage error Glith Peak Voltage Error [V] V setout () logi waveform 2 modelled waveform Figure 1: Standard deviation of glith peak voltage error 2 Figure 8: Ramp onstrution to make peak voltage estimation possile for [7] time when the output voltage equals V DD /2 (whih is a possile logi swithing threshold), time when the setting input voltage equals V DD /2 the setting output ramp starts from the initial voltage V SS or V DD. For further details refer to [7,12]. In figures 9-11 the statistially analyzed differene etween the simulation results ahieved y iruit-level simulation and the gate-level model is shown (i.e., value iruit-level value model ). The presented values are: the glith peak voltage V error (fig. 9: mean value; fig. 1: standard deviation), Glith Peak Time Error [ps] Figure 11: Mean value of glith peak time error Please note, that the results for the glith peak voltage (fig. 9 and 1) were ased on the ases where any of the models

6 AAA AAA AA A AA A Figure 12: Relative amount of ases whih result in no transition for iruit-level simulation and a hazard for the gate-level model in % Figure 13: Relative amount of simulated glithes on iruit-level whih are deteted y the gate-level model in % or the iruit-level simulation result in a glith. I.e. these figures an e used only for relative omparisons. The missing dynami sheduling methodology in model [6] learly results in a pessimisti glith estimation (i.e., the glith peak voltage is signifiantly overestimated for d and e (fig. 9); glithes are less likely to e filtered during propagation (fig. 12); the glith peak time is estimated too late for, d and e (fig. 11)). Comparing the results of [7] and the proposed model with eah other the peak voltage is estimated more preisely y the proposed model. The glith peak time is estimated suffiiently aurate y oth models. However the proposed model detets more of the glithes on iruit-level than model [7] does. By using nononstant values for V T and V V the simulation auray on the one hand an e improved a little. On the other hand more haraterization data is needed and the simulation performane will e dereased. The glith parameters for the model [7] are fixed y the definition of the logi threshold voltages (here 5% VDD) and hene annot e adjusted to a different glithing ehaviour like for the model [6] and the proposed model. 5. Conlusions and future plans Within this paper an attrative way to simulate glithes on gate-level - inluding aurate sheduling and determination of peak voltages - has een introdued. On the ost of only four additional haraterization values per input-tooutput pin omination of eah stage the power simulation an e signifiantly. By the omparison with the approah of [6,7] signifiant progress was demonstrated. This model is urrently eing integrated within the Leapfrog Simulator of Cadene. Additionally a stand alone simulator is under implementation for aurate power estimation. 6. Referenes [1] B. Davari, R.H. Dennard, G.G. Shahidi. CMOS Saling for High Performane and Low Power - The Next Ten Years. Proeedings of the IEEE, Vol. 83: , April 1995 [2] A.P. Chandrakasan, R.W. Brodersen. Minimizing Power Consumption in Digital CMOS Ciruits. Proeedings of the IEEE, Vol. 83: , April 1995 [3] H.J.M. Veendrik. Short-Ciruit Dissipation of Stati CMOS Ciruitry and its Impat on the Design of Buffer Ciruits. IEEE Journal of Solid State Ciruits, Vol. SC-19 NO. 4: , 1984 [4] J. Leijten, J. Meerergen, J. Jess. Analysis and Redution of Glithes in Synhronous Networks. Proeedings of the European Design and Test Conferene: , 1995 [5] M. Favalli, L. Benini. Analysis of glith power dissipation in CMOS ICs. Proeedings of International Workshops on Low Power Design: , 1995 [6] C. Metra, M. Favalli, B. Riò. Glith Power Dissipation Model. Power and Timing Modeling of Integrated Ciruits: , 1995 [7] M. Eisele, J. Berthold. Dynami Gate Delay Modeling for Aurate Estimation of Glith Power at Logi Level. Power and Timing Modeling of Integrated Ciruits: 19-21, 1995 [8] M.A. Ortega, J. Figueras. Bounds on the Hazard Consumption in Modular Stati CMOS Ciruits. a Talk (unpulished) on Power and Timing Modeling of Integrated Ciruits 1994 [9] R. Burh, F.N. Najm, P. Yang, T.N. Trik. A Monte Carlo Approah for Power Estimation. IEEE Transations on VLSI Systems, Vol. 1: pg , Marh 1993, [1] D. Rae, B. Timmermann, W. Neel. CMOS Lirary- Charaterization for Power Consumption. Power and Timing Modeling of Integrated Ciruits: 94-15, 1994 [11] D. Rae, W. Neel. Short Ciruit Power Consumption of Glithes. Proeedings of Symposium on Low Power Eletronis and Design, 1996 [12] D. Rae, B. Fiuzynski, L. Kruse, A. Welslau, W. Neel. Comparison of Different Gate Level Glith Models. Power and Timing Modeling of Integrated Ciruits, 1996