2. PRELIMINARY ANALYSIS

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1 New Paradigm for Low-power, Variation-Tolerant Ciruit Synthesis Using Critial Path Isolation Swaroop Ghosh, Swarup Bhunia*, and, Kaushik Roy Shool of Eletrial and Computer Engineering, Purdue University, IN, US *Eletrial Engineering and Computer Siene, Case Western Reserve University, OH, US bstrat Design onsiderations for robustness with respet to variations and low power operations typially impose ontraditory design requirements. Low power design tehniques suh as voltage saling, dual-v th et. an have a large negative impat on parametri yield. In this paper, we propose a novel paradigm for low-power variationtolerant iruit design, whih allows aggressive voltage saling. The prinipal idea is to isolate and predit the set of possible paths that may beome ritial under proess variations, ensure that they are ativated rarely, and () avoid possible delay failures in the ritial paths by dynamially swithing to two-yle operation (assuming all standard operations are single yle), when they are ativated. This allows us to operate the iruit at redued supply voltage while ahieving the required yield. Simulation results on a set of benhmark iruits at 7nm proess tehnology show average power redution of % with less than % performane overhead and 8% overhead in die-area ompared to onventional synthesis. ppliation of the proposed methodology to pipelined design is also investigated.. INTRODUCTION It is well-known that proess parameter variations (both systemati and random) may ause parametri failures in logi iruits leading to yield loss. Conventional wisdom ditates a onservative design approah (e.g., saling up the V DD or upsizing logi gates) to avoid a large number of hip failures. However, suh tehniques ome at the ost of power and/or die area. Proess tolerane and low power, therefore, represent ontraditory design requirements. Over the past few years, statistial design approah has been widely investigated as an effetive method to ensure yield under proess variations. Several gate-level sizing and/or V th assignment tehniques [] have been proposed reently addressing the minimization of total power while maintaining the timing yield. On the other end of the spetrum, design tehniques (e.g., adaptive body biasing []) have been proposed for post-silion proess ompensation and proess adaptation to deal with proess-related timing failures. Due to quadrati dependene of dynami power of a iruit on its operating voltage, supply voltage saling has been etremely effetive in reduing the power dissipation. Researhers have investigated logi design approahes that are robust with respet to proess variations and, at the same time, suitable for aggressive voltage saling. One suh tehnique [3] uses dynami detetion and orretion of iruit timing errors to tune proessor supply voltage. Design optimization tehniques using gate sizing and dual-v th assignment to improve power/area typially inrease the number of ritial paths in a iruit, giving rise to the so-alled wall effet [4]. The unertainty-aware design tehnique [4] desribes an optimization proess to redue the wall effet. However, it does not address the problem of power dissipation. In this paper, we present a novel design paradigm, whih ahieves robustness with respet to timing failure and provides the opportunity for aggressive voltage saling by ritial path isolation. The notion ritial path isolation is used throughout this paper to indiate the Permission to make digital or hard opies of all or part of this work for personal or lassroom use is granted without fee provided that opies are not made or distributed for profit or ommerial advantage and that opies bear this notie and the full itation on the first page. To opy otherwise, to republish, to post on servers or to redistribute to lists, requires prior speifi permission and/or a fee. ICCD', November 5-9,, San Jose, C Copyright CM //...$5. onfinement of ritial paths of synthesized design to known logi blok (or ofator, as we will see later). Suh isolation leads to a design methodology for low power dissipation by making the ritial paths preditable and rare under parametri variations. ny possible delay errors (that may our under a single yle operation) are predited ahead of time and are avoided by two yle operations (assuming all standard operations are single yle). This lets us sale the supply voltage aggressively for low power dissipation. In partiular, the proposed tehnique: Isolates the ritial paths and makes them preditable (by deoding few primary inputs) under parametri variations so that with redued supply voltage, possible delay errors are deterministi and an be avoided by two yle operation. Restrits the ourrenes of the above two-yle operations by reduing the ativation probability of ritial paths. Inreases the delay margin between ritial and non-ritial paths by both logi synthesis and proper gate sizing for improved yield, reliability of operations and low power by voltage saling. We also present an appliation of the proposed methodology in pipeline based design for low power operation. The iruit is redesigned to operate at fied low supply voltage with oasional twoyle operations. The two-yle operations are implemented by stalling the pipeline. Some researhers have proposed tehniques to orret variabilityindued timing error during operation by voltage saling. The tehnique in [3] referred as RZOR, redues or eliminates voltage margins by dynami saling of the supply voltage while monitoring the error rate. Razor allows the ourrene of errors at low voltage and then reovers. However, it does not modify the logi synthesis or gate sizing proess and thus an perform poorly in presene of large number of ritial paths. The tehnique proposed in this paper, on the other hand, synthesizes a iruit in speifi way to failitate voltage saling for power redution as well as to improve yield by making the delay failures deterministi.. PRELIMINRY NLYSIS In this setion, first we present eample of an adder to illustrate the proposed approah for low power robust iruit design. Net, we present the design flow followed by its analysis whih allows us to apply similar approah to any random logi iruit... Voltage saling and two-yle operations in a 4-bit adder For the sake of simpliity, we hoose a 4-bit ripple arry adder as shown in Fig.. Signals P -P 3 (G -G 3 ) are the propagate (generate) signals whereas C i, (C o, -C o,3 ) are arry-in (arry-out) signals [5]. s evident, the path from arry-in to arry-out is ritial and determines the frequeny of operation of the adder. However, note that the ritial path is ativated only when C i, = and at the same time, P P P P 3 =. Sine the probability of suh ourrenes is very low (as p(p P P P 3 C i, =) = p(p )p(p )p(p )p(p 3 )p(c i, ) is very low), one an redue the supply voltage suh that all operations with P P P P 3 = and/or C i, = an still be performed in one-yle. However, when the ritial path is ativated, the orret results are obtained by evaluating the adder in two lok yles (alled two-yle operation). The ativation of ritial path an be predited by pre-omputation of P P P P 3. In a nutshell, by making the ritial path preditable and utilizing the available slak between ritial and non-ritial path, it is possible to operate the iruit at redued supply voltage. Note that this approah inurs penalty of an etra lok yle when the ritial path is ativated. However, by ensuring low ativation probability of 9

2 Ci, Number of paths P G P G P G P 3 G 3 C o, C o, F F F F Fig. Path delay distribution needed for the proposed methodology ritial paths, it may be possible to redue the ative and leakage power by rarely paying penalty of an etra lok yle. To evaluate the feasibility of this idea, we simulated a 4-bit ripple arry adder with V supply in Hspie. We used BPTM [] 7nm devies for simulation. The ritial path delay was found to be ps and average power onsumption was 3.3uW. ssuming the lok period to be ps, we redued the supply to.8v. Now the non-ritial paths were within the single-yle delay bound however, the ritial path delay inreased to 33ps and was evaluated with two-yles. The power onsumption was 7.3uW, leading to 44% saving in total power... Generalization to random logi Earlier, we presented the idea of supply voltage saling for an adder where the ritial path was unique (assuming no proess variation). However, a random logi an have many ritial paths with orresponding input onditions for ativation. Further, the ritial paths may vary from hip-to-hip due to parametri variations. In suh situations, the overhead assoiated with pre-deoding logi an overshadow the power savings. To eerise similar supply saling tehnique on random logi iruits, we need to make sure that, the ritial paths are onfined to a preditable logi setion; and, the nonritial paths remain non-ritial under proess variation by providing a safe timing slak. The timing slak between ritial and non-ritial paths will be the enabling fator for supply voltage saling. n eample of a possible path delay distribution (artoon) is shown in Fig.. To obtain the delay distribution shown in Fig., the design needs to be partitioned and synthesized in suh a way that the paths are divided into several logi bloks. The partitioning proedure should onsider the fat that these logi bloks an be ative or remain idle based on the state of primary inputs; and, the probabilities of ativation of the logi bloks ontaining ritial paths (alled ritial blok) are very low. Therefore, it will be possible to predit the ativation of a logi blok (and the orresponding paths) just by deoding the states of inputs. Net, gate sizing an be performed on the partitioned logi bloks to maimize the slak between ritial and non-ritial bloks leading to further isolation of ritial paths. Note that the suggested sizing approah will be opposite of the onventional sizing beause in this ase, the ritial paths should be made slower while non-ritial paths should be made faster. By performing the partitioning and sizing, a path delay distribution similar to the one shown in Fig. an be C o, Fig. Ripple arry adder [5] path delay One-yle delay target C o,3 preditable and restrited to a logi setion having low ativation probability slak Input : Optimized netlist. Perform an input based partitioning of the netlist suh that the ativation probability of ritial logi bloks are very small.. Perform gate sizing on logi bloks to reate timing slak between ritial and non ritial bloks. 3. Perform supply voltage saling while meeting the yield for non ritial (ritial) bloks in one yle (two yle). Output : Sized netlist and supply voltage Fig. 3 Design methodology ahieved. Finally, supply voltage saling an be done suh that nonritial bloks meet the desired timing yield with respet to one-yle delay target whereas ritial blok meet the yield with respet to twoyle delay target. In other words, the ritial bloks an operate in two-yles while the non-ritial bloks an operate in single-yle. Sine the probability of ativation of the ritial blok is low, the design operating at a saled voltage will have minimum impat on performane. The overall design strategy is shown in Fig. 3. The partitioning and sizing is more learly illustrated in Fig. 4 where a iruit is partitioned into four funtional logi bloks f -f 4. The outputs are fed to an OR network to generate the final outputs. Suppose that by the virtue of proper partitioning, f 4 beomes the least ativated funtional blok ontaining the ritial paths. Then f 4 an be downsized further while the other funtional bloks an be upsized to maimize the slak and further isolation of ritial paths, as shown by arrows in Fig. 4. In Setion 3, we will desribe a Shannon based partitioning tehnique whih helps in isolating the ritial paths..3. nalysis of the proposed design methodology Let us onsider two different designs for the same ombinational iruit, design- and design-b with timings as shown in Fig. 5. Design- (design-b) is representative of onventional design (proposed design). In design-, the slak of ritial path is S with respet to the lok period T whereas in design-b, the ritial path (shown by hathed lines in Fig. 5) does not meet the timing onstraint and has a negative slak of S 3. However, the non-ritial paths (shown by dotted blok in Fig. 5) in design-b maintain a maimum slak for S. We also assume that the ativation ondition of ritial paths in design-b is known based on the states of few inputs (say, N). n etra deoder is needed in design-b for pre-determining the ourrenes of ritial path ativation. Obviously, design-b an funtion properly with two-yle operations for ritial paths while a single yle operation for non-ritial paths. Let us now ompare the power onsumption of design- and design-b where V is the voltage at whih design- meets the slak requirement S, whereas, design-b meets slak S for non-ritial paths and S 3 for ritial paths. Sine voltage is proportional to (delay) -, the saled voltage ( V design- an be determined as follows, S V and, V V = V T S T T ) for () Primary inputs f 4 CLK 4 CF 3 Original Ciruit f 3 f OR Network PO Design T S EDP /EDP B CF i MUX Primary outputs Fig. 4 Steps and of proposed design methodology f Design B S S 3 Fig. 5 Timing diagram of design- and design-b 5 N..4. S Fig. Plot of EDP ratio of design- and design-b for k =., n o r m C =. and n = 4 d.8 scf Fig. 7 Shannon s epansion based partitioning

3 Fig. 8 Original iruit f f Input : Original netlist, rea onstraint (ma), delay onstraint (Dma). Read netlist and reate graph G, Level =. Initialize glist = {G} 3. Make epansion deision for the graphs in glist 4. urrlist = ll graphs in glist 3 f (CF) 5 9 Similarly, S () VB = V ; s. t. S+ S3 T T If the performane penalty due to two-yle operation in design-b is p, then the effetive lok yle delay of design-b is T + pt. The energy-delay produt (EDP) of both designs are given by EDP = C( V ) ( T ); EDPB = ( CB+ Cd )( VB ) ( T + pt ) (3) where C (C B ) is the average swithed apaitane of design- (design-b) and C d is the average swithed apaitane of the deoding logi (for determination of ritial path ativation). The EDP ratio (after putting the values of V and V ) is given B by: EDP S T S = = C C S B d + p C + C S + p B B d ( ) EDP + C C T where, C ( B C ) is the average swithed apaitane of design-b d (deoder logi) alized with respet to C and S ( S ) is the slak of design- (design-b) alized with respet to T. From the epression shown in equation (4), it is possible to study the onditions under whih it may be useful to opt for design-b rather than design-. It is obvious that design-b an be better than design- if EDP /EDP B >. Sine ( CB + Cd ) > (assuming C B C due to design modifiations) and ( + p) >, a neessary ondition for design- B to be better than design- is, S > S i. e., S > S (5) f (CF) f (CF) 7 Fig. 9 Control variable is 4 : CF ; CF 4 f (CF) f (CF) f (CF) Therefore, a larger value of S is better for power savings. However, the upper bound of S is determined by onstraint S + S 3 T (equation ()). Hene, S an be maimized by minimizing slak S 3. Let us eplore the design spae for whih design-b an be benefiial. For the sake of simpliity, we model the alized apaitanes and performane penalty (p) as follows, k N CB = + ; Cd = NCd, S =.5 and, p= n ( S ) where k is a onstant, N is the number of input vetors that should be deoded to determine if ritial paths are ativated, C is the d alized average swithed apaitane of deoding a single input f (CF) 9 Fig. Control variable is : CF ; CF f (CF) (4) No No vetor and, n is the total number of primary inputs of the iruit. The EDP ratio plotted for different values of N and S is shown in Fig.. From the EDP ratio profile shown in this figure, it is obvious that design-b is benefiial only if N is small (to minimize the swithed apaitane of deoding logi). lso, the initial flat portion of the profile indiates that S should be greater than S. lthough the EDP urve inreases with S the swithed apaitane of the iruit (i.e., a large value of S may inrease C if gate sizing is used) B and offset the saving in power. In the analysis presented above, it an be onluded that the power saving in proposed method mainly omes from quadrati dependeny of power on voltage. Power redues quadratially while the delay inreases only linearly, letting us redue the EDP. 3. DESIGN METHODOLOGY Based on the analysis and the guidelines derived above, we desribe the details of eah step of the design flow (Fig. 3). This is followed by simulation results on a set of benhmark iruits. 3. Ciruit partitioning and synthesis for ritial path isolation Let us first onsider performing an input based partition of the iruit suh that the ritial paths are isolated and their ativation probability is redued. To ahieve this, we used Shannon epansion based partitioning [7] whih partitions a Boolean epression f into disjoint sub-epressions as shown below: f (,...,,..., ) =. f (,..., =,..., ) +. f (,..., =,..., ) i n i i n i i n =. CF +. CF i 5. For eah graph G i in urrlist 9. ll graphs of urrlist traversed? i. Is G i marked for epansion? Yes 7. Choose a ontrol variable andepand G i into CF, CF, scf 8. Remove G i from glist. dd CF, CF, and scf to glist CF = f (,..., i =,..., n ); CF = f (,..., i =,..., n ) where ( n ) are input literals, i is ontrol variable, and CF and CF are alled ofators. If f ontains sub-epressions independent of ontrol variable i, then we may also have a Shared Cofator (scf) (Fig. 7). In this work, we have used Shannon epansion based partitioning mainly due to its following inherent properties: the iruit partitioning is done based on inputs; the ativation probability of partitioned logi bloks an be easily redued by performing multi-level hierarhial epansion; and, () by properly hoosing the ontrol variables, it is possible to isolate the ritial paths to a logi blok having least ativation probability. In the following paragraphs, first we eplain multi-level epansion for redution of Yes. rea < ma and Delay < Dma No Output : glist Fig. utomated synthesis flow Yes Level++ ()

4 # ontrol variables CF 53, CF 3 : 3 CF 3 : CF : Original Ciruit CF CF3 CF4 CF53 3 CF3 3 MUX Network PO # of paths 8 benhmark: st, V = V DD 4 ritial CF ritial paths 4 Delay [s] # ontrol variables CF : 4 CF : 3 CF3, CF4 : CF LEVEL LEVEL LEVEL3 Fig. Hierarhial epansion and sizing of ofators ativation probability of ofators, followed by the ontrol variable seletion strategy for ritial path isolation during partitioning. In equation (), the ativation probability of eah ofator is 5% (assuming 5% swithing probability of inputs). By performing multilevel epansion, the ativation probability of the resulting ofators an be redued further. For eample, a nd level epansion of f (equation (7)) results in four ofators, eah with an ativation probability of 5%. f (,...,,..., ) =. CF +. CF +. CF +. CF (7) i n i j i j i j 3 i j 4 Control variable seletion plays a very important role in ahieving desired goals in Shannon s epansion based partitioning. In [8, 9], the most binate variable is hosen as ontrol variable to minimize the area overhead. However, this heuristi may not lead to the onfinement of ritial paths of the iruit after epansion. For eample, onsider a multiple-output two-level Boolean logi funtion f= and f = From the iruit realization shown in Fig. 8, it an be observed that f is the ritial funtion (or ritial output). If n( i ) is the total literal ount of i in f and f then, n( )=4, n( )=, n( 3 )=, n( 4 )=4, n( 5 )=n( )=n( 7 )=n( 8 )=n( 9 )=. Considering most binate variable as the preferable hoie, either or 4 an be piked as ontrol variable. With 4 as ontrol variable, resulting ofators are shown in Fig. 9. It an be notied that the ritial paths are distributed between the ofators. However, if is hosen as ontrol variable, the ritial path has been onfined to f (CF ) (Fig. ). Clearly, a strategy is needed to isolate the ritial paths and limit them to a partiular ofator. If a i (b i ) is the literal ount of variable i in true (omplement) form in the ritial funtion (or output), then following riterions should be fulfilled: (i) the ontrol variable should be present in ritial funtion (i.e. min(a i, b i ) > ); (ii) differene of a i and b i should be large to ensure that the paths are isolated to one ofator and, (iii) the ma(a i, b i ) should be small to minimize the probability of logi depth of isolated ritial paths being redued by logi optimization. Following metri an be used: TBLE- Proedure performsizing() Input : target delay (T ), yield (Y), list of ofators (glist); Output : sized netlist;. malevel = maimum hierarhy of the ofators in glist ;. run SST on G i glist; 3. ritcf=ofator with ritial paths at malevel hierarhy; 4 for eah ofators G i glist 5. alulate G i mudelay;. end for 7. dtarget = αt ritcf mudelay; 8. downsize(ritcf, dtarget, Y); 9. ritdelay = ritcf madelay + ritcf mudelay;. for eah ofators G i glist. if G i ritcf. dtarget = ritdelay - T - G i mudelay ; 3. upsize(g i, dtarget, Y); 4. end for 5. dd mu s in G i glist to reate a omplete graph G;. return G; # of ouranes # of ouranes Benhmark: st, simulation, V DD = V Org: Critial path delay distribution of original kt CF CF4: Cofator wise ritial path delay distribution of proposed kt CF 4 CF 3 one yle delay target CF CF Org Delay[seonds] Benhmark: st, simulation, V =.7V DD CF CF4: Cofator wise ritial path delay distribution of proposed kt () CF 4 CF 3 CF one yle delay target two yle delay target CF Delay[seonds] Fig. 3 Results for benhmark st: path delay distribution after partitioning and sizing;ofator-wise ritial path delay distribution under V t variation (V DD =V), () V DD =.7V ai bi Mi = (8) ma( ai, bi ) literal with maimum value of M i ensures that the ritial path is isolated to a ofator. Using this metri, we follow the steps desribed in [8] for hoosing the ontrol variable in our synthesis flow. To ahieve the dual objetives of isolating the ritial paths to a ofator while reduing its ativation probability during partitioning and synthesis, we adhere to following approah: we partition the iruit and determine the ofator where the ritial paths have been isolated (alled ritial ofator); we mark this ofator (i.e. ritial ofator) for further epansion to redue the ativation probability of the ritial paths. The above mentioned steps are repeated under a given area and delay onstraint. Note that Synopsys Design Compiler [] has been used for synthesizing the ofators. The overall synthesis flow is shown in Fig.. omplete eample of hierarhial partitioning and synthesis is also illustrated in Fig. where the original iruit is partitioned into four ofators, CF, CF 3, CF 53 and CF 3. The ritial paths have been isolated to CF 53 (whih is ativated by 3 inputs i.e. 3 ). Note that, in this eample we do not have the shared ofator (scf). Shared ofators are important in avoiding the logi dupliation during partitioning. However, they are independent of ontrol variable. Therefore our synthesis flow (Fig. ) automatially hooses it for further epansion (if ritial paths are isolated to it). 3. Gate Sizing for further isolation In the previous subsetion, we presented a iruit partitioning method to isolate the ritial paths to a ofator with small ativation probability. The net step is to size the resulting ofators individually to further isolate the ritial paths and, reate timing slak between ritial and non-ritial ofators to allow lowering of supply voltage. To ahieve this goal, all gates of the ritial ofator are downsized to make the orresponding paths further ritial. The gates belonging to the remaining ofators are seletively upsized to make them more non-ritial and inrease the slak (S, as disussed in Setion.3). n eample of the proposed sizing approah after

5 V D D [V ] ht st ple mu deod m5a alu ount Fig. 5 Eample of a pipeline design using proposed method partitioning is shown in Fig.. The ofators with dashed (solid) lines indiate epanded (non-epanded) iruits and levels indiate the hierarhy. s shown in the figure, ofator CF 53 is downsized to make it further ritial while other ofators are upsized to make them more non-ritial. Note that the proposed sizing approah is very different from the onventional sizing beause in this ase, the ritial paths are made slower while non-ritial paths are made faster. We follow the above mentioned sizing strategy in a Lagrangian Relaation (LR) based gate sizing [] as shown in Table. Given a delay target (T ), it tries to meet the yield requirement with minimum area. The proedure takes glist (i.e., list of ofators) and determines the ofator at highest level of hierarhy, malevel for downsizing it. The target delay (dtarget) for sizing the ritial ofator andidate (i.e. ritcf) is omputed in Step 7 (with α=., determined empirially to allow minimization of S 3 as disussed in Setion.3). The delay targets of non-ritial ofators are obtained by subtrating T and multipleer delays from overall ritial path delay (Step ). The nonritial ofator andidates are now upsized while meeting the yield target (Step 3). The desription of Table is omitted for brevity. 3.3 Determination of supply voltage fter iruit partitioning and sizing, we obtain the path delay distribution similar to Fig.. Now we may assign a lower supply voltage to redue the power dissipation while meeting robustness. To ahieve this, we start from nominal supply and iteratively redue it with two stopping riterions: delay violation of any of the nonritial ofators (one-yle delay target) for the given yield onstraint; and, delay violation of the ritial ofator (two-yle delay bound) for the target yield. Finally, another stopping riterion is the 3V th limit for reliable super-threshold operations [5]. The voltages for a set of MCNC benhmarks are shown in Setion Simulation results In previous setions, we presented a methodology to make the possible delay errors (that may our under single-yle operation) preditable and rare (using iruit partitioning and sizing). We also disussed the determination of supply voltage. In this setion, we present simulation result on a set of MCNC benhmarks to demonstrate the feasibility of this methodology. In partiular, we show isolation of ritial paths to a ofator (having low ativation probability); redution of supply voltage for low power dissipation while maintaining robustness. In the following paragraphs we present simulation setup followed by the results and disussion. For logi optimization in our synthesis flow, we have used Synopsys Design Compiler []. For a basis of omparison, the original benhmarks are also optimized for area in Synopsys. The mapping is done to a standard ell library. The iruit delays are omputed by using SST for BPTM 7nm tehnology. The % Imp. in power 8 4 % imp in power with input swithing prob =. % imp in power with input swithing prob =.5 ht st ple mu deod m5a alu ount re a ( 3 ) () Original design Proposed design ht st ple mu deod m5a alu ount Fig. 4 Supply voltage of proposed design; % improvement in power; and, () rea overhead CLK freeze D D D 3 7ps ht 8ps mu D, D, D 3 are deoding logi 85ps m5a outputs TBLE- Proedure pipelinedesign() Input : yield (Y), list of iruits(dlist), V DDL ; /* V DDL < V */ Output : list of re-designed iruits (dlist); target delay (T ) = ma(stage delays); for eah design D i dlist glist = performpartitioning(d i, V DDL ); /*Fig. */ D i = performsizing(glist, T, Y, V DDL ); /*Table */ end for return dlist; N inreases 4 8 k Fig. Performane penalty for ritial ofator at k=4, different values of k parametri variations (L, T o, doping et) have been lumped into threshold voltage variation. The hange in V th due to inter-die ( Vt inter ) and intra-die ( Vt intra ) proess variations are modeled as Gaussian variables with zero mean and standard deviations of 8mV and 4mV, respetively. The total hange in transistor V th is given by the summation of Vt inter and Vt intra. The delay target (T ) for sizing proedure is hosen by plotting the area-delay urve of the iruit and seleting the delay at whih the slope of the urve is -. The area and delay onstraints for Shannon based partitioning are kept at 4% and % more than original area and delay respetively. The yield targets of original iruit and the ofators for gate sizing are set to 95%. The yield target of ofators operating on one-yle (two-yle) after appliation of redued supply is fied to 95% (%). For power estimation, the iruits are simulated in Hspie by applying a set of random input patterns having input swithing probabilities of. as well as.5. The runtime of the entire methodology is found to be small (.3s for largest benhmark ht on SUN blade workstation). To illustrate the isolation of ritial paths to the ritial ofator, we have plotted the path delay distribution of an eample MCNC benhmark iruit (i.e., st) after partitioning and sizing (Fig. 3). This figure learly indiates that the ritial paths of the re-synthesized design are limited to the ritial ofator. We also present it s ofator-wise ritial path delays distribution under proess variation (V th variation, Fig. 3). From this figure, note that: CF remains ritial even under parametri variation while the other ofators remain non-ritial and; there is a delay slak present between CF and other ofators. lso, note that the ritial ofator CF is at the 4 th hierarhial level (i.e. 4 ontrol variables) to minimize its ativation probability. The delay distribution at redued supply is shown in Fig. 3 (). It shows that CF operates in two-yles while rest of the ofators operates in single-yle. In Fig. 4, we show the area, power and supply voltage for a set of MCNC benhmark iruits. It an be observed from Fig. 4 Performane penalty (%) N=5 # of ontrol variables for ritial ofator vs. performane penalty N= 3

6 that supply voltage required for the re-designed iruits are signifiantly less than nominal supply (V). This results in % average saving in total power as shown in Fig. 4. The partitioning is performed suh that the ritial ofators of all the benhmarks are at the 4 th level of hierarhy. Therefore, the ativation probability of ritial paths (thereby, the number of two-yle operations) is very low. This is also disussed in net setion. Fig. 4 () shows the area overhead (8% on average) assoiated with the proposed design methodology. This omes from two soures: logi dupliations during Shannon based partitioning and; upsizing of ertain ofators. However, for two benhmarks namely, ht and m5a, we observed area improvement. This is mainly due to better optimization after ontrol variable isolation and multi-level Shannon epansion [8]. It is worth noting that even if the iruit path delays are skewed towards the target delay (as in many industrial iruits), it is possible to reate a delay slak by proper partitioning and sizing. 4. PPLICTION IN PIPELINE BSED DESIGN In this setion, we investigate appliation of the design methodology desribed in Setion 3 to pipeline-based design. We assume that eah pipeline stage is designed using this methodology. 4.. Pipeline design methodology and performane analysis Our pipeline design methodology is based on a given redued supply voltage onstraint. The proedure is shown in Table. The maimum stage delay is hosen as target delay (T ) for all the stages (step-). Net, one design is piked at a time and iruit partitioning is performed as eplained in Setion 3 (step-3). Note that the delays are omputed by using SST at speified supply voltage (V DDL ). The output of step-3 is a list of ofators whih is sized to meet the required delay target at supplied voltage (step-4). Steps- to 5 is repeated on eah of the stages. Net, let us evaluate the performane of the pipeline design. Consider a 3-stage linear pipeline after re-design (Fig. 5) where deoders D, D and D 3 predit the ativation of ritial ofators of the individual stages. two-yle operation is needed whenever the ritial ofator of any of the pipeline stages is ativated. Under suh irumstanes, the pipeline is stalled by gating the lok (using signal freeze in Fig 5). Let p i be the ativation probability of ritial ofator of i th stage and p total is probability of two-yle operation in the pipeline. Further, we assume that ritial ofators of eah of the stages have same number of ontrol variables. Hene, p = p =... p (input swithing ativity) k N= p= (9) where k is the hierarhy (or, number of ontrol variables) of ritial ofator. Then p total is given by p ( ) N total = p () If the ideal lok yle-per instrution () of the pipeline is given by ideal, then the is given by = ideal + ptotal.(stall penalty) () The performane penalty due to oasional two-yle operation is given by ideal ptotal.(stall penalty) ptotal Perf. penalty = = = () ideal + ptotal.(stall penalty) + ptotal The performane penalty for different N and input swithing ativities is shown in Fig.. In this plot, we assume that the ritial ofator of eah stage is ativated by 4 inputs (i.e. k = 4). It an be observed from this plot that with the swithing ativities of the ontrol variable between. and.3, performane penalty an be restrited within %. For deeper pipeline (i.e. large N), the penalty may inrease. We suggest following tehniques for reduing the TBLE-3 SIMULTION RESULTS FOR 3-STGE PIPELINE V DDL (V) % Imp in power Overall % rea overhead Overall area # of yles reqd. Perf. penalty ht mu m5a imp (%) ht mu m5a penalty (%) [ht, mu, m5a] (%) [,,] [,,] [,,] [,,] 5.89 performane penalty, tune the ontrol variable seletion metri to pik low swithing inputs as ontrol variables; and, redue the ativation probability of ritial bloks further (i.e., by inreasing k as shown in Fig. ). 4.. Simulation results We performed eperiment on a 3-stage pipeline where eah stage is an MCNC benhmark iruit. The pipeline with the stage delays (for 95% yield with BPTM 7nm devies) is shown in Fig. 5. fter performing step- of the pipelinedesign(), delay target is hosen to be 85ps. We re-design the pipeline stages for V DDL s ranging from.75v to.9v. fter re-design, the entire pipeline is simulated in Hspie using random test patterns with uniform swithing ativity of.5. The results are shown (Table 3). It is interesting to note that the overall power saving inreases initially but delines at lower supply voltages. This is due to inreased swithing apaitane to meet the delay target at low supply voltage. The negative value of area overhead for ht is due to better optimization (Setion 3.4). It should also be noted that the ritial ofator of ht does not need two-yle operations for the given range of V DDL. This is due to the inreased delay target. Ciruit mu may need two-yle operations only when V DDL =.8V and.75v. However, iruit m5a may need two-yle operations for the entire voltage range. Therefore, the pipeline performane penalty varies between -%. Table-3 learly shows that it is benefiial to design the pipeline for V DDL =.85V where the power saving is signifiant (~%) with low performane penalty (~%). Similar tehnique ould also be etended for an N-stage pipeline. 5. CONCLUSION We have proposed a design paradigm based on ritial path isolation, whih ahieves low power operation while being robust with respet to parametri delay failures. The proposed design tehnique makes the possible delay errors preditable and rare under parametri variations. The ritial paths have been isolated to a known logi blok by Shannon partitioning and gate sizing. This leads to a robust iruit design whih allows us to redue the supply voltage aggressively while using the preditability to prevent ourrene of any delay violations. We have also demonstrated that this tehnique an be effetively applied to low power pipeline design. knowledgement: We thank GSRC MRCO for supporting this researh. We also thank Dr. Saibal Mukhopadhyay for valuable suggestions and disussions. REFERENCES []. Srivastava et al., Statistial optimization of leakage power onsidering proess variations using dual-v th and sizing, DC 4. [] S. Borkar et al., Design and reliability hallenges in nanometer tehnologies, DC, 4. [3] D. Ernst et al.., Razor: a low-power pipeline based on iruit-level timing speulation, MICRO, 3. [4] X. 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