Flexible Folded FIR Filter Architecture

Transcription

1 Flexible Folded FIR Filter Arhiteture I. Milentijevi, V. Ciri, O. Vojinovi Abstrat - Configurable folded bit-plane arhiteture for FIR filtering that allows programming of both number of taps and oeffiient length is proposed in this paper. Proposed arhiteture allows designing of flexible folded FIR filter arra with fixed size that enables effiient implementation of different wireless standards on single filter. This paper deals with the mapping of unfolded data flow graph onto the onfigurable folded sstem using a new folding set assignment. The obtained arhiteture as a folded sstem is desribed b data flow graph, funtional blo diagram and data flow diagram. I. INTRODUCTION Cellular-phone tehnolog is hanging rapidl. There is an inreasing number of wireless-ommuniations standards, inluding variants of the IEEE 8. wireless LAN speifiation, ode-division multiple aess, the global sstem for mobile ommuniations, and emerging third-generation tehnologies. Traditionall, devies need a separate hip to wor with eah standard. However, as wireless tehnologies mature, servie providers differentiate themselves b offering new features, suh as multimedia apabilities. Providing eah feature tpiall requires a separate hip, or essene, multiple iruitr sstems phsiall joined on a peae of silion []. The additional iruitr adds ost, taes up spae, inreases power usage in mobile devies, and inrease produtdesign time. This problem an be solved using adaptive approah. With this approah, software an redraw a hip s phsial iruitr on the fl, letting a single proessor to perform multiple funtions []. Fators suh as regularit, salabilit ande abilit to trade hardware for speed within the ontext of an arhiteture beome more important []-[4]. The appliation of folding tehnique onto arra tpe arhitetures for FIR filtering gives designers greater flexibilit in finding the best tradeoff between hardware size and throughput rate [5]. The folding transformation is used to sstematiall determine the ontrol iruits in DSP arhitetures where multiple algorithm operations are time multiplexed to a single funtional unit [6]. B exeuting multiple algorithm operations on a single funtional unit, the number of funtional units in the implementation is redued, resulting in integrated iruit with low silion area [7]. As a starting arhiteture for the snthesis of the folded bit-plane FIR filter arhiteture with hangeable folding sets, well-nown bit-plane arhiteture (BPA) [8] was used in [9]-[]. The BPA is highl regular arhiteture, whih I. Milentijevi, V. Ciri, O. Vojinovi are with the Department of Computer Siene, Fault of Eletroni Engineering, Universit of Nis, Beogradsa 4, 8 Nis, Serbia and Montenegro, {milentijevi,viri,oliver}@elfa.ni.a.u allows extensive pipelining, regular laout, high omputational throughput, trunation of Least Signifiant Bits (LSBs) of intermediate results without an loss of aura, and programmabilit of oeffiients. In this paper we propose flexible folded bit-plane arhiteture for FIR filtering that allows programming of both number of taps and oeffiient length. As a starting point we use the transformed Data Flow Graph (DFG) for the BPA proposed in [9] and involve new assignment of folding sets []. This paper deals with the mapping of the transformed DFG for the BPA onto the onfigurable folded sstem where new assignment of folding sets is implemented. The obtained arhiteture as a flexible folded sstem, will be desribed b DFG, funtional blo diagram and the data flow diagram. The method of operation and operations mapping onto the proessing units will be desribed in detail. The folded proessor arra is fed with data b hardware module for input data entering and oeffiient suppl module. The algorithms for data reordering in both modules will be presented, too. The folded FIR filter arhiteture is desribed in VHDL as a parameterized FIR filter ore. For the sae of the illustration of the arhiteture funtionalit and programming apabilities, few examples are implemented in FPGA tehnolog. The results of implementation, onerning throughput and hip oupation, will be presented. II. OPERATIONS MAPPING The following notation provides the basis for further explanation of mapping of DFG for BPA onto the onfigurable sstem: m oeffiient length, number of j oeffiients, i bit of oeffiient i (with weight j ), N folding fator, number of folding sets, n length of input words x i, L total number of operations in the DFG, where one operation assumes forming of partial produt and the addition performed on one row of basi ells (basi ell ontains AND gate and full adder), p-position of operation within the DFG ( p L-), S s s-th folding set ( s -). Starting DFG, whih is well prepared for appliation of folding tehnique is shown in Fig.. The mathematial desription of folding sets assignment (S s r) is done aording to the following equations s= p mod r= p mod N. () The idea of mapping different operations onto the different hardware units aording to the hosen number of oeffiients and oeffiient length in fixed arra struture is

2 introdued with (). The proposed mapping of operations enables both hanging the number of oeffiients and oeffiient length inluding onstraint L= m = N. The hardware size reduing for fator N is provided in a respet to the arhiteture from Fig.. Let us note that, the number of folding sets is not obligator equal to the number of oeffiients. In order to obtain mapping dependenies between operations and DFG nodes, transformed DFG from Fig. should be used. Eah operation from DFG (Fig. ) stands for multipliation of input data words b one oeffiient bit. Assignment of position numbers to operations in DFG (p) is done as follows: the leftmost operation is denoted with, while the rightmost operation is denoted with L- (Fig. ). Operation p ( p L-) from Fig. performs multipliation of input data word b oeffiient bit j i. Aording to (), folded arhiteture multiplies input data word (Fig. ) b oeffiient j i on folding set s ( s -) in time instane δ N+r ( r N-; δ=,,, ). The operation that has position in DFG equal to p (Fig. ), aording to folding set assignment (), an be desribed as p = m ( - ( j+ ) ) + i. () The dependen between folding set s and folding order r of oeffiient bit i with weight j, using () and (), is obtained as: ( m ( ( j+ ) ) + i) m ( ( j+ ) ) + i) s = mod r = ( mod N Expression () desribes the folding set s that performs j multipliation b oeffiient i in time instanes δ N+r ( r N-; δ=,,, ). III. FOLDED BIT-PLANE ARCHITECTURE Using a new assignment of folding sets that is applied on the transformed DFG from Fig., we obtain folded Bit- Plane arhiteture in general form (Fig. ). Input Data Entering Module (IDEM), denoted with dashed lines in Fig., provides input data for the folded arhiteture in aordane with folding set assignment (). Setions S,S,,S - in Fig. are Proessing Elements (PE) of the folded arhiteture. Eah setion is devoted to omputations from the orresponding folding set. Setions are implemented as rows of basi ells in funtional blo diagram, where the basi ell is omprised of AND gate and full adder. Funtional blo diagram for obtained () folded FIR filter arhiteture with hangeable number of oeffiients and oeffiient length is shown in Fig. for ase =, N=4, = and m =6. Let us note that the ordering of oeffiient depends on number of oeffiients,, and oeffiient length m. The Coeffiient Bit Suppl Module (CBSM) from Fig. provides the proper ordering of oeffiient bits regardless to oeffiient number and length. The internal struture of CBSM from Fig. is given in Fig. 4. In the respet to operations mapping (Eq. ), CBRM has two operational modes. First, initialization mode, when oeffiient bits are entered into the CBRM, and the seond, run mode, when CBRM is feeding arra with oeffiient bits. The CBSM is implemented as two-dimensional arra of lathes where eah lath stores one bit of the oeffiient (Fig. 4). The number of rows is equal to the number of folding sets in FBSM () while the number of olumns is equal to the FBSM s folding fator (N). Output from eah row is feeding one folding set of the folded arra with oeffiient bits. Rows are implemented as shift registers, so during the run mode oeffiients rotate through the rows from right to left, feeding eah folding set of folded arra with oeffiient bits in orret order (solid arrows in Fig. 4). Problem of providing the orret bit order, during initialization mode, an be solved using the propert of modulo dependene in (). Due, the trae of the first oeffiient bit an be desribed with mapping of time instanes t {,,, N} onto the arra position [α,β]: α=((t-) mod )+ β=(( t-) mod N)+. The number of lo les, required for initializing the struture, is N. IV. FUNCTIONAL DESCRIPTION Folding sets S,S,,S - are shown in dashed boxes (Fig. ). Eah folding set ontains N operations. In order to larif the folded FIR filter method of operation, the hardware setion that performs the operation from set S S (s=,,,-) is also denoted with S S. Initiall, the omputation starts in folding set S where the produt - x is obtained in the first lo le. In the next lo le folding set S generates the partial produt - x adding previousl omputed partial produt from S. Thus, the value ( - x )+( - x ) is m m+ m+ m (-)m+ (-)m+ m Fig.. Transformed DFG

3 entered into the next setion, whih performs the operations from S, in the third lo le. The next important time instane is (+)st lo le. In that lo le both input data path and summation path are folded from setion S - to S. In input data path x is present at input of the setion S, while in the summation path ( - x )+( - x )+...+( x ) enters the same setion. S adds - x to the entered sum. But the omputation for the oeffiient - is not finished et. The omplete produt -x is obtained in the setion S (m -) mod during lo le m. The omputation of -x starts in (m +)st lo le. The setion Sm mod omputes {( - x )+( - x )+...+( m - - m - x )}+ + - x = = ( -x )+( m - - x ). The first ompletel generated result at output is with laten m -N lo les. New result is generated ever N lo les. The data flow example that illustrates desribed proess of omputation is shown in Fig. 5. The proposed arhiteture supports the operation with hangeable number of oeffiients and oeffiient length. V. IMPLEMENTATION The implementation is done onto the FPGA Spartan II s-5pq8 with aim to illustrate what filtering an be arried out onto the one folded programmable arhiteture. The Table I illustrates the abilities of one implemented arhiteture with n=8, =8, N max =6 and =7 ( stands for implemented length of output word). Table I gives the implementation results for lo period, throughput and initial laten for possible programmed values of and m taing into aount hosen folding fator N (N max N ). Using the data from Table I, the graphial representation in Fig. 6 that desribes the throughput as a funtion of hosen folding fator, is generated. Inreasing of throughput is ahieved b dereasing of folding fator. Table I also ontains values for initial laten as it is given b m -N+Adder Laten. The initial laten depends also on adder s laten. In the implemented example adder s pipeline stages is equal to adder s length (=7). The number of adder s pipeline stages remains the same regardless to the programmed values for and m. TABLE I POSSIBILITIES FOR CONFIGURATION OF THE ARRAY N m Used Clo Throughput Initial laten slies [MHz] [l] [MHz] [l] [ns] [5%] [5%] [5%] [5%] [5%] [5%] VI. DISCUSSION AND CONCLUSIONS The transformation of soure DFG for the bit-plane arhiteture and proposed assignment of folding sets enable the snthesis of full pipelined folded FIR filter arhiteture with hangeable number of oeffiients, hangeable oeffiient length, and adjustable folding fator. The derived arhiteture has ept desirable features of soure arhiteture suh as extensive pipelining, high regularit, trunation of LSBs of intermediate results without an loss of aura. FPGA implementation of proposed arhiteture proved the funtionalit of the arhiteture and showed liner dependen of throughput as a funtion of folding fator in fixed size arras. tradeoffs between throughput and oupation of on-hip resoures as well as to illustrate onfiguration apabilities of the folded arhiteture. Proposed arhiteture allows designing of flexible folded FIR filter arra with fixed size that enables effiient implementation of different wireless standards on single filter. REFERENCES x {t=n l+} {t=i* m } {t /= N l+} {t /= i* m } l=,,,... i=,,,... S S S- N - {} - {} - {} {} - {} {} IDEM m - {N-} {N-} {N-} {N-} {,,,...,N-} Fig.. Folded FIR filter arhiteture with hangeable number of oeffiients and oeffiient length

4 [] L. Paulson, L. Garber, Reonfiguring Wireless Phones with Adaptive Chips, IEEE Computer, Vol. 6, Number 9, September, pp. 9-. [] P. Corsonello, S. Perri, and G. Coorullo, "Area-Time-Power Tradeoff in Cellular Arras VLSI Implementations", IEEE Transation on Ver Large Sale Integration (VLSI) Sstems, Vol. 8, No. 5, Ot., pp [] R. Lin, "Reonfigurable Parallel Inner Produt Proessor Arhitetures", IEEE Transations on Ver Large Sale Integration (VLSI) Sstems, Vol.9, No., Apr., pp. 6-7 [4] Robert Hawle, Bennett Wong, Thu-ji Lin, Joe Lasowsi, Henr Samueli, Design Tehniques for Silion Compiler Implementations of High-Speed FIR Digital Filters, IEEE Journal of Solid-State Ciruits, Vol, No. 5, Ma 996. [5] Y-C. Lin, F-C. Lin, "Classes of Sstoli Arras for Digital Filtering", Int. J. Eletronis, Vol.7, No.4,99,pp [6] K.K. Parhi, VLSI Digital Signal Proessing Sstems (Design and Implementation), John Wile & Sons, In., New Yor,. [7] T. C. Den, K. K. Parhi, Snthesis of Folded Pipelined Arhitetures for Multirate DSP Algorithms, IEEE Transation on Ver Large Sale Integration (VLSI) Sstems, Vol.6, No. 4, De. 998, pp [8] D. Reuver, H. Klar, "A Configurable Convolution Chip with Programmable Coeffiients", IEEE Journal of Solid State Ciruits, Vol. 7, No. 7, Jul 99, pp. -. [9] I. Milentijevi, V. Ciri, O. Vojinovi, T. Toi, Folded Semi-Sstoli FIR Filter Arhiteture With Changeable Folding Fator, Neural, Parallel & Sientifi Computations, Dnami Publishers, Atlanta, Vol., No,, pp [] I. Milentijevi, V. Ciri, Assignment of Folding Sets for Adaptive FIR Filtering on Folded Arra, Proeedings of the WPS-DSD, 9th EUROMICRO Conferene, Bele, 4 x x x x x parallel in Adder 9 5 l m =6 N=4 CBSM a x b s a x b s Fig.. Funtional blo diagram Fig. 5. Data flow for folded arhiteture (=, N=4, = and m =6) Throughput [ns] [,4] [,] [,] [,] [,4] [,] [,] [,] 8 6 [,4] [,] [,] [,] 4 serial in Fig. 4. Coeffiient Bit Suppl Module CBSM Fig. 6. Throughput as a funtion of hosen folding N

5 Ture, September. pp. -.