Efficient FIR Filter Architectures Suitable for FPGA Implementation

Transcription

1 Effiient FIR Filter Arhiteture Suitable for FPGA Implementation Joeph B. Evan Teleommuniation & Information Siene Laboratory epartment of Eletrial & Computer Engineering Univerity of Kana Lawrene, KS Abtrat Thi paper deribe effiient arhiteture for FIR filter. By eploiting the redued ompleity made poible by the ue of two power-of-two oeffiient, thee arhiteture allow the implementation of high ampling rate filter of ignifiant length on a ingle field-programmable gate array (FPGA). The author an be ontated via at evan@til.ukan.edu. Portion of thi work will be preented at ISCAS 9 in Chiago, Illinoi. Thi reearh i upported by the Univerity of Kana General Reearh alloation

2 Introdution Coniderable attention ha been plaed on the implementation of ignal proeing algorithm in VLSI, ranging from full utom VLSI to general purpoe digital ignal proeor. A variety of approahe to utom implementation of FIR filter have been purued [,,, 4, 5, 7, 8, 9]. In order to attain high performane, parallel implementation trategie uh a ytoli method have been applied. Word-parallel, bit-parallel proeing tehnique appear to ale well with improvement in implementation tehnology and inreaing demand for higher performane. Advane in field programmable gate array (FPGA) tehnology have enabled FPGA to be ued in a variety of appliation. In partiular, FPGA prove partiularly ueful in datapath deign, where the regular truture of the array an be utilized effetively. The programmability of FPGA add fleibility not available in utom approahe, while retaining relatively high ytem lok rate. The diadvantage of FPGA are primarily related to the limited number of logi operation that an be implemented on a partiular devie, the ontraint on the input and output to the atomi logi unit, and the limited ignal routing option that are available for onneting logial operator on the array. Many urrent FPGA arhiteture are implemented uing memory tehnologie, and hene the advane in that area will be refleted in improved FPGA denity and peed. Thi paper preent new parallel FIR filter building blok uited for implementing filter where eah of the oeffiient value i a um or differene of two power-of-two term. Thee arhiteture allow high ampling rate FIR filter of ubtantial length to be implemented on urrent generation FPGA. In binary arithmeti, multipliation by a power-of-two i imply a hift operation. Implementation of ytem with multipliation may be implified by uing only a limited number of power-of-two term, o that only a mall number of hift and add operation are required. Thee implifiation are, however, ahieved at the epene of a deterioration in the frequeny repone harateriti, the etent of whih depend on the number of powerof-two term ued in approimating eah oeffiient value, the arhiteture of the filter, and the optimization tehnique ued to derive the direte pae oeffiient value. It wa demontrated in [6] that an FIR filter with -6dB of frequeny repone ripple magnitude an be realized uing two power-of-two term for eah oeffiient value, given that the filter i in aade form and the oeffiient value are derived uing mied integer linear programming. If the oeffiient value i an integer power-of-two, or a um of two power-of-two, the multiplier in a filter

3 tap an be replaed by hifter, a depited in Figure. Sine the oeffiient will be fied for thi la of filter, the oeffiient value an be realized by appropriately routing the input to the full adder in the filter truture. That i, moving the adder input k plae to the left ahieve the ame effet a would a oeffiient value of k. Arhiteture The ignal flow graph (SFG) of the FIR filter arhiteture diued in thi work are illutrated in Figure. The SFG hown in Figure (a) an be applied to FPGA arhiteture ine the ue of global ommuniation an be tolerated in uh ytem, although more pipelining an be ued if needed. An SFG appropriate for linear phae filter i hown in Figure (b). In order to attain high ampling rate uing onventional FPGA, bit-level parallelim i eploited. The overall filter arhiteture i hown in Figure, where the filter tap and final adder tage are hown. The adder i required to reolve the arrie that are generated and propagated through the pipeline. The truture of the filter tap of Figure (a) i hown in Figure 4. The two adder, whih are neeary for oeffiient that are a um of two igned power-of-two, are implemented a two row of full adder, whoe input are onfigured with the appropriate hift for the given oeffiient. The ign of the oeffiient i ontrolled by inverter. The um and arry ignal from the full adder are pipelined uing a arry-ave addition (CSA) tehnique in order to inreae the ampling rate and alleviate potential routing delay in the target implementation tehnology. The input data bu pae through the bit-lie array to provide hort interonnetion ditane to the firt row of full adder. Thi bu may be optionally pipelined depending on the partiular FPGA implementation tehnology, among other fator. The bit of the input are hifted before ummation, a repreented by the dotted line. The linear phae filter tap of Figure (b) i depited in Figure 4. Thi arhiteture i imilar to the previou ae, with the addition of the upper et of adder and regiter whih implement the delay and um operation on the input data tream. In thi ae, the delayed and global data bit are ummed prior to hifting, a repreented by the dotted line, due to logi unit input/output retrition. While the ripple arry truture doe limit performane, mot reent FPGA arhiteture upport high peed arry logi whih minimize the problem.

4 FPGA Implementation An FIR filter tap a hown in Figure 4 an be implemented in two array olumn of Xilin XC-erie FPGA. Beaue of the high degree of patial and temporal loality, mot ignal routing delay are not ritial, a they are with typial high performane FPGA deign. Eah of the bit lie for the tap require two ombinational logi blok (CLB) in the array for implementation. The etenive loal routing apability of typial FPGA an be ued for the majority of ignal within and between tap. Figure 6 illutrate the loal routing required between CLB, where olumn "" map to the firt et of full adder for a given tap, and olumn "" map to the eond et. The globally routed input data ignal are ditributed uing the horizontal and vertial net running the length and width of the hip between the row and olumn of CLB. The primary onern i with routing of the hift line. In mot realization, the aumulation path will have a wider word width than the input data from the hifter, in order to aount for overflow and round-off problem. For eample, if the input data i B d bit wide, the aumulation path will mot likely be B i ç B d bit wide. Thi implie that the input datapath will ue fewer routing line in eah FPGA olumn than will the aumulation path. By eploiting thee etra, unalloated reoure, the low delay vertial routing line of the FPGA an be ued more effetively. The etra reoure allow the number of vertial routing line to be minimized, a illutrated in Figure 4, where the additional datapath lead to lower ongetion in the routing hannel between the olumn. A tap with B d input datapath bit and B i aumulation path bit an thu be implemented uing B i logi blok. The final adder required by the filter an be implemented on the FPGA or uing an additional hip. Typial filter harateriti have been implemented on an Xilin XC95 FPGA uing thi arhiteture. The XC95 ha an array of by (484) CLB. For eample, an eleven tap lowpa FIR filter with the paband ut-off at :f, the topband beginning :5f, and -8dB topband rejetion wa deigned. An input data word ize of bit wa ued; the row provide uffiient intermediate word width protetion againt overflow. All of the olumn of the array were required for the eleven tap. The final aumulation tage wa not performed on the array. The maimum ampling rate for thi partiular deign wa MHz. The delay i highly dependent on the input data routing, and o higher ampling rate may be attainable for other filter repone (with areful routing). Linear phae FIR filter tap an be implemented in three array olumn of Xilin XC4-erie FPGA, a depited in Figure 5. Beaue the XC4 erie upport dediated arry logi, the ripple arry hain an be

5 ued to implement the adder for the input and delayed data. A 9-tap linear phae filter an be upported on an XC4 omponent, whih ha 9 CLB. Baed on the Xilin timing analyzer, ampling rate on the order of 5- MHz an be obtained. 4 Conluion A new parallel FIR digital filter truture whih allow effiient FPGA implementation of filter whoe oeffiient value are um or differene of power-of-two term wa preented. igital FIR filter with over one hundred tap baed on thi arhiteture hould be poible by the end of the deade if urrent tehnologial trend ontinue. Eample baed on Xilin XC and XC4 FPGA were given, although other programmable logi devie uh a the AT&T ORCA omponent will alo upport thi arhiteture. Automati programming, from filter peifiation to FPGA program, i traightforward. Referene []. E. Borth, I. A. Geron, J. R. Haug, and C.. Thompon. A fleible adaptive FIR filter VLSI IC. IEEE Journ. Selet. Area Commun., SAC-6():494 5, Apr 988. [] J. B. Evan, Y. C. Lim, and B. Liu. A high peed programmable digital FIR filter. In IEEE Int. Conf. Aout., Speeh, Signal Proeing, Apr 99. [] J. Gallia et al. High-performane BiCMOS k-gate array. IEEE J. Solid State Ciruit, SC-5():4 49, Feb 99. [4] M. Hatamian and S. Rao. A MHz 4-tap programmable FIR filter hip. In IEEE Int. Symp. Ciruit and Syt., page 5 56, May 99. [5] R. Jain, P. Yang, and T. Yohino. Firgen: A omputer-aided deign ytem for high performane FIR filter integrated iruit. IEEE Tran. Signal Proeing, 9(7): , Jul 99. [6] Y. C. Lim and B. Liu. eign of aade form FIR filter with direte valued oeffiient. IEEE Tran. Aout., Speeh, Signal Proeing, ASSP-6:75 79, Nov 988. [7] S. Powell and P. Chau. Redued ompleity programmable FIR filter. In IEEE Int. Symp. Ciruit and Syt., page , May 99. [8] P. Yang, T. Yohino, R. Jain, and W. Ga. A funtional ilion ompiler for high peed FIR digital filter. In IEEE Int. Conf. Aout., Speeh, Signal Proeing, page 9, Apr 99. [9] T. Yohino,, R. Jain, et al. A -MHz 64-tapFIRdigital filterin.8 çm BiCMOS gate array. IEEE J. Solid State Ciruit, 5(6):494 5, e 99. 4

6 +/- j +/- k Figure : FIR Filter Tap Arithmeti Unit, Coeffiient with Two Power-of-Two k w N- w N- w N- w y k (a) k w N- w N- w N-5 w w y k (b) Figure : FIR Filter Arhiteture, (a) inverted form, (b) linear phae. filter filter filter input adder B B B B B B tap tap tap output Figure : FIR Filter Arhiteture 5

7 Figure 4: FPGA Filter Tap Struture, with Shifter Routing 7 7 d 6 6 d 5 5 d 4 4 d d d 7 7 d 6 6 d 5 5 d 4 4 d d d Figure 5: FPGA Linear Phae Filter Tap Struture Figure 6: FPGA Filter Tap Loal Interonnetion 6