Implementing a Real-Time Beamformer on an FPGA Platform We designed a flexible QRD-based beamforming engine using Xilinx System Generator.

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1 Implementing a Real-Time Beamformer on an FPGA Platform We deigned a fleible QRD-baed beamforming engine uing Xilin Sytem Generator. by Chri Dik Xilin Chief DSP Arhitet Company: Xilin hri.dik@ilin.om Fred Harri Profeor San Diego State Univerity fred.harri@du.edu Mirolav Paji Engineer Signum Conept mirolav.paji@ignumonept.om Dragan Vuleti Engineer Signum Conept dragan.vuleti@ignumonept.om Mot real-world ommuniation ytem have a mi of proeing element. For eample, appliation program, human/mahine interfae management, and higher networking protool tak proeing are bet implemented on a general-purpoe proeor. But for high-rate, algorithmially omple data proeing often with hard realtime deadline hardware reoure like FPGA are a better math. The interfae between the two depend on the irumtane; the FPGA an be a pre-proeor, oproeor, pot-proeor, or ome ombination thereof. The trik i to get thee heterogeneou ytem to interoperate in an elegant fahion.

2 In thi artile, we ll deribe the development of a fleible, optimized, adaptive beamforming engine that you an eaily ontrol through oftware. The DSP-intenive tak run on the FPGA, while the ommand and ontrol run on an eternal proeor. The beamforming engine i a ompat QR deompoition (QRD-baed iruit) with a novel ontrution. The interfae between the engine and the hot proeor i implemented by the hared memory abtration in the Xilin Sytem Generator deign flow. Diretion of Arrival Array Element (n) 1 (n) 2 (n) M-1 (n) w (n) w 1 (n) w 2 (n) w M-1 (n) Σ (t,θ) MVDR Beamformer Adaptive beamforming i the appliation of adaptive filter to patial ignal proeing. Time erie olleted from uniformly paed array element are weighted and ummed to form a ignal omponent from a eleted diretion of arrival while uppreing ignal omponent from other diretion of arrival (Figure 1). When the diretion of arrival of the undeired ignal omponent are unknown or vary with time, the filter weight mut be adaptively adjuted to teer null to their diretion. The adaptation proe i performed ubjet to a ontraint that the teering vetor ha unity gain in the ignal diretion. The teady tate weight of uh a beamformer form the minimum variane ditortionle repone (MVDR) from the array element. For reaon of numerial robutne and omputational ompleity, a ommon method for omputing the required weight vetor without diretly inverting the orrelation matri i baed on QR deompoition; thi i the approah adopted here. For detail of the proedure, onult Adaptive Filter Theory by Simon Haykin. The QRD Matri Inverion Proe The QRD proe i formed by a equene of two operator: the unitary rotation that onvert ompleput data to real data and aoiated angle-and-element ombiner that individually annihilate the eleted element of the input data et. The QRD proe i mot ompatly repreented in Figure 2 ignal flow diagram. Thi repreentation i the ytoli array realization of the QRD leat-quare olution proeor. Steering Vetor (2) (1) () Triangular Array Triangular Array Proeing Node Definition out (1) () Adaptive Algorithm () d(2) d(1) d(),,1,2,3 1,1 if = then 1 λ 1/2 Otherwie ' λ 1/2 ' ' ' 1,2 λ out - λ 1/2 + λ 1/2 Figure 1 Adaptive beamformer truture 1,3 2,2 2,3 ii w^ i w ^ i = (i) p i ii 1 2 (i) p i ^w k Linear Array Linear Array Proeing Node Definition (k-1) (k) w^ k (k-1) (k) z = z ^ i i + * ik w k Figure 2 Sytoli array implementation of QRD matriverion for a 3 3 array Firt Quarter 27 Xell Journal

3 The array ontain three type of proeing ell: boundary ell, internal ell, and output ell. The boundary ell perform the vetoring operation on omple input ample to nullify their imaginary part and form rotation angle ued by internal ell. The internal ell perform Given rotation of the input value by the angle paed from the boundary ell to annihilate the non-upper-triangular entrie of the tranformed data matri. The output ell in the linear array proe the element of the upper triangular array to perform the required bak ubtitution that produe the beamformer weight. FPGA Implementation of QRD Our goal wa to produe a ompat QRD FPGA implementation. The deign omprie a ingle boundary, internal and bak ubtitution ell. The ytoli array in Figure 2 i folded onto thi et of proeing reoure. The boundary ell i required to ompute two angle. The firt angle Φ = artan(i( )/R( )) One well-known and relatively imple method for omputing angle i the vetoring mode of the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm i an iterative proedure apable of omputing a rih et of mathematial funtion. The elemental operation required in the CORDIC algorithm are addition, ubtration, bit-hift, and table lookup. All of thee funtion are effiiently upported by FPGA arhiteture uh a the Virte erie of devie from Xilin, o the vetoring mode of the algorithm i a good andidate for the foundation of QRD proeor boundary ell. A hown in Figure 3, two CORDIC engine are in ue in the boundary ell: one for omputing φ and the other for omputing θ. The CORDIC algorithm i iterative in nature, with eah iteration refining the angle etimate by approimately 1 bit of preiion. For a proe employing an N- iteration CORDIC proe, a new output i generated every N lok yle and a new et of operand preented every N lok yle. To inreae the throughput of the boundary ell, we employed a fully parallel, or unrolled, arhiteture for the CORDIC (not hown here). After the initial tart-up lateny of the iruit i aborbed, the initi- ( ) tranform the ompleput ample preented to the boundary ell input port into real-valued data. The tranformation that fore the imaginary omponent of in to mut be applied to all element in the ame row aoiated with the boundary ell; thi operation i one of the tak performed by the internal ell. Now that the data in the leading poition of two adjaent row are real-valued, a eond angle i formed a Figure 3 Boundary ell arhiteture baed on two vetor-mode CORDIC proeing engine Θ = artan( e -jφ /) whih i ued to annihilate a term of the input data et in an ordered manner that eventually produe the upper-right triangular matri R. The arithmeti employed in the boundary ell ould be realized in hardware by literally implementing the equation indiated in Figure 2. Thi would require hardware upport for performing quare root and diviion. Although thee iruit are ommonly implemented in FPGA hardware, we ought alternative method for omputing the required angle that had a lower reoure ot over diret and obviou implementation. Figure 4 Sytoli array internal ell arhiteture employing three MAC-baed Given rotation engine

4 ation and ompletion rate of the ell i one new input/output per lok yle. Eah data element entering an internal ell (Figure 4) in row m mut be rotated by the angle φ omputed by the boundary ell for the m th row: R I One option that ha been ommonly ued for the rotation tak in QRD proeor i the rotation mode of the CORDIC algorithm. An alternative i to imply implement the rotation in the obviou manner uing multiply aumulate (MAC) funtional unit; thi i the approah adopted in our implementation. The target FPGA tehnology for the deign i the Virte-4 FPGA. Thee devie have a vat array of embedded MAC unit referred to a DSP48 lie. The DSP48 lie upport a rih et of opode apable of being updated on a per-lok-yle bai that define the arithmeti operation omputed by the tile during a given lok yle. The four multipliation implied in the preeding equation are folded onto a pair of DSP48 lie, with eah DSP48 lie omputing one of the two output term R(υ) and I(υ). Two lok yle are required to ompute the two output term. Eah DSP i upplied with a unique opode for eah lok period. Conider omputing the term R(υ). During the firt lok period, the produt o(φ) R( ) i omputed and tored in the DSP48 produt or p regiter. During the eond lok yle in(φ) I( ) i formed and ubtrated from the Funtional Unit LUT FF DSP48 Slie Blok RAM Slie Boundary Cell 2,145 2, ,266 Inner Cell Bak Subtitution 2,862 3, ,932 QRD Total 5,411 5, ,53 M () () υ υ N o = o () φ in() () φ in() θ θ R I ( in) ( ) in Table 1 FPGA reoure utilization for folded QRD and bak ubtitution array Cyle for Cyle for Time (μ) for Total Cyle Triangularization Bak Subtitution 25-MHz Clok , , , , , , , , , , , , , , , , Table 2 Eeution time for the triangularization and bak ubtitution phae of the FPGA QRD implementation for an M N matri. value in the p regiter to generate the final output term. A imilar equene of omputation i performed to produe I(υ). Uing the DSP48 embedded blok rather than a CORDIC-baed approah for the internal ell redue the lateny of thi phae of the omputation and alo minimize the amount of FPGA logi fabri (look-up table [LUT] and regiter) required for the implementation. Table 1 provide a breakdown of the area for the major funtional unit in the QRD implementation, along with the total area of the deign. The o(φ), in(φ), o(θ), and in(θ) term required by the internal ell are omputed uing a imple LUT that map the angle Φ and Θ omputed by the vetoring unit in the boundary ell to their orreponding ine and oine. Linear interpolation i applied to the output ample of the LUT to inreae the auray of the mapping from angle to amplitude, while keeping the LUT itelf ontrained to a ingle blok RAM. The row and olumn dimenion of the input array for the QRD proeor an be dynamially adjuted at runtime by writing the new dimenion to ontrol regiter that are part of the FPGA ontrol plane. Table 2 provide timing information for everal onfiguration of the input data et. Deign Flow Our QRD implementation ue the Xilin Sytem Generator for DSP modelbaed deign flow. In addition to providing a natural development environment for developing FPGA ignal-proeing implementation, Sytem Generator ha a rih et of feature that upport the development of heterogeneou appliation ompriing not jut the FPGA element but a proeor. The proeor ould be the embedded PowerPC 45 hard IP blok, the MiroBlaze oft-proeor ore, or a proeor eternal to the FPGA. The beamformer developed for thi projet wa partitioned between the hot PC and the FPGA platform. In our implementation the hot appliation running on the PC might be onidered more of an element of the beamformer verifiation proe (tet benh), but the hot applia- Firt Quarter 27 Xell Journal

5 tion ould be a arbitrary and omple a required by the tak at hand. Our beamformer hot appliation i a MATLAB ript (m-ode) that imulate the enor array for the beamforming network. The ript imulate a dynami target and generate the ample of the far-field radiation pattern for the moving target. The ample of the eletri field at eah enor are generated in MATLAB and forwarded to the FPGA QRD proeor. A new etimate of the beamformer weight vetor i produed and returned to the MATLAB environment for further proeing. In thi ae, the additional proeing involve plotting the polar radiation pattern for the updated omple valued weight vetor. Note that the hot appliation doe not neearily have to be aoiated with the MATLAB environment; the appliation ould be a program written in C, for eample. An intereting element of the beamformer appliation i the management of the interfae between the hot appliation, running on a PC in thi ae, and the QRD proe eeuting on the FPGA platform. Sytem Generator provide a uite of hared memory library objet (ROM, RAM, FIFO) that abtrat virtually all of the detail of the proeor/fpga interfae Sytem Generator deign flow inulate the hot program from the detail of the FPGA platform Input Buffer 'foo' FPGA Matlab or C Appliation Matlab or C API Proeing Kernel Shared Objet and enable the hot oftware and FPGA hardware to be omewhat inulated from eah other (Figure 5). Eah new update of the beamformer i eentially a three-tep proedure: 1. New input ample from eah antenna element, a generated by the MATLAB hot appliation, are forwarded to the QRD engine in itu on the FPGA. 2. The QRD proe i triggered. 3. The new weight vetor i returned from the FPGA to the hot. The hared memory library module and aoiated appliation programmer interfae tranform the tranfer of data between the FPGA and the hot PC into imple aignment tatement baed on name/pae referene in MATLAB (or C). For eample, the new weight vetor w, reident in the MATLAB workpae, i updated with the new beamformer oeffiient, FPGAWeight, a omputed by the FPGA QRD proe uing the imple aignment w = FPGAWeight. (FPGAWeight i the name aigned to a hared-memory buffer in the Sytem Generator deription of the QRD engine.) The management of thi type of hot proeor/fpga interation by the Sytem Output Buffer 'bar' API i autogenerated by Sytem Generator Figure 5 Hardware/oftware abtration enabled by the Sytem Generator hared memory library element. The hot appliation perform tranation with the FPGA torage element uing imple name/pae referene in thi ae to the memorie named foo and bar. Generator framework make the development of heterogeneou appliation traightforward, rapid, le error-prone, and enable an FPGA aelerator engine (like the QRD module in thi ae) to be eaily ported between different hardware platform without needing to modify the FPGA oure ode the Sytem Generator model itelf. The interfae abtration upport tranation between the hot appliation and the Sytem Generator oure model, a well a the hot appliation and the final deign running on the FPGA platform. Thi latter element ignifiantly ontribute to the validation proe of the oftware and hardware (FPGA) dimenion of the ytem, a both omponent an be brought online rapidly uing the hared memory abtration. Conluion In thi artile, we ve deribed the FPGA implementation of a fleible QRD proeor that enable the run-time definition of the input matri dimenion. The deign employ a miture of CORDIC-baed proeing (array boundary ell) and MACbaed (array internal ell) arithmeti that i well mathed to the omputational reoure of an FPGA like the Xilin Virte-4 family. All of the boundary- and internal-ell proeing were projeted onto a ingle boundary ell funtional unit and internal ell funtional unit; however, it hould be noted that the abundant reoure of FPGA platform upport the realization of a fully parallel ytoli array, hould the throughput requirement of the target appliation demand etremely high performane. The Sytem Generator programming environment enable the rapid development of heterogeneou ytem (proeor and FPGA) while inulating programmer from the frequently omple and errorprone programming aoiated with hardware/oftware partition. Thi work wa performed by the Xilin Advaned Sytem Tehnology Group (ASTG), the R&D organization within the Xilin DSP Diviion, together with our partner organization Signum Conept and San Diego State Univerity.