Enhancing System-Wide Power Integrity in 3D ICs with Power Gating

Transcription

1 Enhaning System-Wide Power Integrity in 3D ICs with Power Gating Hailang Wang and Emre Salman Department of Eletrial and Computer Engineering, Stony Brook University, Stony Brook, NY 794 USA {hailang.wang, Abstrat Power gating is a ommonly used method to redue subthreshold leakage urrent in nanosale tehnologies. In through silion via (TSV) based threedimensional (3D) integrated iruits (ICs), power gating an signifiantly degrade system-wide power integrity sine the deoupling apaitane assoiated with the power gated blok/plane beomes ineffetive for neighboring ative planes, as demonstrated in this paper. A reonfigurable deoupling apaitor topology is investigated to alleviate this issue by exploiting the ability of via-last TSVs to bypass plane-level power networks when delivering the supply voltage. deoupling apaitors plaed within a plane an provide harge to neighboring planes even when the plane is power gated, thereby signifiantly reduing both RMS power supply noise (by up to 46%) and RMS power gating (in-rush urrent) noise (by up to 85%) at the expense of a slight inrease in area (by.55%) and peak power onsumption (by.36%). Keywords Power delivery, 3D IC, power gating Plane Plane 2 Plane 3 Virtual VDD grid Global VDD grid Via-last TSV Fig.. Coneptual representation of a power distribution network for a three-plane 3D IC with via-last TSVs. Power gating is illustrated with global and virtual power grids and sleep transistors (). I. Introdution Through silion via (TSV) based three-dimensional (3D) integrated iruits have emerged as a promising tehnology for both high performane and low power integrated iruits (ICs) []. 3D ICs alleviate the adverse effets of global interonnets, thereby enabling higher performane at lower power onsumption while potentially lowering ost [, 2]. A signifiant hallenge in vertial 3D integration is the design of a reliable power distribution network. Existing researh efforts have investigated TSV types, plaement, optimization, and power grid arhitetures [3 5]. Deoupling apaitors in 3D ICs have also been onsidered [6,7]. However, the effet of power gating on the power integrity of 3D ICs has not reeived muh attention. Power gating effetively redues subthreshold leakage urrent by turning off the power delivery path of a iruit module when the module is not ative [8]. For 3D systems, due to the harateristis of heterogeneous integration and high parallelism, the amount of nonswithing iruits an be signifiantly high. Thus, 3D ICs are expeted to be heavily power gated to suffiiently redue leakage power. In [9], Todri et al. have investigated the effet of planelevel power gating on power integrity in 3D ICs. It has been demonstrated that the deoupling apaitane plaed This researh is supported in part by the National Siene Foundation CAREER grant under No. CCF and the Offie of the Vie President for Researh at Stony Brook University. within a plane is highly effetive in reduing the power supply noise of neighboring planes. The interdependene between deoupling apaitane and power gating, however, has not been onsidered. In traditional deoupling apaitor topologies, the deoupling apaitane within a iruit blok is onneted to the loal power grid (loser to the swithing iruits) to effetively redue supply noise [0, ]. However, if the blok (or an entire plane) is power gated, those apaitors are disonneted from the global power network and therefore annot provide harge to the neighboring, potentially ative bloks or planes. In [2], Tong et al. have proposed reroutable deoupling apaitors in 2D ICs. The primary objetive has been to relax the tight tradeoff between power gating noise and leakage power by onneting the deoupling apaitors to the global power grid when a blok is power gated. Thus, these deoupling apaitors remain harged, signifiantly reduing the power gating noise at the expense of apaitor leakage urrent. However, in [2], the ability of reroutable apaitors in reduing the power supply noise of neighboring bloks has not been explored. This ability is failitated partiularly in 3D ICs due to shorter global interonnets. In this paper, reonfigurable apaitors are proposed to alleviate power supply noise of the neighboring ative planes in 3D ICs. Two harateristis of via-last TSVs are exploited to inrease the effetive range of a de /5/$ IEEE 322 6th Int'l Symposium on Quality Eletroni Design

2 oupling apaitane: () low resistivity and (2) ability to bypass plane-level power network when delivering the power supply voltage. The rest of the paper is organized as follows. The reonfigurable deoupling apaitor plaement topology for 3D ICs with power gating is introdued in Setion II. Simulation results are presented in Setion III. Finally, the paper is onluded in Setion IV. Transistors Swith Swith 2 Ciruit Bloks Vdd Virtual Vdd II. Deoupling apaitors in 3D ICs with Power Gating Typial methods of implementing power gating in 3D ICs are introdued in Setion II-A. The reonfigurable deoupling apaitor topology is presented in Setion II-B. A. Bakground Similar to 2D planar tehnologies, sleep transistors with high threshold voltage are utilized to ahieve power gating in 3D ICs. Depending upon the type of TSVs (viafirst/middle or via-last), distributed or lumped power gating topologies have been proposed [3]. In the distributed topology (shown to be more appropriate for via-last TSVs), sleep transistors are distributed throughout the entire 3D stak whereas in lumped topology (shown to be more appropriate for via-first/middle TSVs), all of the sleep transistors are loated at the topmost plane [3]. An example of a via-last TSV based 3D power network with distributed power gating topology is illustrated in Fig.. Note that via-last TSVs pass through the metal layers and onnet the topmost metal layer on eah plane. Also, note that in via-last TSV tehnology, the TSV resistane is signifiantly smaller as ompared to via-first/middle tehnologies. These two harateristis of via-last TSVs failitate the utilization of a deoupling apaitor within a plane to redue the power supply noise of the neighboring planes (due to greater effetive range). B. Reonfiguration of the Deoupling Capaitors Sine system-wide power integrity is a ritial hallenge, effetive utilization of intentional deoupling apaitane is ruial, even when power gating is adopted. This issue is exaerbated in 3D ICs due to the power grid impedanes of the multiple planes and higher integration levels. In 2D ICs, it is relatively more diffiult to utilize the apaitane within a power gated domain for the remaining, ative regions due to longer global interonnets. In 3D ICs, however, due to redued interonnet length and relatively low resistane of via-last TSVs, deoupling apaitane within a power gated plane an still be effetive for the neighboring ative planes. Aording to [9], the effetive range of a deoupling apaitor exeeds single plane in 3D ICs with via-last TSVs, as also observed in this work. Thus, reonfigurable deoupling apaitor topology is an effetive method to enhane power integrity in 3D ICs with power gating. In the reonfigurable topology, two swithes are introdued, as oneptually illustrated in Fig. 2. If a ertain Fig. 2. Coneptual representation of the reonfigurable deoupling apaitor topology with power gating. Loal Z Swith 2 Swith 2 Ciruit Blok Global Vdd Transistor Virtual Vdd Fig. 3. Illustration of the additional resistive path between the global and virtual power networks formed by the reonfigurable swithes. plane is ative, the deoupling apaitors on that plane are onneted to the virtual V DD grid through swith 2, thereby reduing the power supply noise on that plane. Alternatively, if the plane is power gated (sleep transistors are turned off), the deoupling apaitors are onneted to the global V DD grid, bypassing the sleep transistors. Thus, even if the plane is power gated, the deoupling apaitors remain effetive for the ative planes. The overhead of this topology inludes the reonfigurable swithes, metal resoures to route the ontrol signals, and higher leakage urrent if the apaitors are implemented as MOS apaitors, as quantified in this work. Similar to sleep transistors [4], high-v th MOS swithes are used to minimize the voltage at the virtual V DD grid when the plane is power gated (swith is on and swith 2 is off). Note that the two reonfigurable swithes form an additional path from global V DD grid to virtual V DD grid, as depited in Fig. 3. Thus, the effetive resistane of the sleep transistors and the effetive resistane of the reonfigurable swithes are in parallel, partially reduing the off-resistane between global and virtual V DD grids. High-V th swithes are therefore required to maintain signifiant savings in the leakage urrent when the plane is power gated. III. Simulation Results A omprehensive ase study is developed to investigate the benefits and tradeoffs of the proposed reonfigurable deoupling apaitor topology. The analysis setup is de-

3 transistor C4 bump Global VDD grid swith TABLE I Primary physial harateristis of the global and loal power grids [5]. Parameters Values Pith 45 µm Global grid (Metal 0 & 9) Width 40 µm Resistivity (ohm/sq) 0.03 Pith 23.5 µm Loal grid (Metal 8 & 7) Width 20 µm Resistivity (ohm/sq) Ciruit load Virtual VDD grid TABLE II Pakage, TSV, and C4 bump parasiti impedanes [5, 6]. Parameters Values Lumped pakage resistane R pakage mω Lumped pakage indutane L pakage 20 ph Single C4 bump resistane R C4 5 mω Single C4 bump indutane L C4 200 ph Single via-last TSV resistane R tsv 20 mω Single via-last TSV apaitane C tsv 283 ff Single via-last TSV indutane L tsv 35 ph Fig. 4. Plane-level power network illustrating distributed sleep transistors, deoupling apaitors (traditional and proposed topologies), swithing load iruits (gates with ative devies), and the C4 bumps (for the top plane only). sribed in Setion III-A. Simulation results are presented in Setion III-B where the proposed topology is ompared with the traditional topology in terms of area overhead, power supply noise, power gating noise, and leakage urrent. A. Simulation Setup A highly distributed model of a power distribution network is developed for a three-plane 3D IC with via-last TSVs. A 45 nm CMOS tehnology with 0 metal layers in eah plane is assumed [5]. A portion of the power network with an area of mm by mm is analyzed using HSPICE. Eah plane onsists of a global power network, virtual power network, distributed PMOS sleep transistors, distributed deoupling apaitane, and distributed swithing load iruits, as depited in Fig. 4. Top two metal layers (9 and 0) on eah plane are dediated to global power distribution network with an interdigitated grid of.metal layers 8 and 7 are used as the virtual power network represented by an interdigitated grid of 2 2. Power gating is ahieved using a distributed method where the sleep transistors that ontrol a plane are plaed within that plane [3]. Primary physial harateristis of the 3D power grid are listed in Table I. The pith and width of the metal lines are determined based upon the tehnology design rules [5] while also onsidering routing onstraints. Physial harateristis of the via-last TSVs, C4 bumps, and the pakage impedanes are listed in Table II. A fliphip pakage is assumed and modeled with a lumped resistane of mω and indutane of 20 ph [6]. C4 bumps are regularly plaed with a pith of 200 µm over the mm mm area [5]. Eah C4 bump has a resistane of 5 mω and indutane of 200 ph. Clustered via-last TSVs are distributed throughout the area as a 0 0 array and onnet the global power grid on eah plane. Eah TSV luster onsists of nine TSVs. A single via-last TSV is modeled as an RLC iruit [7] with the impedane values listed in Table II. As opposed to using pieewise linear (PWL) urrent soures to model the swithing load iruit (typial pratie in existing work [8]), gates with ative devies are used sine power gating is onsidered. Similar to [8], inverter pairs with varying size are used to model the swithing load iruit. The overall area is divided into 30 segments and a swithing iruit is onneted to eah segment to onsider the spatial heterogeneity of the urrent loads. The spatial load urrent distribution is determined based on [9], whih produes a peak power density of approximately 40 W/m 2 [20]. As an example, the load urrent distribution of the top plane is illustrated in Fig. 5 where the peak urrent for eah blok is indiated. The deoupling apaitors are implemented as MOS apaitors and distributed throughout the entire die area based on the spatial power supply noise distribution. B. Results on Power Integrity and Overhead The effiay of the proposed deoupling apaitor plaement topology is demonstrated by omparing the methodology with the traditional topology. Three power gating senarios are onsidered: Senario : All of the three planes are ative, representing the greatest workload. Senario 2: The top and bottom planes are ative, while the middle plane is power gated. Senario 3: Only the bottom plane is ative, while the middle and top planes are power gated. B. Area Overhead Area overhead is listed in Table III. For both topologies, the deoupling apaitors are sized to ensure that the

4 Node voltage (V) Time (ns) Fig. 6. Transient behavior of voltage noise at a speifi node within the bottom plane for eah topology for senario 3. (Unit of peak urrent: ma) Fig. 5. Current distribution within the top plane based on [9]. The numbers refer to the peak urrent drawn by the digital gates at eah node. TABLE III Comparison of the physial area overhead of the traditional and reonfigurable topologies. Transistors Swith Area 36.3 mm 2.87 nf N/A 6.70% 36.3 mm 3.20 nf 60 mm 8.25% worst ase power supply noise is within 5% of the V DD (50 mv) in senario. Note that the size of the deoupling apaitors, sleep transistors, and swithes (for the reonfigurable topology) in Table III refers to per plane. In the proposed topology, the area overhead inreases from 6.70% to 8.25% (by only.55%) due to reonfigurable swithes and higher deoupling apaitane required to ompensate for the shielding effet of the reonfigurable swithes. Note that all of the deoupling apaitors are implemented as MOS apaitors in 45 nm tehnology with an oxide thikness of nm [5]. This slight inrease in the physial area signifiantly enhanes power integrity when one or more planes are power gated, as desribed in the following subsetions. B.2 Power Supply Noise Power supply noise results are listed in Table IV for eah senario. Note that power supply noise is observed in the bottom plane. As listed in this table, when some of the planes are power gated (senarios 2 and 3), the reonfigurable topology ahieves less power supply noise by exploiting the apaitors of the power gated plane(s). For example, in senario 3 where two planes are power gated, the redution in peak noise is approximately 27% whereas the redution in RMS noise is approximately 46%. Note that in the traditional topology, the peak noise in senario 3 exeeds 50 mv despite the redution in overall swithing urrent due to power gating. This harateristi is due to less deoupling in the power network sine the deoupling apaitors in the power gated planes annot behave as harge reservoirs for the remaining, ative planes. This Node voltage (V) Time (ns) Fig. 7. Transient behavior of power gating noise at a speifi node within the bottom plane for eah topology for senario 3. observation justifies the need for reonfigurable apaitors. Transient behavior of voltage noise at a speifi node within the bottom plane is also depited in Fig. 6 for senario 3, demonstrating the redution in peak and RMS noise. B.3 Power Gating Noise To investigate power gating noise, the power gated middle plane transitions from inative to ative state in senarios 2 and 3, and the voltage flutuation due to in-rush urrent during the wake-up proess is analyzed. Peak power gating noise is observed at the bottom plane. Results are listed in Table IV. The reonfigurable topology ahieves more than 80% redution in peak and RMS power gating noise. In traditional topology, a signifiant amount of inrush urrent flows not only for the ativated iruit, but also to harge the assoiated deoupling apaitors. Alternatively, in the reonfigurable topology, the deoupling apaitors are onneted to the global V DD grid when the plane is power gated. Thus, even if the plane is power gated, these apaitors remain harged (signifiantly reduing in-rush urrent) and an behave as harge reservoir one the plane transitions to ative state. The transient behavior of the power gating noise is illustrated in Fig. 7 for senario 3 where the transition happens at ns.

5 TABLE IV Power supply noise and power gating noise obtained from eah senario and noise redution ahieved by proposed topology. Power status Power supply noise (mv) Power gating noise (mv) Top Mid. Btm. Peak RMS Peak Redtn. RMS Redtn. Peak RMS Peak Redtn. RMS Redtn. Senario on on on N/A % N/A N/A Senario 2 on off on % % % % Senario 3 off off on % % % % TABLE V Overall Average Power Consumption (when all of the deoupling apaitors are implemented as MOS apaitors) Power (mw) Power (mw) Overhead (%) Senario % Senario % Senario % B.4 Power Overhead To quantify the power overhead of the reonfigurable topology, both topologies are simulated for eah senario and the overall average power onsumption is determined. All of the deoupling apaitors are implemented as MOS apaitors to onsider MOS-C leakage. Results are listed in Table V. The smallest overhead ours in senario where all of the planes are ative. This overhead is due to inreased apaitane and swithes (for the reonfigurable topology only). Power overhead inreases to 5.85% in senario 3 due to the leakage urrent of MOS apaitors that are onneted to the global grid. The absolute power is, however, signifiantly smaller in this senario ompared with the peak power in senario. Thus, the maximum power inreases by only.36%. Also note that this power overhead an be further redued if low leakage deoupling apaitor implementations are adopted suh as metal-insulator-metal (MIM) apaitors. IV. Conlusions In 3D ICs with power gating, traditional deoupling apaitors within a power gated blok/plane are disonneted from the global grid, and therefore are ineffetive for neighboring ative bloks/planes. apaitors have been proposed to alleviate this issue and signifiantly enhane system-wide power integrity. Analysis results demonstrate up to 46% and 85% redution in, respetively, RMS power supply and power gating noise at the expense of.55% inrease in physial area and.36% inrease in peak power onsumption. Referenes [] V. F. Pavlidis and E. G. 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