Simulator Based Simplified Design Approach of a CMOS 2-Stage Opamp

Transcription

1 IASIT International Journal of Engineering and Tehnology, Vol. 4, No. 6, Deember 2012 Simulator Based Simplified Design Approah of a MOS 2-Stage Opamp Ashis Kumar Mal, Abirjyoti Mondal, Om Prakash Hari, and Rishi Todani response is aoided. In PDM, the dimensions of a deie are found using a simulator; suh that a desired urrent at pre-defined bias onditions are set. Sine the bias onditions are predefined, PDM ensures that all the transistors are in saturation. This methodology an be applied to any analog blok and is independent of power supply and tehnology. In this work, a 2-Stage opamp is designed using PDM. The performane of an opamp is haraterized by a number of metris suh as gain bandwidth, phase margin, slew rate, low frequeny gain and output swing. These performane metris are determined by bias urrents, omponent parameters, et. Further, sine opamps are often employed with negatie feedbak [8], frequeny ompensation beomes ital for losed loop stability. In order to ahiee the required degree of stability, usually indiated by phase margin, other performane parameters are ompromised. The following setion presents the design approah, simulation results and design optimization tehniques. Abstrat Two stage (Miller) opamp is one of the most ommonly used opamp arhitetures in analog and mixed signal design. This paper presents the design of a Miller opamp using Potential Distribution Methodology (PDM). It is obsered that a wide ariety of design objeties depend on distribution of oltages and urrents aross the differential and gain stage. These dependenies are exploited to optimize the opamp performane and simulation results are presented. Index Terms MOS, opamp, PDM. I. INTRODUTION Analog and mixed signal design has always been a hallenging task. Opamps are one of the most important building bloks of analog and mixed signal iruits. Typial opamp design tehniques gien in literature [1], [2], [3] and een reently published work [4], [5] onentrate mainly on analytial design approah. Being based on SPIE leel 1 or leel 2 models, the mathematial expressions assoiated with these tehniques are generally simple. Howeer, these expressions are large in number. Young and noie designers may find it diffiult to manage so many equations. Alternate design methodologies are also proposed in [6], [7], whih handle these equations using other tools like MATAB, Mathematia, et. Managing equations may beome easier with these tools; howeer, the design methodology may beome extremely omplex. When the results obtained by these tehniques are used to implement iruits in modern simulator using deep sub-miron deies (whih is usually the ase), the simulation results do not math with mathematial expetations. This is primarily due to the fat that deep sub-miron deies are modeled using long hannel equations. The designer is then fored to adopt a simulator-based approah to optimize the design. Whateer may be the approah; the net time to market inreases signifiantly. PDM is an analog design methodology, whih is free from any analytial expression. It diretly uses the simulator to arrie to a design point. As the simulator uses the target tehnology and is apable of handling aurate and omplex SPIE models like BSIM, unexpeted results or Fig. 1. Shemati of 2-stage miller opamp. II. SINGE-ENDED 2-STAGE OPAMP ARHITETURE Fig. 1 details the arhiteture of a 2-Stage Miller opamp [8], [9]. The iruit onsists of an input differential stage and a ommon soure stage. A ompensation apaitor () proides negatie feedbak to ommon soure amplifier. Wide Swing urrent Mirror shown in Fig. 2, and gien in [1], [10], biases the differential and gain stage. This opamp is widely used in a ariety of appliations suh as swithed apaitor filters, sensing iruit, analog to digital onerters. Manusript reeied June 22, 2012; reised July 29, This work was supported in part by National Institute of Tehnology, Durgapur under Grant SMDP. Ashis Kumar Mal and Rishi Todani are with the National Institute of Tehnology, Durgapur India ( akmal@ee.nitdgp.a.in, todani.rishi@gmail.om). Abirjyoti Mondal was with the National Institute of Tehnology, Durgapur INDIA. He is now with the Department of omputer Engineering, Malaiya National Institute of Tehnology, Jaipur, India ( abir_jm@hotmail.om). Om Prakash Hari is with the Tejas Netwoks td. ( om.nitd@gmail.om). DOI: /IJET.2012.V4.493 Fig. 2. Shemati of wide swing urrent mirror 826

2 III. DESIGN OF 2-STAGE OPAMP USING PDM The 2-Stage opamp is initially designed without muh onsideration on its performane metris. One, the first ersion of the design is ready, it is modified and optimized to meet the design requirements. PDM uses simulator to find the deie dimensions that auses a speified urrent at pre-defined bias onditions. The bias onditions are hosen suh that VDS VGS VT keeping VGS VT. Using these onditions, the bias oltages are seleted ensuring that the deies remain in saturation. In this work, proprietary 180 nm MOS proess employing BSIM 33 model has been used with VDD = 1.8V. The lengths of all transistors are fixed at 500 nm. The design methodology is broken into following steps: A. Identify Node Voltages It is desirable to note all the node oltages that are at ommon mode leel (in this ase V DD / 2 or approximately 0.9 V). It is identified that the input nodes ( in+ and in ) and the output node ( V ) must be kept atv / 2. out B. urrent, I Slew rate (SR) requirement sets the lower limit of tail urrent ( I ) and is gien by I = SR where is the load apaitane. Half of this tail urrent ( I / 2 ) flows through the differential pair transistors, M 0 & M 1. urrent mirror shown in Fig. 2 biases M 2 whih sets I. DD Fig. 3. Effet of body bias on threshold oltage.. Threshold Voltage Estimation It is known that staking of transistors lead to body bias, whih in turn inreases threshold oltage of the deies. For proprietary 180nm MOS proess, the effet of body bias on threshold oltage is shown in Fig. 3. D. Transistor, M 2 The design is started by estimating drop aross tail transistor (M 2 ). It does not experiene any body bias and arries a urrent equal to I. From Fig. 3 its threshold oltage (V T0n ) is read as 0.45 V. With oerdrie (V o ) of 0.1 V, an appropriate bias oltage of b 1 = Vis applied to gate. Drain to soure drop aross tail transistor is kept at 0.3 V. Thus node A is kept at 0.3 V. Thus, for M 2, VGS = 0.55 V and VDS = 0. 3V. Using simulator a plot of drain urrent ersus transistor width at pre-defined bias onditions is obtained. From this plot, the transistor width orresponding to I is hosen. E. Differential Pair M 0 and M 1 From Fig. 1 it is noted that gates of M 0 and M 1 are at V = / 2. The soure terminal (node A) of these M V DD transistors is at 0.3V. Thus the differential pair will haevgs = 0. 6 V. Due to existene of body bias, threshold oltage (V Tn ) of M 0 and M 1 is more than V T0n. V Tn of M 0 and M 1 must be less than V GS with body bias. If not, then the potential at node A is hanged aordingly so as to lower body bias and threshold oltage. Sine differential pair is fully symmetri between differential inputs, transistor sizes are also fully symmetri. To keep M 1 in saturation, oltage at node B is kept at 0.8 V. Due to systemati offset ondition, drain oltage of M 0 is same as that of M 1. Thus for differential pair, VGS = 0. 6 V and VDS = 0. 5 V. Therefore, B and are at 0.8 V. F. urrent Mirror M 3 and M 4 Transistor M 3 is always in saturation beause V GD = 0. Systemati offset ondition implies that drain soure (V DS ) oltage of M 4 is same as that of M 3. So M 3 is also in saturation. Dimensions of M 3 and M 4 are noted for predefined bias oltages using simulator. G. Transistor M 5 and M 6 The oltage at node B is applied to gate of NMOS drier (M 5 ) and an appropriate oltage of 0.6 V to gate of PMOS load (M 6 ). The output of opamp is fixed at 0.9 V. It is noted that with aboe set up M 5 and M 6 are in saturation. The dimensions of M 5 and M 6 are obtained using simulator for a urrent same as I. H. ompensation Network ompensation apaitor ( ) is inluded in the negatie feedbak path of the seond stage. Its funtion is to enhane the Miller effet already present in M 5, and thus proide the opamp with a dominant pole. The alue of is seleted using = 0.22 Typially, 2-Stage opamps employ a ompensation resistor in series with the ompensation apaitor to plae a zero on the negatie real axis. As per the aailable literature, the alue of this resistor is gien by: 1 R Gm 5 where, G m5 is the transondutane of the seond stage. The transondutane of transistors are readily proided by modern simulators. Using this, the alue of resistane is first estimated. In this ase, R = 3. 7 ΚΩ. In this work, the ompensation resistor is realized by using transmission gate 827

3 (TG). Using TG instead of a resistor makes the design area effiient. Test iruit shown in Fig. 4. is used to estimate the resistane offered by TG. are is taken that the transistors are operating in linear or triode region and a plot of deie dimension ersus resistane is obtained as shown in Fig. 5. From this, suitable deie dimension is hosen whih offers required resistane. When all the deie dimensions are found out, the omplete opamp shemati is drawn and simulated. transistor (M 2 ) of differential stage was kept at 30 µa. The node potentials at the initial design set up are shown in Table I. The urrent in the gain stage was fixed at I. D analysis results show that all transistors are in saturation and respetie dimensions are noted as shown in Table II. A analysis results with = 1 pf and = 220 ff is shown in Table III. TABE III: INITIA RESPONSES Performanes Gain Response 60.3 db Bandwidth khz Phase margin 62º UGF MHz Fig. 4. Test iruit for estimation of resistane using TG. Fig. 5. Plot of resistane ersus dimensions. TABE I: NODE POTENTIAS AT INITIA DESIGN Node Potentials A 0.3 B in+ 0.9 in 0.9 out 0.9 V. OPTIMIZATION The effet of urrent and oltage distribution aross the opamp is now examined. It is found that the performane of the opamp an be optimized in two ways. First, the urrent distribution between the differential and gain stage, and seond, adjusting the potential at nodes A and B. A. urrent Distribution Keeping the node oltages fixed at pre-defined alues shown in Table I, urrents in M 2 and gain stages are aried in suh a way so that total urrent remains same. Again d analysis followed by a analysis is performed for speified urrent branhing. The transistor dimensions are noted along with performane metris for the same apaitane alue. Fig. 6 depits dependeny of D gain and 3 db bandwidth (BW) on perentage urrent entering differential transistors. It is seen that D gain remains onstant whereas BW improes with urrent branhing. Fig. 7 shows the ariation of phase margin (PM) and unity gain frequeny (UGF) with urrent branhing. Both PM and UGF are dereasing with perentage urrent entering differential pair. Taking the stability of the opamp into onsideration, a suitable urrent distribution whih sets the desired PM may be hosen. TABE II: TRANSISTOR WIDTH AT INITIA DESIGN (=500NM) Transistor Width ( µm) W W W W W W W IV. SIMUATION RESUTS AND ANAYSIS Using the design steps disussed in preious setion, a 2-Stage Miller opamp was designed using 180 nm MOS proess employing adene Spetre. The urrent in the tail Fig. 6. Gain and 3dB bandwidth dependeny. 828

4 Fig. 7. Phase margin and unity gain frequeny dependeny. B. Node Voltage Variation Further analysis was performed with urrents from preious results. Here urrent is kept fixed at both tail transistor and gain stage while node oltages are aried. The oltages at either of the nodes A or B are aried keeping the other at fixed alue. The seletion of oltages is done taking into onsideration threshold oltage of the transistors and gate bias oltages. After one iteration of analysis, the potential at fixed node is hanged to next suitable alue. It is kept fixed and ariation ours at other node for the said urrent only.. Potential at Node A Initially urrent in M 2 and gain stage was fixed at 30 µa. The oltage at node B was fixed at 0.8 V and node A oltage was aried. Then d analysis followed by a analysis is performed for eery possible oltage distributions. Transistor dimensions are noted using simulator. Performanes are first noted for = 1 pf and = 220 ff. Then the improed performanes are obtained with = 400 ff and = 88 ff [1]. This proess is repeated by speifying a fixed oltage at node B and simultaneously arying node A oltage for same pre-defined urrent. From Fig. 8-9 it is noted that gain, BW and UGF improes while PM lowers for fixed oltage at node B and ariation at node A. D. Potential at Node B Now the potential at node A is kept fixed and potential at nodes B is aried. Performanes are first noted for default alue of apaitanes and then improed performanes for pre-defined alue of apaitanes. Fig depits that gain, PM and UGF are lowering while BW improes for fixed oltage at node A and ariation at node B. Although PM is diminishing it is within the limit for a speifi oltage distribution mentioned initially so as to attain stability. The optimal results are obtained when drop aross the tail transistor is kept at 300 mv, drop aross differential pair is around 700 mv and rest drop aross PMOS load. It was also obsered that same trend in hanges our for the remaining urrent branhing. Fig. 10. Gain and 3dB bandwidth dependeny. Fig. 8. Gain and 3dB bandwidth dependeny. Fig. 9. Phase margin and unity gain frequeny dependeny. Fig. 11. Phase margin and unity gain frequeny dependeny The optimal results for 30 µa urrent branhing are gien in Table IV. It is also obsered from simulation that if urrent distribution is inreased for pre-defined ratio then better unity gain frequeny an be ahieed while phase margin is lowered. Minimizing urrent distribution in same ratio results in improed phase margin and unity gain frequeny is degraded. 829

5 TABE IV: PERFORMANE MEASURES FOR 30 µa IN TAI PORTION AND NODES A AND B AT 300 MV AND 700 MV RESPETIVEY Performanes Initial Performane Optimized Gain 60 db 62 db Bandwidth khz 240 khz Phase margin 62º 59º UGF MHz 237 MHz Aided Design of Integrated iruits and Systems, ol. 20, no. 1, pp , Jan [7] M. Hershenson, S. Boyd, and T. ee, Optimal Design of a MOS Op-amp ia Geometri Programming, IEEE Transations on omputer-aided Design, ol. 20, no. 1, pp. 1-21, Jan [8] P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design A Tutorial Oeriew, IEEE J. of Solid-State iruits, ol. 17, pp , De [9] D. A. Johns and K. Martin, Analog Integrated iruit Design, New York: Wiley, [10] R. J. Baker, MOS iruit Design, ayout, and Simulation, Wiley-Intersiene, VI. ONUSION PDM is found to be free from omplexity of analytial expressions and maintains a simple design methodology, whih an be applied to any analog design. So noie designers an implement the steps mentioned preiously to design an opamp. Sine PDM is independent of supply oltage, proess tehnology and the MOSFET model being used, it an be applied to any omplex opamp strutures. The results are obtained quikly and are aurate to a greater extent as ompared to designs based on analytial equations. The Potential Distribution Method (PDM) proposed earlier is repeated here for the design of 2-Stage Miller opamp and the trade off assoiated with tail urrent ariations upon performane metri was plotted. It is obsered that a speifi oltage distribution using PDM results in improed performanes and the transistors in saturation, thus simplifying the design proess. AKNOWEDGMENT The authors graefully aknowledge Dr. Debashis Datta, Ministry of ommuniation and Information Tehnology, Got. of India, for extending the SMDP projet at NIT Durgapur. Prof. S. K. Datta, Prof. G. K. Mahanti SMDP hair of NIT Durgapur and Prof. Swapna Banerjee, SMDP hair of IIT Kharagpur are thanked. The authors also aknowledge Kanhan Maji, Projet Engineer SMDP II, for his kind assistane. REFERENES [1] P. E. Allen and D. R. Holberg, MOS Analog iruit Design, Oxford Uniersity Press, [2] B. Razai, Design of Analog MOS Integrated iruits, Analysis and Design, Tata MGraw-Hill Publishing ompany imited, [3] S. Frano, Design with Operational Amplifiers and Analog Integrated iruits, MGraw-Hill ompanies, [4] P. K. Meduri and S. K. Dhali, A framework for automati OpAmp sizing, IEEE International Midwest Symposium on iruits and Systems, pp , Aug [5] K. Bult and G. Geelen, A Fast-Settling MOS Operational Amplifier for S iruits with 90-dB D Gain, IEEE J. of Solid-State iruits, ol. 25, pp , De [6] P. Mandal and V. Visanathan, MOS Op-Amp Sizing Using a Geometri Programming Formulation, IEEE Trans. on omputer Ashis Kumar Mal reeied his Ph.D. in miroeletronis and VSI from the Indian Institute of Tehnology, Kharagpur, India, in He joined the Eletronis and ommuniation Engineering Department, North Eastern Regional Institute of Siene and Tehnology (NERIST), Itanagar, in 1993 as a eturer. In 2007, he joined the National Institute of Tehnology (NIT), Durgapur, and urrently seres as an Assoiate Professor there. His researh interests inlude mixed signal VSI design, sampled analog iruits, interonnet modeling, and optial networking. He has oauthored more than 40 tehnial papers. He is a member of IEEE. Abir jyoti Mondal was born in June 1984, India. He did his Bahelor of Engineering in Eletronis and ommuniation engineering under Burdwan Uniersity, India in Further he ompleted his M.Teh degree in Miroeletronis and VSI from National Institute of Tehnology, Durgapur, India in His major field of study is Networks on hip. He is urrently working as a Researh Sholar at Malaiya National Institute of Tehnology, Jaipur, India. Om Prakash Hari obtained his B. Teh in Eletronis & ommuniation Engineering, from The Tehno Shool, Bhubaneswar, under Biju Patnaik Uniersity of Tehnology, Rourkela, India in He reeied M. Teh degree in Miroeletronis & VSI under department of Eletronis and ommuniation Engineering, from National Institute of Tehnology, Durgapur, India, in His urrent researh atiities and interest inlude VSI system design, high speed ADs, high speed serial protool design, semiondutor memories design and optimization. He is urrently working as Researh & Deelopment Engineer at Tejas Networks td, Bangalore, India. Rishi Todani was born in a small town alled Raniganj, situated in the Burdwan distrit of West Bengal, India, on 3 rd Otober He obtained his B.E. degree in 2008 in eletronis engineering from Uniersity of Mumbai and his M.Teh. degree in Miroeletronis and VSI in 2010 from National Institute of Tehnology, Durgapur. His primary field of work inlude analog and mixed signal design. In 2010 he joined the EE Department at National Institute of Tehnology, Durgapur as a Projet Faulty in SMDP-II Projet and is urrently working there. Mr. Todani is an IEEE Member. 830