A Digitally Controlled Oscillator for ADPLL Application. Wu Xiulong, Wang Faniu, Lin Zhiting, and Chen Junning

Transcription

1 pplied Mehanis and Materials Online: ISSN: , Vols , pp doi:.428/ 22 Trans Teh ubliations, Switzerland Digitally Controlled Osillator for DLL ppliation Wu Xiulong, Wang Faniu, Lin Zhiting, and Chen Junning Shool of Eletroni and Information Engineering, nhui University, Hefei,China Keywords: Digitally Controlled Osillator; Wireless Communiation; MOS varators ; Frequeny Moderation bstrat. In order to solve the defets in performane for analog RF iruit in deep submiron proess, this paper disusses a new type of LC osillators(digitally Controlled Osillator), whih uses digital RF method to ahieve the tehnology requirements of wireless ommuniation. This new type of osillator uses MOS varator arrays to moderating the output frequeny, through the using of digitally Sigma-Delta tehnology, we an get more preise resolution, and through using three modes progressively working way an make this kind of struture easily implement in proess. Introdution With the explosive growth of the wireless ommuniation industry, researh related to ommuniation iruits and arhitetures has reeived great attention. The issues being addressed are low ost, low voltage and low power designs, whih ahieve neessary performane while be able to be eonomially manufatured in high volumes. s the feature size of the digital logi CMOS tehnology beomes smaller, the frequeny at whih CMOS transistors an operate while delivering aeptable performane beomes higher. Espeially, when CMOS proess goes into ultra deep sub-miron(udsm), CMOS iruit has more and more advantages. However, RF transeiver requires higher performane, the traditional voltage ontrolled osillator(vco) annot be ompetent. Reently, the ideal of digitally RF was widely used in wireless ommuniation field[]. Beause in UDSM CMOS proess, the digitally iruits have faster flip speed and higher integrated level. Some traditional RF iruits an be replaed by the digitally iruits[2]. In this work, we will introdue a digitally ontrolled osillator(dco), whih ontrolled by digitally iruits. Figure is the struture diagram of DCO. The frequeny ontrol words are d to d n-. The osillation is perpetuated by a negative resistane devie, whih is normally built as a positive feedbak ative amplifier network. Fig. The struture diagram of DCO Figure 2 shows normalized representative urves of a MOS varator apaitane versus ontrol voltage (C V) urve for both a traditional CMOS proess and a UDSM proess[4]. reviously, a large linear range of the C V urve ould be exploited for a preise and wide operational ontrol of frequeny. With a UDSM proess, the linear range is now very ompressed and has undesirable high gain, whih makes the osillator extremely suseptible to noise and operating point shifts. Due to the well isolation properties in the proess, the MOS devie is a better andidate for a varator. The inversion-type varator features more distintly defined operational regions than does the aumulation-type varator. In fat, the flat on-state region of the depletion mode and the flat off- ll rights reserved. No part of ontents of this paper may be reprodued or transmitted in any form or by any means without the written permission of Trans Teh ubliations, (ID: , ennsylvania State University, University ark, US-/5/6,9:38:39)

2 56 Mehanial and Eletrial Tehnology IV Fig.2 Idealized apaitane versus voltage urves of a MOS varator [4] Fig.3 Core iruit of DCO state region of the inversion mode are used as two stable binary-ontrolled operating points. dvaned CMOS proess lithography today allows the reation of extremely small-size, but well-ontrolled varators. The swithable apaitane of the finest differential least signifiant bit varator is on the order of tens of attofarads. The slight drop of apaitane in the flat strong inversion region had not been of any pratial signifiane until the advent of UDSM CMOS proesses. It is due to the depletion layer being reated in the gate polysilion. DCO ore iruit design The Core iruit of DCO is shown as figure 3. The ross-oupled pair NMOS transistors Mn and Mn2 in aompany with the MOS transistors Mp and Mp2 has the ability to generate the negative resistane to ompensate the LC tank loss. The tank onsists of an indutor and varators Cr array. Mp4 provides the tail urrent. The value of varators array is determined by digital ontroled signal. In LC tank, the osillated frequeny is f () LC In DCO, we divided the total apaitane into N individual digitally ontrolled varators[3], then equation () beomes f (2) N L C k k The DCO entral frequeny is.2ghz. In SMIC CMOS.8um 6M proess, onsidering the area and Q value of indutor, we hoose 6.3nH. ording to the indutor parasiti resistane, we an determine the transondutane( gm) of ross-oupled MOSFETs[4]. In order to ompensate the LC tank loss, we need gmr5. The transondutane is influened by tail urrent and MOSFET width and length. We set tail urrent 3m by experiene, then, the value of MOSFET W/L an be derived. We an use these iruit parameters as initial value to simulate the DCO, obtaining the optimized performe through adjusting these parameters. The varators in DCO onsists a pair of same size MOS and NMOS[5]. ording to the values of frequeny ontrolled words, the ontrol voltage signal is generated from soure, drain, substrate of the differential varators. Then, the varator ould work in high apaitane state and in low apaitane state. Varator array ould also work in this two states, C high,k and C low,k. The apaitane differene of high and low state is C C C (3) k highk, lowk, C k is a single-bit k ontrolled effetive apaitane value. So C C + d C (4) k low, k k k where C k is the FCW. We an re-write equation (2),

3 pplied Mehanis and Materials Vols f L N k ( Clow, k+ dk Ck) When it is arranged as d, d, d2... dn, the MSB signal d n- ontrols the maximal apaitane C n- ; the LSB signal d ontrols the minimum apaitane C. DCO tuning resolution is determined by C. Implementation of DCO tuning We ould use an example to illustrate the proedure of DCO tuning. When the osillating frequeny is.2 GHz and a frequeny resolution of khz, at least 2 bits of DFC resolution is required. It is learly utmost diffiult to ahieve this kind of preision even with the most advaned omponent-mathing tehniques. The best one ould hope to eonomially ahieve is 8 bits of apaitor mathing preision, without resorting to elaborate mathing shemes that often require numerous and time-onsuming design, layout, and fabriation yles. In fat, better than -bit resolution would normally require by the follow tuning tehniques. In the first step, the large osillating frequeny unertainty due to the VT variations is alibrated. fter the VT alibration, the nominal enter frequeny of the osillator will be lose to the enter of the Bluetooth band. Sine this unertainty ould easily be in the hundreds of megahertz range, -MHz inrement is satisfatory. In this ase, an 8-bit resolution is suffiient. The seond step is to aquire the requested operational hannel within the available band. For an 8-bit resolution, half-megahertz steps would span over MHz, whih is enough for the 8-MHz Bluetooth band. The third step is the finest, but with the most narrow-band range, and serves to trak the frequeny referene and to perform data modulation within the hannel. Traking-mode operation presents a different set of requirements. The frequeny range is relatively low but the resolution required is quite high. In the proposed solution, the -MHz hannel spaing resolution of the Bluetooth band already starts at the first step (VT), but beause of the very oarse frequeny seletion grid possibly overing multiple hannels, the best that ould be ahieved is to get near the neighborhood of the desired hannel. However, the fine seletion of the requested hannel ould only be aomplished in the third step, whih is most refined of them all. Therefore, the traking mode dynami range has to additionally over the resolution grid of the preeding aquisition mode. The DCO operational mode progression ould be desribed mathematially. When power-up or reset, the DCO is set at a enter resonant frequeny f by appropriate presetting of the dk inputs. This orresponds to a state in whih varators representing half of the total apaitane are turned on to extend maximally the operational range in both diretions. The total apaitane value of the LC tank is C and the natural frequeny is f (6) During VT mode, the DCO will approah the desired frequeny f by setting the d p ontrol bits appropriately so that the new total apaitane is C C+ C.The resulting final frequeny of the VT mode is f (7) The aquisition mode will start from a new enter frequeny of f. It will approah the desired frequeny f by appropriately setting the d ontrol bits so that the new total apaitane is C C + C + C. The resulting final frequeny of the aquisition mode is f (5) (8)

4 58 Mehanial and Eletrial Tehnology IV The traking mode will begin from a new enter frequeny of f. It will reah and maintain the desired frequeny f by setting the d T ontrol bits appropriately so that the total apaitane is T C C + C + C + C. Traking-mode ontains integrated-resolution and frational- tott, resolution traking. The integrated-resolution traking varator for normal operation, and frational-resolution traking varator bank for high speed dithering. DCO simulation results The DCO is designed by SMIC CMOS.8um 6M proess. The supply voltage is 3.3V. The simulation tool is Spetre. Figure 4 shows the higest and lowest frequeny of the DCO an work. Figure 5 is the osillate output waveform in time domain. We an see that the start osillate time is about 45ns. Fig.4 The frequeny range of DCO output Fig.5 The output waveform of DCO Summary We have introdued a new type of LC osillator, whih is digitally ontrolled osillator. The DCO struture and funtion is desribed. DCO tuning proedure is divided into three steps, simulation results show the output signal frequeny step by step. We an see that DCO gets more preise frequeny resolution in the UDSM CMOS proess. knowledgment This work is supported by the Key Researh rojet of nhui Eduation Department (KJ222). Referenes [] Hosseini,. Gharaee, H. Optimum quad band DCO in DS method for WCDM transmitter in 9nm CMOS. IEEE International Conferene on Semiondutor Eletronis, pp.45-48, 28. [2] R.B.Staszewski, John Wallberg, et al. ll-digital LL and GSM/EDGE Transmitter in 9nm CMOS. ISSCC Dig. Teh. apers, pp , Feb. 25 [3] Wei Liu, Wei Li, et al, VT Tolerant to 5 MHz ll-digital hase-loked Loop With Coupled TDC and DCO. IEEE Journal of Solid-State Ciruits,Vol.45, pp.34-32, Feb. 2 [4] Sang-Sun Yoo, Jeong-Ho ark, et al, The variations of osillation freqeuny aording to the osillation amplitudes in DCO. IEEE International Conferene of Eletron Devies and Solid-State Ciruits (EDSSC), pp.-4, 2 [5] Xueyi Yu, Yuanfeng Sun Li Zhang,et al, GHz Frational-N LL Clok Generator with Low-OSR Modulation and FIR-Embedded Noise Filtering, ISSCC Dig. Teh. apers, pp , Feb. 28

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