Multi-Level DC/DC Power Conversion System with Multiple DC Sources Miaosen Shen

Transcription

1 Multi-evel DC/DC Power Conversion System with Multiple DC Soures Miaosen Shen Siemens DO Automotive, Fang Z. Peng Mihigan State University, eon M. Tolbert University of Tennessee, Abstrat: A multilevel d/d power onversion system with multiple d soures is proposed this paper. With this onversion system, the output voltage an be hanged almost ontuously without any magneti omponents. With this magneti-less system, very high temperature operation is possible. Power loss and effiieny analysis is provided the paper. Comparison results show that the system does not require more semiondutors or apaitane than the traditional boost onverter. Experimental results are provided to onfirm the analysis and ontrol onept.. NTODUCTON d d DC/ DC Converter Module DC/ DC Converter Module nverter DC Bus out Traditional d/d onverters require at least one dutive omponent, whih is bulky, heavy, and ostly. With the tehnology advanement of the silion arbide (SiC) devies and erami apaitors, very high temperature omponents (above 5 o C) will be available exept magneti ores. Thus very high temperature operation of magneti-less onverter beome possible and very attrative beause natural air oolg an be adopted, whih will redue the size, weight, and the ost of the onverter signifiantly. The multi-level d/d onverter [-9] beomes a good andidate for this appliation, beause there are no magneti omponents neessary, and also beause of its bi-diretional nature. Traditional multi-level d/d onverters usually output a fixed voltage for a given put voltage, this may beome a drawbak of these onverters beause for some appliations, suh as hybrid vehiles, a variable d bus voltage is preferable so that the verter an always be operated its most effiient d voltage. n this paper, a bi-diretional multi-level d/d onversion system that an output variable voltage with multiple d soures will be proposed.. DESCPTON OF THE DC/DC CONESON SYSTEM The proposed d/d onversion system is shown Fig. (a), where there are n isolated d soures, d ~ dn, and n idential d/d onverters ells with the output onneted series. One possible appliation of this topology is hybrid eletri vehiles, stead of onnetg all batteries series as one power soure and a bi-diretional boost onverter to terfae the battery and the d bus, one an use separate batteries to power separate onverter modules and onnet the output of the modules series as a d bus supplyg the verter. The d/d onverter ell is shown Fig. (b), whih is a two level onverter. dn DC/ DC Converter Module n n (a) D/d power onverter system onfiguration d S S S3 S4 out (b) Topology of the d/d onverter module Fig.. D/d power onversion system onfiguration and onverter ell topology. For eah d/d onverter ell as shown Fig. (b), there are three swithg states as illustrated Fig /7/$. 7 EEE 8 Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

2 . CONETE CONTO DUNG TANSTON a b Fig.. Converter swithg states. 4 Battery n steady state, the voltage differene between the battery and the apaitors beg harged/disharged is very small, therefore the urrent through the swithes is well limited. Durg transition when one wants to hange the output voltage between and *, the voltage differene between the two ould be relatively large, whih might result high transient urrent. To limit the urrent, a small dutor as shown Fig. 3 is onsidered, the requirement of the dutane is very small (<uh) as will be shown the later setion, it an be onsidered as the parasiti dutane of the able and the ES of the apaitor on the battery side. Usually it would be large enough espeially for hybrid eletri vehiles if the battery is not plaed adjaent to the onverter. a. Change the output voltage from to * Before the output voltage is hanged to, the apaitor voltage,, equals to half of the battery voltage. n this transition, the two apaitors will be harged up from half put voltage to full put voltage, thus put urrent will be higher when the battery is outputtg power durg the transition omparg with when hargg the battery. Therefore, the battery is assumed to be outputtg urrent durg the transition as the ondition is more ritial. When the transition starts, the onverter starts to get to swithg states b and, the equivalent iruit when hargg C and C are shown Fig. 4 (a) and (b) respetively. Fig. 3. Converter with small dutane. With these three swithg states, the onverter is able to output two different voltages. When the onverter is swithg state a, (swithes S and S4 are on, S and S3 are off), the followg equation will be met, i S3 out. () oad Obviously, when the swithes (MOSFETs or GBTs with free wheelg diodes) are turned on, the urrent an flow either diretion, so the onverter is a bidiretional onverter. n the seond mode, the onverter alternates its swithg states between b and omplementarily with 5% duty ratio for eah swithg state at a high frequeny, the followg equations will be met, () Thus the output voltage is out. Also, the onverter is bi-diretional this mode. Therefore, eah sgle module is able to output two different voltages: or *. For a system that onsists of n ells, the system is able to output n+ different voltages from n* to *n* with step of, when the number of n reases, the output voltage an be onsidered as almost ontuous and the verter fed by the d/d onverter an always operate lose to the optimum voltage pot. (a) i S oad (b) Fig. 4. The equivalent iruit of swithg states (b) and (). 9 Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

3 S S S3 S4 Fig.5. Control signals durg output voltage transient from to *. n the transition, the battery is hargg the two apaitors equally. Fig. 4 (a) and (b) eah shows half of the operation ondition. n eah ondition, there are two swithg states: the swith (S or S3) is on or the swith is off. When the swith is on, i equals to one apaitor voltage; when it is off, it equals to the sum of the two apaitor voltages beause of the freewheelg. Thus the effet the swithg state when S is turned on is the same as the state when S3 is turned on terms of dutor urrent. Defg the duty ratio, D, as the sum of the duty ratio of S3 and S and assumg that the dutor urrent is ontuous mode, steady state, the relationship of the apaitor voltage and the put voltage is D ( D) ( D) (3) i From above equation, the duty ratio should be gradually reased from to order to rease the apaitor voltage from / to gradually. As a result, the swithg signals shown Fig. 5 are required to ontrol the swithes. S and S3 show the atual duty yle, whih is half of D, S and S4 are verted signals of S and S3, respetively. b. Change the output voltage from to Before hangg the output voltage from * to, the apaitor voltage equals to battery voltage. The apaitor voltage will be disharged from the battery voltage to half of it, thus the transition is more ritial when the battery is beg harged by the load. The equivalent iruit of swithg state a is shown Fig. 6. When the swith is turned on, S and S4 are turned on the atual iruit. When these two swithes are on, i equals to twie of the apaitor voltage, otherwise i equals to zero due to freewheelg. Assumg the duty ratio is D, the relationship of the voltages and the duty ratio for ontuous urrent ondition is D. (4) As a result, the duty ratio should hange from.5 to gradually to ontrol the apaitor voltage from to / as shown Fig.7. S and S3 are verted signals of S and S4. S,S4 S,S3 Fig. 7. Control signals durg output voltage transient from to. When the swithg frequeny is relatively low, usg the above method may not be suffiient enough to limit the peak urrent beause the urrent hange one yle an be relatively big due to small dutane. To further suppress the peak urrent durg transient, a higher swithg frequeny may be used durg the transition.. OUTPUT OTAGE OSS When outputtg *, dead time has to be implemented order to prevent shoot through. Assume that the put urrent is ontuous beause of the small parasiti dutor, and the duty yle is D (the perentage of time the put is onneted to either of the apaitors). When the put is onneted to one of the apaitors, the voltage aross the parasiti dutor is. (5) Durg the dead time, if the battery is outputtg power to the load, the urrent flows through the freewheelg diodes of S and S4 to harge both apaitors, the voltage aross the dutor is. (6) f the battery is beg harged from the load side, the urrent flows through the freewheelg diodes of S and S3, and the voltage aross the dutor is. (7) Thus the steady state output voltage differs by the diretion of the power flow. When the battery is powerg the load, the output voltage is out. (8) D The output voltage when the battery is beg harged by the load is out. (9) D Thus the output voltage ould be slightly different dependg on the power flow diretion and dead time. Also the voltage drop aross the swithes should be luded. Fig. 6. Equivalent iruit for swithg state (a). Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

4 . POWE OSS ANAYSS n previous literature [-3], the power loss of this type of onverters is analyzed. n the literatures, the parasiti dutane is not onsidered and the C onstant of the onverter is always omparable to the swithg period to ahieve high effiieny. When onsiderg the small parasiti dutane, results differ. When the put is onneted to one of the apaitors, the equivalent iruits with and without onsiderg the parasiti dutor are shown Fig. 8(a), where oad is the load urrent. When there is no dutane, the urrent an be expressed by the followg equation, t C i( t) e oad, () where is the itial voltage differene between the voltage soure and the voltage aross the apaitor. The urrent waveform is shown Fig. 9, the shaded area orresponds to the average put urrent. When onsiderg the parasiti dutor, the put urrent is i( t) C oad oad ( ) f ( t e e t, ) e os( s( t ( C s( ( C ) t) ( C ) t) ) t (, )), () where oad + and are the itial urrent and itial voltage differene between the put voltage and apaitor. Another feature of this ase is that the itial urrent and the urrent when the swith turns off are the same beause the onverter repeats the same proess with the other apaitor after it fishes hargg one apaitor. Thus the put urrent is shown Fig. 9 with the itial urrent equal to the urrent at the end of the proess, the shaded area orresponds to the average put urrent. (a) C oad (b) C oad Fig. 8. Equivalent iruit with and without the parasiti dutane. a b s A T B Current waveform without Current waveform onsiderg Fig. 9. nput urrent of the onverter with and without parasiti dutane. For a fixed output power and given put voltage, the average put urrent is fixed (area A should equal to area B for the same power and voltage), different dutane results different put urrent shape, whih further results different put urrent rms value. The ondution loss of the iruit is diretly proportional to the square of the rms value assumg MOSFETs are used as the swithes. Based on the above equations, one an easily numerially alulate the ratio of rms urrent over the average urrent based on the different parameters, and from whih the loss an be alulated. As an example, Fig. shows the normalized ondution loss of a onverter with different parasiti dutanes, the other parameters of the onverter are: ds on (MOSFET on resistane) = mohm, C (apaitane of eah apaitor) = mf, f s (swithg frequeny) = 5 khz. The normalized loss with no parasiti dutane is 7.. From whih we an see that the ondution loss is dramatially redued with a small parasiti dutane. The swithg loss is diretly proportional to the swithg urrent given the fixed onverter voltage. t is noteworthy that half of the swithg ations this onverter is zero voltage swithg due to the urrent freewheelg Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

5 through the body diodes durg the dead time. The swithg urrent is the itial and endg urrent, a, b, and s, shown Fig. 9. Fig. shows the swithg urrent normalized by the average urrent for the same onverter versus different parasiti dutanes. From Fig., the swithg urrent redues as the parasiti dutane redues until it reahes the resonant pot with.6 H and then reases aga with further redug of the dutane. The normalized swithg urrent of the system without any parasiti dutane is 6. Normalized Condution oss Normalized Swithg Current Parasiti ndutane (uh) Fig.. Normalized ondution loss versus Parasiti ndutane (uh) Fig. Normalized swithg urrent versus. With small amount of parasiti dutane, both ondution loss and swithg loss are redued signifiantly ompared to the system with zero dutane. n previous literature [-3], the apaitane has to be relatively large so that the time onstant of C is omparable to swithg period to keep high effiieny. n other words, the onverter s apaitane requirement is dramatially redued with small parasiti dutane.. COST COMPASON WTH TADTONA CONETE To ompare the ost of the onverter with the traditional bi-diretional boost onverter, the semiondutor A ratg and the apaitor urrent apability are ompared. Defe the semiondutor A ratg as the produt of the average urrent that flows through the devie and the maximum voltage aross it. For a traditional bi-diretional boost onverter, the sum of the A ratg of the two swithes is A *, () traditional where out is the output voltage and is the put average urrent. For the proposed onverter, there are four swithes and eah of them sustas half of the output voltage and onveys the put urrent durg half of the time, thus the total A ratg is out out A proposed 4 * * out *. (3) Therefore the total A ratgs of the semiondutors are the same for both ases. To ompare the apaitor requirement, the traditional boost onverter is assumed to be operated with duty ratio of 5%, so that the boost ratio is the same as the proposed onverter. Under this ondition, the apaitor urrent is square wave and with an rms value of half of the put urrent assumg that the put urrent is onstant for both ases. Therefore, the apaitor urrent is the same. One apaitor sustag whole output voltage is used traditional boost onverter, while apaitors eah sustag half of the output voltage are used the proposed onverter. Thus the total apaitor requirement is roughly the same. n the proposed topology, one of the apaitors is beg harged while the other is beg disharged, therefore the output voltage ripple is muh smaller than the traditional boost onverter for the same apaitane beause of the anellation of the ripple aross eah apaitor. This results lower apaitane requirement than the traditional boost onverter for the same output voltage ripple requirement.. EXPEMENTA ESUTS To verify the onept, a kw d/d onverter shown Fig. has been built. The swithes used are MOSFET module FM6TU-7A, mf film apaitors are used for both apaitors C and C. The onverter operates at 5kHz for steady state operation when outputtg, and it operates at 5 khz durg the 5-ms transition between to to limit the transient urrent. No extra dutor is used and the battery is onneted to the onverter from a foot away. Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

6 out : /div i : A/div : /div i out : 5/div Fig.. The d/d onverter module. () Transition from to out : /div : /div i : A/div i out : 5/div out : /div : /div i : A/div i out : 5/div (a) Steady state waveform when outputtg out : /div i : A/div : /div i out : 5/div (b) Steady state waveform when outputtg (d) Transition from to Fig. 3 Experimental results of the onverter, means the output voltage equals to put voltage, means the output voltage is twie of the put voltage. Fig. 3 (a) shows the put and output urrent/voltage when outputtg. Fig. 3(b) shows the same waveforms when outputtg. As an be seen from the results that the put urrent is ontuous and has exatly the same shape as depited Fig. 9. Also, it is noteworthy that the output voltage does not quite reah twie of the put voltage, whih is aused by the voltage loss aross the swithes and dead time. Fig. 3() and (d) shows the transition between and. As an be seen from the results, the urrent is well regulated durg steady state operation and well limited durg the transition. The transition time is only 5 ms. The onverter effiieny is measured at different put voltages and different powers as shown Fig. 4. As an be seen from the figure, the effiieny is quite high. The redution of the effiieny at low power is maly beause of the ontrol and gate drive power beomes signifiant terms of perentage at low power. 3 Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.

7 Effiieny (%) Effiieny (%) =3 =38 =44 = Output Power (kw) (a) when outputtg Output Power (kw) =3 =38 =44 =47.5 ACKNOWEDGMENT The authors would like to thank Dr. Haipg Xu and Ms. Wei Qian for their help measurg the onverter effiieny. EFEENCES [] Z. Pan, F. Zhang, F. Z. Peng, Power losses and effiieny analysis of multilevel DC-DC onverters, EEE Applied Power Eletronis Conferene, Marh 5, pp [] F. Zhang, F. Z. Peng, Z. Qian, Study of multilevel onverters DC-DC appliation, EEE Power Eletronis Speialists Conferene, June 4, pp [3] F. Z. Peng, F. Zhang, Z. Qian, A novel ompat DC-DC onverter for 4 systems, EEE Power Eletronis Speialists Conferene, June 3, pp [4] K. D. T. Ngo,. Webster, Steady-state analysis and design of a swithed-apaitor DC-DC onverter, EEE Transations on Aero. and Ele. Systems, vol. 3, no., pp. 9-, Jan [5] W. Harris, K. Ngo, Power swithed-apaitor DC-DC onverter, analysis, and design, EEE Transations on Aero. and Ele. Systems, vol. 33, no., pp , April 997. [6] S.. Cheong, H. Chung, A. oovii, ndutor-less DC-to-DC onverter with high power density, EEE Transations on ndustrial Eletronis, vol. 4, no., pp. 8-5, April 994. [7] F. Khan,. Tolbert, A multilevel modular apaitor lamped d/d onverter, Proeedgs of the EEE ndustry Appliations Annual Meetg, Ot. 6, pp [8] F. Zhang,. Du; F. Z. Peng, Z. Qian; A new design method for high effiieny DC-DC onverters with flyg apaitor tehnology EEE Applied Power Eletronis Conferene, Marh 6, pp [9] Ozpei, B.; Tolbert,.M.; Su, G.-J.; Du, Z.; Optimum fuel ell utilization with multilevel DC-DC onverters EEE Applied Power Eletronis Conferene, Marh 4, pp (b) when outputtg Fig. 4. Measured effiieny. CONCUSON n this paper, a multi-level d/d onversion system with multiple d soures is proposed. Ciruit analysis and ontrol are presented. The power loss of the onverter is analyzed, the analysis shows that a small amount of parasiti dutane redues the power loss dramatially and redues the apaitane requirement signifiantly. Also, the requirement of semiondutor and apaitor of the onverter is ompared with the traditional boost onverter, the omparison shows that the proposed onverter requires no more semiondutors or apaitane. Experimental results are provided to onfirm the funtionality without any extra dutors. With the help of parasiti dutane of the onnetion able, the urrent durg transition is well regulated. The requirement of the parasiti dutane an be further redued by reasg the swithg frequeny durg transition time. The high effiieny nature is proved by experimental results. This topology provides the potential for high temperature operation of d/d onverters. 4 Authorized liensed use limited to: UNESTY OF TENNESSEE. Downloaded on Marh 4, 9 at 7:55 from EEE Xplore. estritions apply.