ICL7116, ICL / 2 Digit, LCD/LED Display, A/D Converter with Display Hold. Description. Features. Ordering Information. Pinouts.

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1 SEMICONDUCTOR ICL116, ICL11 August / 2 Digit, LCD/LED Disply, A/D Converter with Disply Hold Fetures HOLD Reding Input Allows Indefinite Disply Hold Gurnteed Zero Reding for 0V Input True Polrity t Zero for Preise Null Detetion 1pA Typil Input Current Diret Disply Drive LCD ICL116 LED lcl11 Low Noise Less Thn 15µV PP (Typ) On Chip Clok nd Referene Low Power Dissiption Typilly Less Thn 10mW No Additionl Ative Ciruits Required Surfe Mount Pkge Aville Ordering Informtion PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. ICL116CPL 0 to 0 Ld PDIP E.6 ICL116CM44 0 to 0 44 Ld MQFP Q44.10x10 ICL11CPL 0 to 0 Ld PDIP E.6 Desription The Hrris ICL116 nd ICL11 re high performne, low power, 3 1 / 2 digit, A/D onverters. Inluded re seven segment deoders, disply drivers, referene, nd lok. The ICL116 is designed to interfe with liquid rystl disply (LCD) nd inludes multiplexed kplne drive. The ICL11 will diretly drive n instrument size, light emitting diode (LED) disply. The ICL116 nd ICL11 hve ll of the fetures of the ICL106 nd ICL10 with the ddition of HOLD Reding input. With this input, it is possile to mke mesurement nd retin the vlue on the disply indefinitely. To mke room for this feture the referene low input hs een onneted to Common internlly rther thn eing fully differentil. These iruits retin the ury, verstility, nd true eonomy of the ICL106 nd ICL10. They feture utozero to less thn 10µV, zero drift of less thn 1µV/ o C, input is urrent of 10pA mximum, nd roll over error of less thn one ount. The verstility of true differentil input is of prtiulr dvntge when mesuring lod ells, strin guges nd other ridgetype trnsduers. And finlly, the true eonomy of single power supply opertion (ICL116) enles high performne pnel meter to e uilt with the ddition of only eleven pssive omponents nd disply. Pinouts ICL116, ICL11 (PDIP) TOP VIEW ICL116 (MQFP) TOP VIEW HLDR D1 C V B1 4 (1 s) A1 5 (10 s) (100 s) F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E V (10 s) (100 s) NC NC NC HLDR D1 C B NC BP POL AB4 E3 F3 B3 (1000) AB4 19 (MINUS) POL 20 BP/ A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 CAUTION: These devies re sensitive to eletrostti dishrge. Users should follow proper IC Hndling Proedures. Copyright Hrris Corportion File Numer 83.1

2 ICL116, ICL11 Asolute Mximum Rtings Supply Voltge ICL116, to V V ICL11, to V ICL11, V to v Anlog Input Voltge (Either Input) (Note 1) to V Referene Input Voltge (Either Input) to V Clok Input ICL to ICL to Therml Informtion Therml Resistne (Typil, Note 2) θ JA ( o C/W) PDIP Pkge MQFP Pkge Mximum Juntion Temperture o C Mximum Storge Temperture Rnge o C to 150 o C Mximum Led Temperture (Soldering 10s) o C (MQFP Led Tips Only) Operting Conditions Temperture Rnge o C to 0 o C CAUTION: Stresses ove those listed in Asolute Mximum Rtings my use permnent dmge to the devie. This is stress only rting nd opertion of the devie t these or ny other onditions ove those indited in the opertionl setions of this speifition is not implied. NOTES: 1. Input voltges my exeed the supply voltges provided the input urrent is limited to ±100µA. 2. θ JA is mesured with the omponent mounted on n evlution PC ord in free ir. Eletril Speifitions (Note 3) T A = o C, f CLOCK = 48kHz, V REF = 100mV PARAMETER CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Zero Input Reding V IN = 0V, Full Sle = 200mV ± Digitl Reding Rtiometri Reding V ln = V REF, V REF = 100mV / 1000 Rollover Error V IN = V ln 195mV Differene in Reding for Equl Positive nd Negtive Inputs Ner Full Sle Linerity Full Sle = 200mV or Full Sle = 2V Mximum Devition from Best Stright Line Fit (Note 5) 1000 Digitl Reding ±0.2 ±1 Counts ±0.2 ±1 Counts Common Mode Rejetion Rtio V CM = ±1V, V IN = 0V, Full Sle = 200mV (Note 5) 50 µv/v Noise V IN = 0V, Full Sle = 200mV (PekToPek Vlue 15 µv Not Exeeded 95% of Time) (Note 5) Lekge Current Input V ln = 0 (Note 5) 1 10 pa Zero Reding Drift V ln = 0, 0 o C To 0 o C (Note 5) µv/ o C Sle Ftor Temperture Coeffiient V IN = 199mV, 0 o C To 0 o C (Note 5) 1 5 ppm/ o C Supply Current V IN = 0 (Does Not Inlude LED Current for ICL11) ma V Supply Current ICL11 Only ma Pin Anlog Common Voltge kω Between Common nd Positive Supply (With V Respet to Supply) Temperture Coeffiient of Anlog Common kω Between Common nd Positive Supply (With 80 ppm/ o C Respet to Supply) (Note 5) DISPLAY DRIVER (ICL116 ONLY) PekToPek Segment Drive Voltge = to V = 9V, (Note 4) V PekToPek Bkplne Drive Voltge DISPLAY DRIVER (ICL11 ONLY) Segment Sinking Current = 5V, Segment Voltge = 3V (Exept Pins 19 nd 20) 5 8 ma Pin 19 Only ma Pin 20 Only 4 ma NOTES: 3. Unless otherwise noted, speifitions pply to oth the ICL116 nd ICL11. ICL116 is tested in the iruit of Figure 1. ICL11 is tested in the iruit of Figure Bk plne drive is in phse with segment drive for off segment, 180 degrees out of phse for on segment. Frequeny is 20 times onversion rte. Averge DC omponent is less thn 50mV. 5. Not tested, gurnteed y design. 3

3 Typil Applitions nd Test Ciruits ICL116, ICL11 R3 C 4 R 1 R 5 IN 9V R 4 C 5 C R 2 2 C 3 C 1 2 COM V DISPLAY BP C 1 = 0.1µF C 2 = 0.4µF C 3 = µf C 4 = 100pF C 5 = 0.01µF R 1 = kω R 2 = 4kΩ R 3 = 100kΩ R 4 = 1kΩ R 5 = 1MΩ ICL HLDR D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL DISPLAY FIGURE 1. ICL116 CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE TP 5 R 3 5V 5V IN R 5 R 1 TP 1 TP 2 TP 3 C 4 R 4 C 5 C R 2 2 C 3 C 1 TP 4 DISPLAY R 6 TO DECIMAL PO C 1 = 0.1µF C 2 = 0.4µF C 3 = µf C 4 = 100pF C 5 = 0.01µF R 1 = kω R 2 = 4kΩ R 3 = 100kΩ R 4 = 1kΩ R 5 = 1MΩ R 6 = 150Ω HLDR D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL COM V 2 ICL11 DISPLAY FIGURE 2. ICL11 CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 3

4 ICL116, ICL11 Design Informtion Summry Sheet OSCILLATOR FREQUENCY f OSC = 0.45/RC C OSC > 50pF; R OSC > 50kΩ f OSC (Typ) = 48kHz OSCILLATOR PERIOD t OSC = RC/0.45 EGRATION CLOCK FREQUENCY f CLOCK = f OSC /4 EGRATION PERIOD t = 1000 x (4/f OSC ) 60/50Hz REJECTION CRITERION t /t 60Hz or t lnt /t 50Hz = Integer OPTIMUM EGRATION CURRENT I = 4µA FULL SCALE ANALOG INPUT VOLTAGE V lnfs (Typ) = 200mV or 2V EGRATE RESISTOR V INFS R = I EGRATE CAPACITOR ( t )( I ) C = V EGRATOR OUTPUT VOLTAGE SWING ( t )( I ) V = C V MAXIMUM SWING: (V 1.0V) < V < ( 0.5V), V (Typ) = 2V DISPLAY COUNT V IN COUNT = 1000 V REF CONVERSION CYCLE t CYC = t CL0CK x 00 t CYC = t OSC x 16,000 when f OSC = 48KHz; t CYC = 3ms MODE INPUT VOLTAGE (V 1V) < V ln < ( 0.5V) AUTOZERO CAPACITOR 0.01µF < C AZ < 1µF REFERENCE CAPACITOR 0.1µF < < 1µF V COM Bised etween nd V. V COM 2.8V Regultion lost when to V < 6.8V. If V COM is externlly pulled down to (V to V )/2, the V COM iruit will turn off. ICL116 POWER SUPPLY: SINGLE 9V V = 9V Digitl supply is generted internlly V 4.5V ICL116 DISPLAY: LCD Type: Diret drive with digitl logi supply mplitude. ICL11 POWER SUPPLY: DUAL ±5.0V = 5V to V = 5V to Digitl Logi nd LED driver supply to ICL11 DISPLAY: LED Type: NonMultiplexed Common Anode Typil Integrtor Amplifier Output Wveform ( Pin) AUTO ZERO PHASE (COUNTS) SIGNAL EGRATE PHASE FIXED 1000 COUNTS DEEGRATE PHASE COUNTS TOTAL CONVERSION TIME = 00 x t CLOCK = 16,000 x t OSC 3

5 ICL116, ICL11 Pin Desriptions PIN NUMBER PIN DIP 44 PIN FLATPACK NAME FUNCTION DESCRIPTION 1 8 HLDR Input Disply Hold Control. 2 9 D1 Output Driver Pin for Segment D of the disply units digit C1 Output Driver Pin for Segment C of the disply units digit B1 Output Driver Pin for Segment B of the disply units digit A1 Output Driver Pin for Segment A of the disply units digit F1 Output Driver Pin for Segment F of the disply units digit. 14 G1 Output Driver Pin for Segment G of the disply units digit E1 Output Driver Pin for Segment E of the disply units digit D2 Output Driver Pin for Segment D of the disply tens digit C2 Output Driver Pin for Segment C of the disply tens digit B2 Output Driver Pin for Segment B of the disply tens digit A2 Output Driver Pin for Segment A of the disply tens digit F2 Output Driver Pin for Segment F of the disply tens digit. 14 E2 Output Driver Pin for Segment E of the disply tens digit. 15 D3 Output Driver pin for segment D of the disply hundreds digit. 16 B3 Output Driver pin for segment B of the disply hundreds digit. 1 F3 Output Driver pin for segment F of the disply hundreds digit. 18 E3 Output Driver pin for segment E of the disply hundreds digit. 19 AB4 Output Driver pin for oth A nd B segments of the disply thousnds digit POL Output Driver pin for the negtive sign of the disply. BP/ Output Driver pin for the LCD kplne/power Supply Ground. Output Driver pin for segment G of the disply hundreds digit. Output Driver pin for segment A of the disply hundreds digit. Output Driver pin for segment C of the disply hundreds digit. Output Driver pin for segment G of the disply tens digit. V Supply Negtive power supply. 2 Output Integrtor mplifier output. To e onneted to integrting pitor. Output Input uffer mplifier output. To e onneted to integrting resistor. Input Integrtor mplifier input. To e onneted to utozero pitor. Input Supply/ Output Supply Differentil inputs. To e onneted to input voltge to e mesured. LO nd HI designtors re for referene nd do not imply tht LO should e onneted to lower potentil, e.g., for negtive inputs hs higher potentil thn. Internl voltge referene output. Connetion pins for referene pitor. Power Supply. 3 Input Disply test. Turns on ll segments when tied to. 4 6 OS OSC2 OSC1 Output Output Input Devie lok genertor iruit onnetion pins. 3

6 ICL116, ICL11 Detiled Desription Anlog Setion Figure 3 shows the Anlog Setion for the ICL116 nd ICL11. Eh mesurement yle is divided into three phses. They re (1) utozero (), (2) signl integrte () nd (3) deintegrte (DE). AutoZero Phse During utozero three things hppen. First, input high nd low re disonneted from the pins nd internlly shorted to nlog. Seond, the referene pitor is hrged to the referene voltge. Third, feedk loop is losed round the system to hrge the utozero pitor C AZ to ompenste for offset voltges in the uffer mplifier, integrtor, nd omprtor. Sine the omprtor is inluded in the loop, the ury is limited only y the noise of the system. In ny se, the offset referred to the input is less thn 10µV. Signl Integrte Phse During signl integrte, the utozero loop is opened, the internl short is removed, nd the internl input high nd low re onneted to the externl pins. The onverter then integrtes the differentil voltge etween nd for fixed time. This differentil voltge n e within wide ommon mode rnge: up to 1V from either supply. If, on the other hnd, the input signl hs no return with respet to the onverter power supply, n e tied to nlog to estlish the orret ommon mode voltge. At the end of this phse, the polrity of the integrted signl is determined. DeIntegrte Phse The finl phse is deintegrte, or referene integrte. Input low is internlly onneted to nlog nd input high is onneted ross the previously hrged referene pitor. Ciruitry within the hip ensures tht the pitor will e onneted with the orret polrity to use the integrtor output to return to zero. The time required for the output to return to zero is proportionl to the input signl. Speifilly the digitl reding displyed is: V IN DISPLAY COUNT = V REF Differentil Input The input n ept differentil voltges nywhere within the ommon mode rnge of the input mplifier, or speifilly from 0.5V elow the positive supply to 1V ove the negtive supply. In this rnge, the system hs CMRR of 86dB typil. However, re must e exerised to ssure the integrtor output does not sturte. A worst se ondition would e lrge positive ommon mode voltge with ner full sle negtive differentil input voltge. The negtive input signl drives the integrtor positive when most of its swing hs een used up y the positive ommon mode voltge. For these ritil pplitions the integrtor output swing n e redued to less thn the reommended 2V full sle swing with little loss of ury. The integrtor output n swing to within 0.5V of either supply without loss of linerity. Differentil Referene The referene voltge n e generted nywhere within the power supply voltge of the onverter. The min soure of ommon mode error is rollover voltge used y the referene pitor losing or gining hrge to stry pity on its nodes. If there is lrge ommon mode voltge, the referene pitor n gin hrge (inrese voltge) when lled up to deintegrte positive signl ut lose hrge (derese voltge) when lled up to deintegrte negtive input signl. This differene in referene for positive or negtive input voltge will give rollover error. However, y seleting the referene pitor suh tht it is lrge enough in omprison to the stry pitne, this error n e held to less thn 0.5 ount worst se. (See Component Vlue Seletion.) STRAY STRAY R C AZ C ER 2 10µA 2.8V EGRATOR TO DIGITAL SECTION DE DE INPUT HIGH 6.2V DE DE AND DE(±) N V INPUT LOW COMPARATOR FIGURE 3. ANALOG SECTION OF ICL116 AND ICL11 3

7 ICL116, ICL11 Anlog This pin is inluded primrily to set the ommon mode voltge for ttery opertion (ICL116) or for ny system where the input signls re floting with respet to the power supply. The pin sets voltge tht is pproximtely 2.8V less thn the positive supply. This is seleted to give minimum endoflife ttery voltge of out 6.8V. However, nlog hs some of the ttriutes of referene voltge. When the totl supply voltge is lrge enough to use the zener to regulte (>6.8V), the COM MON voltge will hve low voltge oeffiient (0.001%/V), low output impedne ( 15Ω), nd temperture oeffiient typilly less thn 80ppm/ o C. The limittions of the on hip referene should lso e reognized, however. With the ICL11, the internl heting whih results from the LED drivers n use some degrdtion in performne. Due to their higher therml resistne, plsti prts re poorer in this respet thn ermi. The omintion of referene Temperture Coeffiient (TC), internl hip dissiption, nd pkge therml resistne n inrese noise ner full sle from µv to 80µV PP. Also the linerity in going from high dissiption ount suh s 1000 (20 segments on) to low dissiption ount suh s 1111 (8 segments on) n suffer y ount or more. Devies with positive TC referene my require severl ounts to pull out of n overrnge ondition. This is euse overrnge is low dissiption mode, with the three lest signifint digits lnked. Similrly, units with negtive TC my yle etween over rnge nd nonover rnge ount s the die lterntely hets nd ools. All these prolems re of ourse eliminted if n externl referene is used. The ICL116, with its negligile dissiption, suffers from none of these prolems. In either se, n externl referene n esily e dded, s shown in Figure 4. Anlog is lso used s the input low return during utozero nd deintegrte. If is different from nlog, ommon mode voltge exists in the system nd is tken re of y the exellent CMRR of the onverter. However, in some pplitions will e set t fixed known voltge (power supply ommon for instne). In this pplition, nlog should e tied to the sme point, thus removing the ommon mode voltge from the onverter. The sme holds true for the referene voltge. If referene n e onveniently tied to nlog, it should e sine this removes the ommon mode voltge from the referene system. Within the lc, nlog is tied to n NChnnel FET tht n sink pproximtely ma of urrent to hold the voltge 2.8V elow the positive supply (when lod is trying to pull the ommon line positive). However, there is only 10µA of soure urrent, so my esily e tied to more negtive voltge thus overriding the internl referene. V ICL116 ICL11 V ICL116 ICL11 FIGURE 4A. FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE The pin serves two funtions. On the ICL116 it is oupled to the internlly generted digitl supply through 500Ω resistor. Thus it n e used s the negtive supply for externlly generted segment drivers suh s deiml points or ny other nnunitor the user my wnt to inlude on the LCD disply. Figures 5 nd 6 show suh n pplition. No more thn 1mA lod should e pplied. ICL116 BP 20kΩ The seond funtion is lmp test. When is pulled high (to ) ll segments will e turned on nd the disply should red The pin will sink out 5mA under these onditions. V 1MΩ 6.8V ZENER I Z 6.8kΩ ICL V REFERENCE TO LCD DECIMAL PO TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL PO CAUTION: On the ICL116, in the lmp test mode, the segments hve onstnt DC voltge (no squrewve) nd my urn the LCD disply if left in this mode for severl minutes. 3

8 ICL116, ICL11 ICL116 BP HOLD Reding Input DECIMAL PO SELECT CD The HLDR input will prevent the lth from eing updted when this input is t logi 1. The hip will ontinue to mke A/D onversions, however, the results will not e updted to the internl lthes until this input goes low. This input n e left open or onneted to (ICL116) or GROUND (ICL11) to ontinuously updte the disply. This input is CMOS omptile, nd hs 0kΩ (See Figure ) typil resistne to either (ICL116) or GROUND (ICL11). TO LCD DECIMAL POS FIGURE 6. EXCLUSIVE OR GATE FOR DECIMAL PO DRIVE Digitl Setion Figures nd 8 show the digitl setion for the ICL116 nd ICL11, respetively. In the ICL116, n internl digitl ground is generted from 6V Zener diode nd lrge PChnnel soure follower. This supply is mde stiff to sor the reltive lrge pitive urrents when the k plne (BP) voltge is swithed. The BP frequeny is the lok frequeny divided y 800. For three redings/seond this is 60Hz squre wve with nominl mplitude of 5V. The segments re driven t the sme frequeny nd mplitude nd re in phse with BP when OFF, ut out of phse when ON. In ll ses negligile DC voltge exists ross the segments. Figure 8 is the Digitl Setion of the ICL11. It is identil to the ICL116 exept tht the regulted supply nd k plne drive hve een eliminted nd the segment drive hs een inresed from 2mA to 8mA, typil for instrument size ommon node LED displys. Sine the 1000 output (pin 19) must sink urrent from two LED segments, it hs twie the drive pility or 16mA. In oth devies, the polrity indition is on for negtive nlog inputs. If nd re reversed, this indition n e reversed lso, if desired. e f g d e f g d e f g d BACKPLANE LCD PHASE DRIVER TYPICAL OUTPUT 0.5mA 2mA OUTPUT ERNAL DIGITAL GROUND DECODE LATCH DECODE DECODE 1000 s 100 s 10 s 1 s COUNTER COUNTER COUNTER COUNTER 200 THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 4 ERNAL DIGITAL GROUND LOGIC CONTROL 0kΩ V TH = 1V 6.2V 500Ω 1 V HLDR FIGURE. ICL116 DIGITAL SECTION 3

9 ICL116, ICL11 e f g d e f g d e f g d DECODE DECODE DECODE TYPICAL OUTPUT LATCH 0.5mA 8mA TO 1000 s 100 s 10 s 1 s COUNTER COUNTER COUNTER COUNTER DIGITAL GROUND THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 4 LOGIC CONTROL 1 0kΩ 500Ω DIGITAL GROUND HLDR FIGURE 8. ICL11 DIGITAL SECTION System Timing Figure 9 shows the loking rrngement used in the ICL116 nd ICL11. Two si loking rrngements n e used: ERNAL TO PART 4 CLOCK 1. Figure 9A, n externl osilltor onneted to pin. 2. Figure 9B, n RC osilltor using ll three pins. The osilltor frequeny is divided y four efore it loks the dede ounters. It is then further divided to form the three onvertyle phses. These re signl integrte (1000 ounts), referene deintegrte (0 to 2000 ounts) nd utozero (1000 ounts to 00 ounts). For signls less thn full sle, utozero gets the unused portion of referene deintegrte. This mkes omplete mesure yle of 4,000 ounts (16,000 lok pulses) independent of input voltge. For three redings/seond, n osilltor frequeny of 48kHz would e used. To hieve mximum rejetion of 60Hz pikup, the signl integrte yle should e multiple of 60Hz. Osilltor frequenies of 0kHz, 120kHz, 80kHz, 60kHz, 48kHz, khz, 1 / 3 khz, et. should e seleted. For 50Hz rejetion, Osilltor frequenies of 200kHz, 100kHz, 66 2 / 3 khz, 50kHz, khz, et. would e suitle. Note tht khz (2.5 redings/seond) will rejet oth 50Hz nd 60Hz (lso 0Hz nd 4Hz). ICL11 ICL116 FIGURE 9A. EXTERNAL OSCILLATOR ERNAL TO PART 4 R C FIGURE 9B. RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS CLOCK 3

10 ICL116, ICL11 Component Vlue Seletion Integrting Resistor Both the uffer mplifier nd the integrtor hve lss A output stge with 100µA of quiesent urrent. They n supply 4µA of drive urrent with negligile nonlinerity. The integrting resistor should e lrge enough to remin in this very liner region over the input voltge rnge, ut smll enough tht undue lekge requirements re not pled on the PC ord. For 2V full sle, kω is ner optimum nd similrly 4kΩ for 200mV sle. Integrting Cpitor The integrting pitor should e seleted to give the mximum voltge swing tht ensures tolerne uildup will not sturte the integrtor swing (pproximtely. 0.5V from either supply). In the ICL116 or the ICL11, when the nlog is used s referene, nominl 2V fullsle integrtor swing is fine. For the ICL11 with 5V supplies nd nlog tied to supply ground, ±3.5V to 4V swing is nominl. For three redings/seond (48kHz lok) nominl vlues for C lnt re 0.µF nd 0.1µF, respetively. Of ourse, if different osilltor frequenies re used, these vlues should e hnged in inverse proportion to mintin the sme output swing. An dditionl requirement of the integrting pitor is tht it must hve low dieletri sorption to prevent rollover errors. While other types of pitors re dequte for this pplition, polypropylene pitors give undetetle errors t resonle ost. AutoZero Cpitor The size of the utozero pitor hs some influene on the noise of the system. For 200mV full sle where noise is very importnt, 0.4µF pitor is reommended. On the 2V sle, 0.04µF pitor inreses the speed of reovery from overlod nd is dequte for noise on this sle. Referene Cpitor A 0.1µF pitor gives good results in most pplitions. Generlly 1µF will hold the rollover error to 0.5 ounts in this instne. Osilltor Components For ll rnges of frequeny 100kΩ resistor is reommended nd the pitor is seleted from the eqution: 0.45 f = For 48kHz Clok (3 Redings/se), C = 100pF. RC Referene Voltge The nlog input required to generte full sle output (2000 ounts) is: V ln = 2V REF. Thus, for the 200mV nd 2V sle, V REF should equl 100mV nd 1V, respetively. However, in mny pplitions where the A/D is onneted to trnsduer, there will exist sle ftor other thn unity etween the input voltge nd the digitl reding. For instne, in weighing system, the designer might like to hve full sle reding when the voltge from the trnsduer is 0.682V. Insted of dividing the input down to 200mV, the designer should use the input voltge diretly nd selet V REF = 0.1V. Suitle vlues for integrting resistor nd pitor would e 120kΩ nd 0.µF. This mkes the system slightly quieter nd lso voids divider network on the input. The ICL11 with ±5V supplies n ept input signls up to ±4V. Another dvntge of this system ours when digitl reding of zero is desired for V IN 0. Temperture nd weighing systems with vrile fre re exmples. This offset reding n e onveniently generted y onneting the voltge trnsduer etween IN HI nd nd the vrile (or fixed) offset voltge etween nd. ICL11 Power Supplies 3. The ICL11 is designed to work from ±5V supplies. However, if negtive supply is not ville, it n e generted from the lok output with 2 diodes, 2 pitors, nd n inexpensive lc. Figure 10 shows this pplition. See ICL660 dt sheet for n lterntive. ICL11 V V = 3.3V CD09 IN µf IN914 FIGURE 10. GENERATING NEGATIVE SUPPLY FROM 5V In ft, in seleted pplitions no negtive supply is required. The onditions to use single 5V supply re: 1. The input signl n e referened to the enter of the ommon mode rnge of the onverter. 2. The signl is less thn ±1.5V. 3. An externl referene is used. 10 µf 3

11 ICL116, ICL11 Typil Applitions The ICL116 nd ICL11 my e used in wide vriety of onfigurtions. The iruits whih follow show some of the possiilities, nd serve to illustrte the exeptionl verstility of these A/D onverters. The following pplition notes ontin very useful informtion on understnding nd pplying this prt nd re ville from Hrris semiondutor. Applition Notes NOTE # DESCRIPTION AnswerFAX DOC. # AN016 Seleting A/D Converters 9016 AN01 The Integrting A/D Converter 901 AN018 Do s nd Don ts of Applying A/D Converters 9018 AN0 Low Cost Digitl Pnel Meter Designs 90 AN0 AN046 AN04 AN052 Understnding the AutoZero nd Common Mode Performne of the ICL1//9 Fmily Building BtteryOperted Auto Rnging DVM with the ICL106 Gmes People Ply with Hrris A/D Converters, edited y Peter Brdshw Tips for Using Single Chip 3 1 / 2 Digit A/D Converters Typil Applitions 100kΩ 100kΩ 100pF SET V REF = 100mV 100pF SET V REF = 100mV 0.1µF 1kΩ kω 0.1µF 1kΩ kω 5V V 2 0.4µF 0.µF 4kΩ 1MΩ 0.01µF IN 9V V 2 0.4µF 4kΩ 0.µF 1MΩ 0.01µF IN 5V TO DISPLAY TO DISPLAY BP TO BACKPLANE Vlues shown re for 200mV full sle, 3 redings/se., floting supply voltge (9V ttery). FIGURE 11. ICL116 USING THE ERNAL REFERENCE Vlues shown re for 200mV full sle, 3 redings/se. my e tied to either for inputs floting with respet to supplies, or for single ended inputs. (See disussion under Anlog.) FIGURE 12. ICL11 USING THE ERNAL REFERENCE 3

12 ICL116, ICL11 Typil Applitions (Continued) 100kΩ 100kΩ 100pF SET V REF = 1.000V 100pF SET V REF = 100mV 0.1µF kω kω 0.1µF 1kΩ 10kΩ 15kΩ 1.2V (ICL8069) 5V 0.04µF kω 1MΩ 0.01µF IN 0.4µF 4kΩ 1MΩ 0.01µF IN V 2 0.µF V V 2 0.µF TO DISPLAY TO DISPLAY An externl referene must e used in this pplition, sine the voltge etween nd V is insuffiient for orret opertion of the internl referene. FIGURE 13. ICL116 AND ICL11: RECOMMENDED COMPONENT VALUES FOR 2.0V FULL SCALE FIGURE 14. ICL11 OPERATED FROM SINGLE 5V SUPPLY 100kΩ 100kΩ 100pF 100pF SCALE FACTOR ADJUST 0.1µF 0.4µF 4kΩ 0.1µF 0.01µF 100kΩ 1MΩ 100kΩ 0kΩ 0.4µF 4kΩ ZERO ADJUST 9V kω SILICON NPN MPS 04 OR SIMILAR V 2 0.µF V V 2 0.µF TO DISPLAY TO DISPLAY BP TO BACKPLANE The resistor vlues within the ridge re determined y the desired sensitivity. FIGURE 15. ICL11 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL A silion diodeonneted trnsistor hs temperture oeffiient of out 2mV/ o C. Clirtion is hieved y pling the sensing trnsistor in ie wter nd djusting the zeroing potentiometer for reding. The sensor should then e pled in oiling wter nd the sleftor potentiometer djusted for reding. FIGURE 16. ICL116 USED AS A DIGITAL CENTIGRADE THERMOMETER 3