# V O = a(v I - V B ) (EQ. 10) V B = V O Z 1 / (Z 1 + Z 2 ), I B = 0 (EQ. 11) V O = av I - az 1 V O / (Z 1 + Z 2 ) (EQ. 12)

Size: px
Start display at page:

Download "V O = a(v I - V B ) (EQ. 10) V B = V O Z 1 / (Z 1 + Z 2 ), I B = 0 (EQ. 11) V O = av I - az 1 V O / (Z 1 + Z 2 ) (EQ. 12)"

Transcription

1 APPLICATION NOTE Feedbck, Op Amps nd AN9415 Rev Introduction There re mny benefits [1] which result from the use of feedbck in electronic circuits, but the drwbcks re the incresed complexity of the clcultions nd the opportunity for the resulting circuit to ring or oscillte. This pper employs grphicl techniques to simplify stbility clcultions, thus enbling the designer to chieve stble, well behved circuit which meets ll resonble performnce criteri. Now the designer cn obtin the dvntges of feedbck without worrying bout ringing or oscilltion. Development of the Generl Feedbck Eqution Referring to the block digrm shown in Figure 1, Eqution 1, Eqution 2 nd Eqution 3 cn be written by inspection if it is ssumed tht there re no loding concerns between the blocks. The no loding ssumption is implicit in ll block digrm clcultions, nd this requires tht the output impednce of block be much lower thn the input impednce of the block it is driving. This is usully true by one or two orders of mgnitude. Algebric mnipultion of Eqution 1, Eqution 2 nd Eqution 3 yield Eqution 4 nd Eqution 5 which re the defining equtions for feedbck system. = EA (EQ. 1) E = (EQ. 2) E = /A (EQ. 3) / = A/(1 + A) (EQ. 4) E / = 1/(1 + A) (EQ. 5) E FIGURE 1. FEEDBACK SYSTEM BLOCK DIAGRAM The prmeter A, which usully includes the mplifier nd thus contins ctive elements, is clled the direct gin in this nlysis. The prmeter, which normlly contins only pssive components, is clled the feedbck fctor. Notice tht in Eqution 4 s the vlue of A pproches infinity, the quntity A, which is clled the loop gin, becomes much lrger thn one; thus, Eqution 4 cn be pproximted by Eqution 6. / is clled the closed loop gin, nd since the direct gin, or the mplifier response, is not included, the eqution for the closed loop gin it is independent of mplifier prmeter chnges. This is the mjor benefit of feedbck circuits. / = 1/ for A >> 1 (EQ. 6) A Eqution 4 is dequte to describe the stbility of ny feedbck circuit becuse ll feedbck circuits cn be reduced to the this form through block digrm reduction techniques [2]. The stbility of the feedbck circuit is determined by setting the denomintor of Eqution 4 equl to zero. 1 + A = 0 (EQ. 7) A = 1 = 1 / 180 (EQ. 8) Referring to Eqution 4 nd Eqution 8, it is observed tht if the mgnitude of the loop gin, A, cn chieve one while the phse equls 180 degrees, the closed loop gin becomes infinity becuse of division by zero. Since this stte is unstble, the circuit will oscillte, nd it will oscillte t the frequency where the phse shift equls to 180 degrees. If the loop gin t the frequency of oscilltion is slightly greter thn one it will be reduced to one by the reduction in gin suffered by the ctive elements s they pproch the limits of sturtion, but if the vlue of A is much greter thn one, gross nonlinerities cn occur nd the circuit my then cycle between sturtion limits. Preventing instbility is the essence of feedbck circuit design, thus this topic will be touched lightly here nd covered in detil lter. A good strting point for discussing stbility is finding n esy method to clculte it. Figure 2 shows tht the loop gin, A, cn be clculted from block digrm by opening current inputs, shorting voltge inputs, breking the loop nd clculting the response to test input signl. V TO / V TI = A (EQ. 9) The block digrm techniques cn be pplied to op mps thus reducing the stbility nlysis to simple tsk. The schemtic for noninverting mplifier is shown in Figure 3, nd the block digrm equivlent is shown in Figure 4. Eqution 10 nd Eqution 11 re combined to yield Eqution 12 which describes the block digrm shown in Figure 4A, while block digrm trnsformtions [3] re employed to get to Figure 4B. V TO V TI FIGURE 2. BLOCK DIAGRAM FOR COMPUTING THE LOOP GAIN = ( V B ) (EQ. 10) V B = Z 1 / (Z 1 + Z 2 ), I B = 0 (EQ. 11) = Z 1 / (Z 1 + Z 2 ) (EQ. 12) A AN9415 Rev Pge 1 of 13

2 V A + Z 2 + V TO V TI Z 2 V TI Z 1 /(Z 1 + Z 2 ) V B Z 1 V TI Z 1 FIGURE 3. NONINVERTING CIRCUIT The block digrm shown in Figure 4A is written by inspection of Eqution 12. The block digrm shown in Figure 4B is derived from Figure 4A by block digrm mnipultions. Eqution 13 is derived from Eqution 12 by lgebric mnipultion, or it cn be written by inspection of Figure 4B becuse the system is shown in stndrd form. V A Z 1 /(Z 1 + Z 2 ) FIGURE 4A. BLOCK DIAGRAM AS WRITTEN FROM EQUATION 12 V B FIGURE 5. NONINVERTING OP AMP WITH INPUT GROUNDED AND FEEDBACK LOOP BROKEN V TO Z 1 = = A V TI Z 1 + Z 2 (EQ. 14) Referring to the inverting op mp configurtion shown in Figure 6, the nlysis will be performed by working from the mplifier circuit to the block digrm. The closed loop gin equtions re derived in references one nd six s well s most electronic text books. The closed loop gin which is equl to 1/ is known to be Z 2 /Z 1 ; thus, is clculted s Z 1 /Z 2 with the minus sign indicting negtive input. Referring to Figure 6, if is set to zero nd the loop is broken t the negtive input to the op mp the circuit is identicl to tht shown in Figure 5. + V Z Z I 1 V A 2 Z 1 /(Z 1 + Z 2 ) FIGURE 4B. AFTER BLOCK DIAGRAM MANIPULATION FIGURE 4. BLOCK DIAGRAM OF THE NONINVERTING OP AMP AS SHOWN IN EQUATION 12 / = /(1 + Z 1 / (Z 1 + Z 2 )) (EQ. 13) FIGURE 6. INVERTING OP AMP SCHEMATIC An exmintion of Figure 5 nd Figure 6 revels tht the loop gin, A, is identicl for both the inverting nd noninverting circuit configurtions. The loop gin is the only prmeter tht determines stbility, nd it is not function of the loction of the inputs. Hence the loop gin for the inverting op mp is given to us by Eqution 14. Now tht A nd 1/ re both known, A cn be determined by multipliction to be Z 2 /(Z 1 + Z 2 ). Since the direct gin nd the loop gin re both known Figure 7 cn be constructed from these quntities. The loop gin, A, is equl to Z 1 /(Z 1 +Z 2 ), the closed loop gin, 1/, is equl to (Z 1 +Z 2 )/Z 1, nd the direct gin, A, is equl to the op mp gin,. The loop gin cn be determined from Figure 4B by inspection, or if the system block is not vilble the loop gin cn be obtined directly from the mplifier schemtic s shown in Figure 5. First set voltge sources to zero by grounding them, then open current sources, brek the feedbck loop t ny convenient plce nd then clculte the loop gin. Remember, the output impednce of the op mp must be much lower thn the feedbck impednce so tht block digrm techniques cn be used. The test input is V TI, nd it is mplified by the op mp gin,. The op mp output, V TI is divided by before it is fed bck s V TO. Z 2 /(Z 1 + Z 2 ) Z 1 /Z 2 FIGURE 7. BLOCK DIAGRAM OF THE INVERTING OP AMP Eqution 15, which is the closed loop gin eqution for n inverting op mp cn be written directly from Figure 7. As () pproches infinity in Eqution 15, the closed loop gin pproches Z 2 /Z 1. V A AN9415 Rev Pge 2 of 13

3 Z 2 Z 1 + Z 2 = Z Z 1 + Z 2 (EQ. 15) The closed loop gin for the noninverting circuit, / = (Z 1 + Z 2 ) / Z 1, is different from the closed loop gin for the inverting circuit, / = Z 2 / Z 1. It will lwys be the cse tht the loop gin, hence the stbility, is independent of the loction of the inputs, but the closed loop performnce is highly dependent on the plcement of the input. Mny circuits tke dvntge of this phenomen to gin better performnce s will be shown in the benefits section. A NON INV = ; which is to A INV = Z 2 / (Z 1 + Z 2 ) (EQ. 16) Compring the block digrms of the noninverting nd inverting circuits revels tht their direct gins re different, nd this explins why there re some slight performnce differences between the configurtions. The noninverting circuit with the higher direct gin hs less closed loop error; t closed loop gin of 2 for both circuits the noninverting circuit hs 3.5 more loop gin. The inverting circuit is more stble for the sme mgnitude of closed loop gin; i.e., for closed loop gin of 2, A INV = 0.33 nd A NONINV = 0.5. Normlly these differences re minor, but they re pointed out becuse they my be tken dvntge of or they cn cuse very subtle problems in unique situtions. There re mny other op mp circuit configurtions, but they will ll reduce to these two bsic forms; ech of which is vrition of the bsic feedbck circuit shown in Figure 1. Letting Z 1 nd or Z 2 equl vrious combintions of RLCs will give different closed loop performnce, but the nlysis techniques remin the sme. More complicted circuit configurtions cn ll be reduced to these simple circuits through block digrm reduction techniques nd superposition. Benefits of Feedbck The tolernces nd drift coefficients of pssive components re much less thn those ssocited with ctive components. If the circuit trnsfer function cn be mde to be dependent only on the pssive component prmeters it will be much more stble circuit; feedbck ccomplishes this through the direct gin s shown here. Differentiting the closed loop Eqution 4, with respect to the direct gin yields Equtions 17 nd Eqution 18 shown below. Notice tht the percentge chnge in the closed loop gin is the percentge chnge in the direct gin divided by the loop gin. Thus for very high loop gins the initil ccurcy nd drift will be function of the pssive components rther thn of the direct or mplifier gin. Although the feedbck reduces the gin errors, other mplifier errors such s input voltge offset re not ffected by the feedbck becuse they occur s n input rther thn within the feedbck loop. d / da 1 1 ³/ = 1 + A 2 = 1 + A A (EQ. 17) d / da 1 = / A 1 + A (EQ. 18) All mplifiers hve noise nd distortion chrcteristics ssocited with them, nd low noise or low distortion mplifiers commnd premium price. Very often feedbck cn be used t no cost increse to reduce the effects of distortion nd noise. Both closed loop nd open loop systems re shown in Figure 8 nd Figure 9; notice tht both systems hve the sme number of components except for the pssive feedbck elements. V 0 V 1 V 2 A 1 A 2 FIGURE 8. CLOSED LOOP SYSTEM V 0 V 1 V 2 A 1 A 2 FIGURE 9. OPEN LOOP SYSTEM Eqution 19 nd Eqution 20 re derived from the closed loop nd open loop systems shown in Figure 8 nd Figure 9. If Eqution 19 is rewritten s shown in Eqution 21 it is obvious tht Eqution 22 results when the quntity A 1 A 2 pproches infinity s it will in n idel system. A 1 A 2 + V 0 A 2 V 1 V 2 = A 1 A 2 1+ A 1 A A 1 A 2 = A 1 A 2 + V 0 + A 2 V 1 + V 2 + V 0 V 1 /A 1 V 2 /A 1 A 2 = 1 A 1 A A 1 A A 1 A V 0 V 1 /A 1 = + (EQ. 19) (EQ. 20) (EQ. 21) For A 1 A 2 pproching infinity (EQ. 22) Now let V 0 nd V 1 represent the mplifier s internl noise referred to the input, nd let V 2 represent the noise from the ny other system components. Notice from Eqution 22 tht in the closed loop system V 2 hs disppered, V 1 is decresed proportionl to the gin A 1 nd tht the input noise hs only been multiplied by the closed loop gin, 1/. Conversely, Eqution 20 indictes tht in the open loop system the input noise hs been multiplied by A 1 A 2 (which would be equivlent to the closed loop gin), tht V 1 is multiplied by A 2 nd tht V 2 is present. The feedbck in the closed loop system hs drmticlly reduced the noise from the sources which follow the mplifier A 1 so this cn become big design dvntge. In the closed loop system the mplifier A 1 should be selected for it s AN9415 Rev Pge 3 of 13

4 excellent noise performnce, but the mplifier A 2 cn be selected bsed on some other criteri such s cost. This option is not vilble in the open loop system. Very often when driving low impednces like spekers, the output mplifiers re driven s close to the power supply rils s possible to obtin the mximum dynmic rnge. One result of this prctice is tht some distortion of the signl occurs s ctive device prmeters re driven so tht they become nonliner. This nd most other sources of distortion usully occur in the output stges of the mplifier. Becuse the distortion occurs t the output it cn be represented by V 2 in Eqution 19, nd this quntity goes to zero s the direct gin pproches infinity, so it is essentilly eliminted by feedbck. The connection from the speker driver output to the premplifier input in udio mplifiers is there to provide the feedbck which reduces the mplifier s distortion when the mplifier is driven to its limits. Some mplifiers such s guitr mplifiers purposely introduce distortion into the sound, so open loop mplifiers re used in these cses, but closed loop mplifiers re usully employed in high fidelity pplictions. If the noise source, V 1, is set to zero in Eqution 22, then the mplifier input noise represented by V 0 is multiplied by the closed loop gin 1/. There is method to further reduce the effects of V 0 by using frequency discrimintion methods. If V 0 is exmined s function of frequency, it will be noticed tht the noise is mde up of mny different frequency components, see Figure 10. IDEAL FILTER SIGNAL NOISE 0 100Hz 10KHz NOISE REMOVED FIGURE 10. INSERTING AN IDEAL FILTEN THE TRANSFER FUNCTION REDUCES NOISE The signl of interest hs finite bndwidth, nd if the noise bndwidth is lrger thn the signl bndwidth, the noise cn be reduced by mking the loop gin function of frequency. Assuming tht the noise bndwidth is 10KHz nd tht the signl bndwidth is 100Hz, the noise beyond 100Hz cn be reduced to minimum if 1/ is reduced to zero beyond 100Hz. One method vilble to ccomplish this bndwidth reduction is through the idel filter inserted in the closed loop, s shown in Figure 10. This filter cn be pproximted with pssive components. F The input nd output impednce of the closed loop circuit cn be controlled by the mount of feedbck nd by the circuit configurtion [4 ]. Through the use of feedbck it is possible for the sme mplifier IC to pper to hve n output impednce pproching zero or pproching infinity, depending on the circuit configurtion employed. Another interesting spect of feedbck systems is tht if function is put in the feedbck loop, in mnner similr to the feedbck fctor,, the inverse function will pper t the output. Grphicl Representtion of the Feedbck Eqution The mthemticl mnipultions required to nlyze feedbck circuit re complicted becuse they involve multipliction nd division; H. W. Bode [5] developed technique clled Bode plot which simplifies the nlysis through the use of grphicl techniques. The Bode equtions re log equtions which tke the form of 20LOG (F(t)) = 20LOG ( F(t) ) + phse ngle. Since these re log equtions, the terms which were multiplied nd divided cn be now dded nd subtrcted; thus, they cn esily be solved grphiclly s will be shown. The trnsfer function for the integrtor shown in Figure 11 is given in Eqution = 1 + RCs Where s = jnd j = (1) R FIGURE 11. INTEGRATOR CIRCUIT (EQ. 23) The mgnitude of the trnsfer function is given by the eqution / = 1 /(1+(RC)2). The pproximte mgnitude or / =1 when = 0.1/RC, / = when =1/ RC nd / = 0.1 when = 10 / RC. These vlues re plotted in Figure 12 using stright line pproximtions. PHASE SHIFT 20LOG( / ) = 0.1/RC DEGREES 45 DEGREES = 1/RC C = 10/RC 2/DECADE 90 DEGREES FIGURE 12. BODE PLOT OF INTEGRATING CIRCUIT TRANSFER FUNCTION The downwrd slope of the mplitude curve in Figure 12 is AN9415 Rev Pge 4 of 13

5 2/decde, nd the point t which the slope chnges, t = 1/RC, is termed the brekpoint. Reding the curve, it cn be seen tht gin initilly is one,, t very low frequencies, flling off to 0.707, 3, t the brek frequency nd decreses t rte of 2/decde for higher frequencies. The phse shift for the integrtor is given in Eqution 24 nd plotted in Figure 12. Notice tht the phse shift is 45 degrees t the brekpoint where = 1/RC. = tngent 1 (1 / RC) (EQ. 24) When the brekpoint occurs in the denomintor, its slope is negtive nd is clled pole. Conversely, when the brekpoint occurs in the numertor, its slope is positive nd it is clled zero. The bnd reject circuit shown in Figure 13 hs two poles, two zeros nd DC gin. Ech pole nd zero is plotted seprtely in Figure 14. The DC gin component is plotted s stright line t 6 becuse it is frequency independent. The two zeros in the numertor both occur t = 1/RC; thus they re plotted on top of ech other, nd this results in positive sloped line rising t 4/decde. The two poles in the denomintor occur t = 0.44/RC nd = 4.56/RC, nd they re ech plotted with negtive slope of 2/decde. Where s = j C R R FIGURE 13. BAND REJECT FILTER CIRCUIT 1+ RCs1+ RCs = 21 + RCs/ RCs/ = 0.44/RC = 1/RC (EQ. 25) FIGURE 14. BODE PLOT OF THE INDIVIDUAL COMPONENTS OF THE BAND REJECT FILTER Ech of the seprte Bode plots shown in Figure 14 re combined into one composite plot in Figure 15. The phse plots re treted much like the mplitude plots becuse the seprte phse responses from the poles nd zeros cn be combined into one plot such s is shown in Figure 15. Now the complete mplitude or phse response of the circuit cn be observed by looking t Figure 15. Although the phse shift t pole is 45 degrees, the plot indictes 5 degrees t = 0.44/RC becuse the double zero locted t = 1/RC hs lredy ccumulted C +4/DECADE = 4.56/RC 2/DECADE R LOG 2/DECADE significnt positive phse shift t the pole frequency. The nonlinerity of the phse plot, result of the tngent function, mkes it hrd to pproximte ccurtely when severl poles nd zeros congregte in the sme vicinity. PHASE SHIFT FIGURE 15. COMPOSITE BODE PLOT FOR THE BAND REJECT FILTER Spcing the poles nd zeros by decde enbles n ccurte phse plot using pproximte methods, but the circuit performnce criteri usully will not llow this luxury. The mplitude plot lso becomes smered by the close proximity of the poles nd zeros, but the exct vlues re not usully plotted becuse the pproximte vlues usully suffice for nlysis [6]. The demnd for the phse ccurcy stems from the oscilltion or stbility criteri which is dependent on phse. Applying logrithms to the system equtions will enble quick nd rther complete nlysis. Eqution 4 is repeted in Eqution 26 in log form; i.e., both sides of the eqution hve been operted on by the function 20LOG 10 (F(t)). 20LOG( / ) = 20LOG(A) 20LOG(1 + A) (EQ. 26) As would be expected from the preceding nlysis, the shpe of the plot will be determined by the brekpoints, if ny, contined in A or.the mgnitude portion of the closed loop system eqution is plotted in Figure 16 for the cse where A nd re not function of frequency. Notice tht both plots re flt lines, nd there is no phse plot. Obviously this cse is trivil nd of no interest to the circuit designer becuse it does not represent the rel world since the gin of ll mplifiers is function of frequency [7]. AMPLITUDE AMPLITUDE DEGREES +12 DEGREES DEGREES 20LOG(A) 20LOG( / ) = 0.44/RC = 1/RC 20LOG(1 + A) = 4.56/RC FIGURE 16. PLOT OF EQUATION 4 WHEN A AND ARE NOT FREQUENCY DEPENDENT Most high gin mplifiers such s opertionl mplifiers hve multiple poles, two per trnsistor, with the mplifier hving s mny s 20 trnsistors leding to potentil of 40 or more poles. Normlly only few poles re importnt becuse the other poles occur t very high frequencies where the gin is less thn one so tht they AN9415 Rev Pge 5 of 13

6 cn not cuse oscilltion. In mny mplifiers the mnufcturer compenstes the mplifier with single pole usully clled dominnt pole (f AMP ), nd the mplifier s performnce cn be pproximted by the trnsfer function A = / (1 + j (f / f AMP )). Eqution 4 is plotted in Figure 17 with the ssumption tht A is frequency dependent nd is resistive or frequency independent. 20LOG(A) 20LOG( / ) 20LOG(1 + A) f = f AMP f 3 FIGURE 17. PLOT OF EQUATION 4 WHEN A = / (1 + j (f /f AMP )) AND IS FREQUENCY INDEPENDENT The closed loop gin grphicl pproximtion is constnt until its projection intersects the mplifier gin t point X. The ctul closed loop gin strts rolling off prior to point X, nd it is down 3 t point X. If 20LOG( / ) 20LOG(A) = 3 then 20LOG(1 + A) = 3, nd if the mgnitude of (1 + A) is considered, then the squre root of (1 + (A) 2 ) = resulting in A = 1. In other words, A = 1/ t the intersection of the two curves. There is method [8] of relting the phse shift, nd thus the stbility, to the slope of the curves t the intersect point, but this method will not be covered here in fvor of the Bode A method. The dominnt pole cuses the open loop gin to hve brekpoint t the frequency f AMP. The internlly compensted op mp cts like dominnt pole chrcteristic so its AC prmeters cn be determined by referring to the OpenLoop Frequency Response curve contined in the dt sheet. Although the curve is clled OpenLoop Frequency Response, it relly is the direct gin (A). Notice tht the CA158 op mp s shown in the Intersil Corportion ctlog [9] hs brekpoint which occurs t f AMP = 5Hz., nd the DC gin is 11. If the trnsfer function shown in Figure 17 ws for the CA158 then the direct gin would be A = /(1 + j (f/ f AMP )), or A = 316,227 /(1 + j (f/ 5)). Consider for moment the difficulty nd hence the probble error ssocited with mesuring the DC gin nd the brek point. A populr method of mesuring the op mp gin nd phse is to configure the op mp in the inverting mode nd then mesure the error voltge; i.e., the voltge from the inverting input to ground. Then Eqution 3, E = / A, is employed to clculte the op mp gin from the mesured error. Assume tht the op mp is configured in gin of 100; then the direct gin is A = 100 / 101 times the op mp gin so smll offset must be ccounted for becuse the mesurement is not direct mesurement in the inverting circuit configurtion. If the output voltge,, is kept smll to gurntee smll signl ccurcy, sy one volt, then for the CA158, V ERROR = 1/316,217 = 3.16V. Mesuring this smll voltge especilly considering tht noise my be present is formidble tsk so designers must ssume tht there my be considerble tolernce ssocited with these mesurements. The numbers given in this pper re for explntion purposes; professionl test engineers will often configure the op mp with gin of A = 10,000 nd then be mesuring errors in the nnovolt rnge. These mesurements require considerble skill, nd even then there my be X 24 difference between the minimum specifiction point nd the typicl vlue such s in the HA5177 dt sheet. GAIN () K 10K 100K 1M 10M 100M FIGURE 18. OPEN LOOP FREQUENCY RESPONSE OF THE HA2842C Figure 18 is plot of the gin phse reltionship for high frequency op mp, the HA2842C. The DC gin is 9, nd since the phse shift reches 45 degrees t 1200Hz the first pole must occur t pproximtely 1200Hz. This is high frequency op mp so the internl compenstion cpcitor hs been reduced significntly to increse the bndwidth vilble to the designer, nd it is pprent tht second pole exists becuse the phse shift pproches 135 degrees t 70MHz. Looking closely t the point where the gin crosses the xis, nd then following tht constnt frequency line, 120MHz, down to the phse curve indictes tht the phse shift is bout 165 degrees. This op mp is mrginlly stble, nd the op mp is susceptible to stbility problems unless externl compenstion techniques re employed. The HA2842C cn be modeled with DC gin of 31,623, the first brek point t 1200Hz nd the second brekpoint t 145MHz. The eqution for the HA2842C is then A = 31,623 / (1 + j (f / 1200))(1 + j (f / 145E6)). Stbility s Determined from Loop Plots A = 1 = 1 /180 (EQ. 27) Eqution 8 hs been repeted bove s Eqution 27. If the mgnitude of the gin is greter thn one in Eqution 27, the eqution will be stisfied becuse the nonliner effects of the ctive devices s they enter sturtion will reduce the gin to one. This is demonstrted in oscilltor design where the designer must design for worse cse gin of t lest one, so the circuit will oscillte under ll conditions, nd the nominl gin usully is much greter thn one. The oscilltor designers re cught in trp, for if they design for worse cse low gin greter thn one, then the worse cse high gin will be much greter thn one. In the low gin cse, the circuit brely oscilltes, but the sinewve is very pure. In the high gin cse, the circuit lwys oscilltes, but there is significnt distortion in the sinewve. Just s the oscilltor designer must mke compromises for the ske of instbility, so, the nlog designer mke compromises for the ske of stbility. In the cse of mplifier design, the phse shift must never become 180 degrees, t gin greter thn one, or oscilltion will occur. The compromise PHASE (DEGREES) AN9415 Rev Pge 6 of 13

7 occurs when the mplifier designer trdes off gin nd / or bndwidth for positive phse shift becuse the methods which produce sfe phse shift tend to reduce gin or bndwidth, s will be shown lter. In mny cses oscilltion is not the limiting fctor becuse s the phse shift gets much greter thn 135 degrees, the mplifier output will hve incresing overshoot nd ringing. Plotting the loop gin gives gret insight into both the stbility nd closed loop performnce; stbility will be discussed in this section nd closed loop performnce predictions from open loop plots will be discussed in the next section. K A = 1+ R 1 C 1 s1+ R 2 C 2 s where K = DC gin. 20LOG(K) AMPLITUDE (A) PHASE (A) /R 1 C 1 20LOG(A) 1/R 2 C 2 (EQ. 28) LOG (f) GM FIGURE 19. LOOP PHASE AND GAIN PLOT OF EQUATION 27 Figure 19 is used to help define the industry stndrd terms, phse mrgin, M, nd gin mrgin, GM. Phse mrgin is mesure of reltive stbility, nd it is defined s the mount of phse shift between the point where the loop gin equls nd 180 degrees. Eqution 29 defines the phse mrgin mthemticlly. M = 180 tngent 1 (A) (EQ. 29) Gin mrgin is defined s the gin t the point where the phse equls 180 degrees. Gin mrgin is lwys negtive (), or less thn one, in stble system, nd it does not contin much informtion bout stbility or closed loop performnce. The phse mrgin shown in Figure 19 is pproximtely 16 degrees; ttempting to mesure the phse mrgin in Figure 19 points out how importnt it is to plot phse mrgin ccurtely. This circuit will be stble since the phse mrgin is positive; the phse shift cnnot ever rech the 180 degrees required for oscilltion if the circuit is to remin stble. Becuse the phse mrgin is very smll, the overshoot will be very lrge, nd the output will exhibit dmped oscilltion commonly known s ringing. If the gin, K, were incresed in the loop trnsfer function until it crossed the xis t 180 degrees phse shift, then the circuit would oscillte; thus, there is definite limit on the loop gin. The loop trnsfer function, shown s Figure 19, is repeted in Figure 20 with the gin incresed by fctor of C. Notice tht indeed the 180 degree phse crossover point occurs prior to the crossover point, so the phse mrgin is negtive nd the circuit will oscillte. Conversely, the trnsfer function shown in Figure 20 does not even hve enough gin t the 180 degree point to ensure oscilltion under production tolernces, so the circuit is good for nothing in its present condition. M 20LOG(K + C) 20LOG(K) AMPLITUDE (A) PHASE (A) /R 1 C 1 LOG (f) 1/R 2 C M = 0 FIGURE 20. LOOP PHASE AND GAIN PLOT OF EQUATION 27 WITH ADDED GAIN C Extremely high gin systems hve very low errors, but they re limited in the bndwidth they cn obtin without oscillting, so designers resort to other techniques such s nonliner trnsfer functions. An exmple of high gin, ccurte system which employs nonliner techniques to chieve stbility, is gyro stbiliztion pltform which would go into limit cycle if the gin ws not reduced upon strtup. If the second brekpoint, 1 / R 2 C 2, were moved closer to the first brekpoint, then the circuit would ccumulte phse shift from the brekpoint erlier nd it my become unstble. Figure 19 is repeted s Figure 21, where the second brekpoint hs been moved closer to the first brekpoint. Notice tht the 45 degree phse point is not ffected, the 135 degree phse point hs moved in towrds the 45 degree phse point, nd tht the 180 degree phse point occurs prior to the crossover point. Generlly, moving the two poles closer together cn cuse instbility. 20LOG(K) AMPLITUDE (A) 45 PHASE (A) 135 1/R 1 C 1 1/R 2 C 2 20LOG(A) LOG (f) 180 M = 0 FIGURE 21. LOOP PHASE AND GAIN PLOT OF EQUATION 27 WITH 1/R 2 C 2 CLOSER TO 1/R 1 C 1 The single pole system cnnot ccumulte more thn 90 degrees of phse shift so it cnnot become unstble; thus single pole systems will not be discussed here. This does not men tht n internlly compensted op mp, which cts like dominnt pole, cnnot become unstble becuse ll op mps hve more thn one pole. The proof of this is the dt sheet, consider the HA2500 [10] which is internlly compensted for unity gin, where the Open Loop Frequency nd Phse Response curve AN9415 Rev Pge 7 of 13

8 shows phse shifts beyond 90 degrees. Lots of good dt cn be gthered from these curves; i.e., the phse mrgin for the HA2500 is pproximtely 30 degrees so there will be some overshoot, nd there is second pole t bout 3MHz. There is no such thing s n unconditionlly stble op mp unless it lies on the tble with power disconnected, becuse ll op mps re multiple pole devices especilly when stry cpcitnces re considered. This conclusion my led someone to wonder where to drw the line when doing n nlysis, nd most engineers drw the line t two poles becuse the mthemtics re esy to hndle. If required, they obtin solution for lrger systems through the use of superposition, but usully the poles re seprted fr enough for some of them to be ignored or the circuit is modified to chieve the seprtion. The next section will delve into the second order stbility nlysis more deeply. Poles nd zeros lwys occur in pirs, lthough sometimes either the pole or zero my be t the origin or infinity, thus they will not lwys pper in the trnsfer function. Whenever pole is referred to, its corresponding zero is lso considered. Predicting Stbility nd Performnce from Closed Loop Plots The closed loop AC performnce of feedbck circuit is dependent on the order of the denomintor eqution which is often considered equivlent to the number of poles contined in the circuit. If the circuit hs no poles then its AC performnce does not vry with frequency. If the circuit hs one pole then the closed loop AC performnce is rther esy to describe; the gin on Bode plot will be 20LOG(K) nd the mplitude response will strt flling off t the brekpoint with 2/decde slope. If the circuit hs two or more poles the closed loop AC response is much more complicted, the circuit cn overshoot, then ring nd finlly oscillte. The second order circuit, which contins two poles, is so populr tht it is described extensively in the literture [11], nd it is the one tht will be dwelled on here. Higher order circuits cn usully be reduced to second order for closed loop performnce nlysis, so this nlysis will be restricted to stbility nd closed loop performnce for second order circuits. Eqution 7 is written here s Eqution 30 with second order loop trnsfer function substituted for A. Eqution 31 is obtined from Eqution 30 through lgebric mnipultion. K 1 + As = 1 + = s s 2 where = RC s K + s + = (EQ. 30) (EQ. 31) Eqution 32 is the stndrd second order control eqution, nd it is compred to Eqution 31 to obtin Eqution 33 nd Eqution 34 which define the dmping rtio,, nd undmped nturl frequency, N. s N s + N = 0 = 2f K N = N = 1 2 (EQ. 32) (EQ. 33) (EQ. 34) The frequency where the mgnitude of the loop trnsfer function, A, is equl to one is defined s the crossover frequency, C ; this is expressed in Eqution 35 with C substituted for. Then Eqution 35 is lgebriclly mnipulted to obtin Eqution 36 from which the phse functions shown in Eqution 37 nd Eqution 38 re obtined. K = C C 2 (EQ. 35) C 4 + 2N 2 C 2 N 4 = 0 (EQ. 36) M TAN 1 C = 2 1 C 1 2 M = TAN 1 2 N / C (EQ. 37) (EQ. 38) Considering the trnsfer function shown in Figure 22, if the crossover frequency, = C, occurs well fter the brek frequency, 1 / 2, then Eqution 39 cn be simplified to Eqution 40. Solving Eqution 40 for C yields Eqution LOG(A) = 20LOG(K) 20LOG( ) 1/2 20LOG( ) 1/2 (EQ. 39) 20LOG(A) = 20LOG(K) 20LOG( 1 ) 20LOG( 2 ) for» 1/ 2 (EQ. 40) C = DAMPING RATIO, K 1 N for» PERCENT MAXIMUM OVERSHOOT PHASE MARGIN, M (EQ. 41) FIGURE 22. PHASE MARGIN AND PERCENT OVERSHOOT AS A FUNCTION OF DAMPING RATIO Figure 22 is plot of Eqution 38; now the phse mrgin is expressed in terms of known quntities so it cn be clculted from knowledge the pole loctions. The estimtion procedure is to determine the pole loctions from knowing the op mp pole loctions nd from the externl circuitry. Once the pole loctions nd the gin re known or estimted the phse mrgin, dmping rtio nd cutoff frequency cn be clculted. Then using Figure 22 yields the percent overshoot. The pole loctions nd gin cn be vried to obtin different solutions to the problem. After ll of this dt is stisfctory, then the loop trnsfer function should be plotted to determine stbility. While only the poles were used in the estimtion procedure, both the poles nd zeros must be used to plot the open trnsfer function. After severl itertions workble solution should pop out AN9415 Rev Pge 8 of 13

9 if one exists. Remember tht this procedure is n pproximtion, thus it must lwys be verified in the lbortory. Schemes All op mps re compensted; some re compensted with internl components thus sving the designer time nd money. Mny op mps re not compensted internlly becuse leving out the compenstion gives the designer n extr degree of freedom, nd these op mps must hve some kind of externl compenstion or they will oscillte. The internlly compensted op mps re usully compensted with method clled dominnt pole or lg compenstion severl forms of which re shown in Figure 23. R C C pole compenstion is only used inside the op mp, when the closed loop bndwidth requirements re not gret, or if noise reduction is desired. A simpler method of compensting the op mp is with gin compenstion. Consider Eqution 14 which is repeted here s Eqution 42; this eqution is for the loop gin nd it is vlid for both inverting nd noninverting op mps. If the closed loop inverting gin is incresed to 9, then Eqution 42 becomes A/10 decrese of 2 in the DC intercept. Plotting these results in Figure 25 revels tht the circuit hs become stble without much of bndwidth reduction. V O Z = 1 = A V I Z 1 + Z 2 2 (EQ. 42) ORIGINAL OP AMP CURVE 20LOG(A) COMPENSATED OP AMP CURVE C C R C C C 1/ 1 1/ 2 FIGURE 25. GAIN COMPENSATION FIGURE 23. EXAMPLES OF DOMINANT POLE COMPENSATION Dominnt pole compenstion circuits tend to be ssocited with the op mp, nd they usully re not prt of the feedbck circuit. The loop trnsfer function for n op mp is shown in Figure 24 in solid lines. There re two poles ccumulting phse shift prior to the crossover point; thus this circuit my very well be unstble. The first pole, 1/ 1, is the low frequency brek point of the op mp, nd the second pole, 1/ 2, is the high frequency brek point. Since these pole loctions re inherent in the op mp design, the circuit designer must live with them, but the effects of these poles cn be modified with externl feedbck components. Locting the dominnt pole, 1/ DP, so tht the crossover point coincides with the first op mp pole, 1, yields phse mrgin of 45 degrees. By locting the dominnt pole zero crossing t 1/ 1 the circuit scrifices significnt bndwidth which cn be regined by moving the pole further out. The exct pole plcement will be function of the circuit specifictions such s the llowed overshoot or the bndwidth required. 20LOG(A) 1/ DP 1/ 1 1/ 2 FIGURE 24. DOMINANT POLE COMPENSATION PLOT Becuse of the loop gin loss nd the bndwidth loss dominnt The occsion lwys rises where the closed loop gin must be one or less, thereby precluding the use of gin compenstion; thus the designer must resort to other techniques to chieve the circuit performnce. An lternte method of compenstion is clled led compenstion, nd it consists of putting zero in the loop trnsfer function to cncel out one of the poles. The best plce to locte the zero is on top of the second pole, since this cncels the negtive phse shift cused by the second pole. The schemtic of circuit which employs led compenstion is shown in Figure 26, nd Eqution 43 is for the loop trnsfer function. + FIGURE 26. LEAD COMPENSATION The zero in Eqution 43 occurs before the pole, so it cn be used to cncel out the pole t 1/ 2 by plcing the zero on top of the pole. Now the 135 degree phse shift point hs moved out to 1/R F Cs yielding better phse mrgin. There re lwys compromises to be mde when designing feedbck circuit, nd the one mde here is to dd externl components. If the op mp hs dditionl poles close to 1/ 2, nd mny op mps do, then the pole plcement is criticl. Some op mps hve so mny poles in the re of 1/ 2 tht this method of compenstion cnnot be used. R F Cs + 1 A = + R F R F Cs + 1 (EQ. 43) Unless specified otherwise, the mplifier gin () will be R F C AN9415 Rev Pge 9 of 13

10 ssumed to hve the form = K / (1 + 1 s)(1 + 2 s). 20LOG(K /( + R F )) Referring to Figure 29, it cn be seen tht the ledlg compensted circuit crosses t lower frequency thn the uncompensted circuit, thus the compenstion hs mde the circuit more stble. Also, the trnsfer function of the compenstion hs been shown in Figure 29 for clrity. There is n dditionl dvntge to ledlg compenstion in tht it yields higher gin t high frequencies. The closed loop gin plots, Figure 30, show tht the zero precedes the pole; the poles nd zeros interchnge when the plot chnges from the loop gin to the closed loop gin. Also, the high frequency gin is emphsized with ledlg compenstion. The high frequency emph 20LOG(A) 1/ 1 1/ 2 1/R F Cs ORIGINAL TRANSFER FUNCTION 1/R F Cs FIGURE 27. LEAD COMPENSATION PLOT MODIFIED TRANSFER FUNCTION Sometimes good look t the problem revels potentil solution, so the cse of stry input cpcitnce will be investigted. An inverting mplifier with stry input cpcitnce, C I, is shown in Figure 28. Looking t Eqution 44 for the open loop trnsfer function, it is obvious tht the stry cpcitnce dds pole to the trnsfer function, nd if the dded pole is close to 1/ 2 the circuit will become unstble. The cpcitor, C F shown in dotted lines, is dded to the circuit to yield the trnsfer function shown in Eqution 45. Inspection of Eqution 45 revels tht if C I = R F C F, then the poles nd zeros in the trnsfer function will cncel ech other, nd the trnsfer function will pper to be independent of frequency. This type of compenstion is nmed fter the sme ide used in the compensted ttenutor, which is n old instrument design trick. Which just proves tht little in circuit design is relly new. + C F in circuit: C I s + 1 A = R F C I s R F C F s + 1 (EQ. 45) There re times when n extr degree of freedom is required nd the ledlg, sometimes clled the feedforwrd, form of compenstion yields this freedom. This method of compenstion puts pole nd zero in the loop trnsfer function. If the pole nd zero loctions must be independent of ech other, then seprte compenstion networks need to be used. An exmple of this would be to use lg circuit similr to tht shown in Figure 24, nd led circuit similr to tht shown in Figure 26. The led nd lg would then be independent in the exmple so they could be plced conveniently for compenstion purposes. The circuit shown in Figure 29 hs both pole nd zero, but their plcement is not independent. RCs + 1 A = + R F R + R F R+ R F Cs + 1 R F + C 20LOG( /(R F + )) R + R F 20LOG(A) BEFORE COMPENSATION (EQ. 46) C I C F AMPLITUDE 20LOG(A) AFTER COMPENSATION ORIGINAL TRANSFER FUNCTION 20LOG(A) PHASE (A) FIGURE 28. COMPENSATED ATTENUATOR CIRCUIT SCHEMATIC, GAIN PLOT AND PHASE PLOT No C F : ORIGINAL TRANSFER FUNCTION 1 A = + R F 1 + R F Cs 1/ 1 1/ 2 1/ R F Cs MODIFIED TRANSFER FUNCTION MODIFIED TRANSFER FUNCTION (EQ. 44) 1/ 1/(RC) 1/ 1 1/ 2 COMPENSATION NETWORK (R +R F R+R F ) Cs (R F + ) FIGURE 29. LEADLAG COMPENSATION SCHEMATIC AND A AMPLITUDE PLOT AN9415 Rev Pge 10 of 13

11 sis my be desirble when high overll gin is needed, but some unwnted effects, such s DC offset, must be minimized. The ledlg method of compenstion usully requires the precise plcement of the poles nd zeros so detiled nd ccurte [12] phse plot is generlly constructed for this cse. 20LOG(A) 20LOG(R F / ) 1/(R+ )C DIRECT GAIN CLOSED LOOP COMPENSATED CLOSED LOOP UNCOMPENSATED FIGURE 30. LEADLAG CLOSED LOOP GAIN PLOTS FOR COM PENSATED AND UNCOMPENSATED CIRCUITS Comprison of Results Dominnt pole compenstion is the esiest method of compenstion to implement within n IC, but it rolls off the closed loop gin so quickly tht it is seldom used except in op mp design. The circuit resulting from dominnt pole design is very well behved becuse the phse mrgin is usully bout 45 degrees, but the frequency response is very poor. If the trnsfer function for the HA2842C shown in Figure 18 is compensted by dominnt pole compenstion, the pole would be plced t 1200Hz; the loop gin when moving to lower frequency would then rise t rte of 2/decde until it hit the 9 point t 0.06Hz. This is n effective bndwidth reduction of 4.5 decdes, from 120MHz to 1200Hz, so this method is only used when no other type of compenstion is vilble, noise reduction is more importnt thn bndwidth or bndwidth is not importnt. Gin compenstion is lwys the preferred method of compenstion if the resulting higher closed loop gin meets the performnce criteri, but mny times the design specifictions cll for buffer or n inverter both with gin of one, which precludes gin compenstion. Gin compenstion does not require ny dditionl externl components beyond the gin setting resistors, it preserves the op mp bndwidth nd it is esy to implement. In single pole system, incresing gin will reduce the bndwidth by the sme fctor. Led compenstion offers n AC compenstion which cn function for ny DC gin, nd it is hs much higher frequency response thn dominnt pole compenstion. One deficiency with led compenstion is tht the DC gin, the zero nd the pole re ll tied together tightly. For exmple if the HA2842C shown in Figure 18 is led compensted for closed loop gin of 1 then = R F. This mens tht the pole nd zero re only seprted by n octve so the compenstion must be done in n re of the loop gin plot which is very close to. Observing Figure 18, it cn be seen tht the best plce tht led compenstion cn improve stbility significntly is t the second pole where the phse equls 135 degrees phse shift nd the frequency is 75MHz. Plcing the zero t 75MHz yields phse mrgin of bout 60 degrees resulting nice stble circuit with 10% overshoot per Figure 22. The closed loop response eqution is /V F = R / 1 / (R F Cs + 1), nd the closed loop gin is 1 until it reches the frequency f =1/2R F C, 150MHz, where it is down by 3. Led compenstion rolls off the closed loop frequency response drmticlly. AN9415 Rev Pge 11 of 13

12 The compensted ttenutor pproch works well for negting the effects of n input cpcitnce becuse both the open loop nd closed loop trnsfer functions hve flt frequency response. Also, the compenstion required is very smll. When the output resistnce of n op mp gets very high, the stry cpcitnce seen cross the resistor cts like led circuit nd rolls off the high frequency gin. Adding n input cpcitor, the reverse of ttenutor compenstion, serves to restore the high frequency performnce. Both digitltonlog converters nd opticl receiving diodes hve lrge ssocited cpcitnces, so when they re put into the input circuit of n op mp, often in n ItoV converter configurtion, the circuit oscilltes. The compensted ttenutor tmes these circuits, but bewre, the compenstion must consider the worst cse especilly for current DACs which hve wide rnge of output cpcitnce. The ledlg compenstion scheme is very similr to the led compenstion scheme but it hs two dvntges. First, setting the DC gin does not fix the pole zero seprtion, so for low gins the pole nd zero could be seprted by more thn n octve. Second, zero shows up in the closed loop trnsfer function where it increses the gin t high frequencies. The combintion of these two dvntges re gret enough to outweigh the cost of the extr components dded to the circuit. The compenstion techniques demonstrted here serve s good foundtion for feedbck circuit design, but like ll foundtions it is ment to be built on [13]. There re other methods of treting compenstion such s closed loop stbility plots, Nichols chrts, root locus plots nd Nyquist nlysis. Ech technique offers some dvntges nd disdvntges; the Bode method simply is the uthor s personl choice so the other techniques deserve investigtion. References [1] Areocentric, Sol, Feedbck Amplifier Principles, Mcmilln Publishing Compny, [2] Del Toro, Vincent nd Prker, Sydney, Principles of Control Systems Engineering, McGrwHill Book Compny, [3] Del Toro, Vincent nd Prker, Sydney, Principles of Control Systems Engineering, McGrwHill Book Compny, [4] DiStefno, Joseph, Stubberud, Allen nd Willims, Ivn, Theory nd Problems of Feedbck nd Control Systems, Schum s Outline Series, McGrwHill Book Compny, [5] Bode H. W., Network Anlysis nd Feedbck Amplifier Design, D. Vn Nostrnd, Inc., [6] D Azzo, John nd Houpis, Constntine, Feedbck Control System Anlysis nd Synthesis, McGrwHill Book Compny, [7] Frederiksen, Thoms, Intuitive Opertionl Amplifiers, McGrwHill Book Compny, [8] Bower, J. L. nd Schultheis, P. M., Introduction to the Design of Servomechnisms, Wiley, [9] Intersil Corportion, Liner nd Telecom ICS for Anlog Signl Processing Applictions, [10] Sme s bove. [11] Del Toro, Vincent nd Prker Sydney, Principles of Control Systems Engineering, McGrwHill Book Compny, [12] Kuo, Benjmin, Automtic Control Systems, PrenticeHll, Inc., [13] Bell, Ken, Converstions bout feedbck circuits while t Chrles Strk Drper Lbs, AN9415 Rev Pge 12 of 13

13 Notice 1. Descriptions of circuits, softwre nd other relted informtion in this document re provided only to illustrte the opertion of semiconductor products nd ppliction exmples. You re fully responsible for the incorportion or ny other use of the circuits, softwre, nd informtion in the design of your product or system. Reness Electronics disclims ny nd ll libility for ny losses nd dmges incurred by you or third prties rising from the use of these circuits, softwre, or informtion. 2. Reness Electronics hereby expressly disclims ny wrrnties ginst nd libility for infringement or ny other clims involving ptents, copyrights, or other intellectul property rights of third prties, by or rising from the use of Reness Electronics products or technicl informtion described in this document, including but not limited to, the product dt, drwings, chrts, progrms, lgorithms, nd ppliction exmples. 3. No license, express, implied or otherwise, is grnted hereby under ny ptents, copyrights or other intellectul property rights of Reness Electronics or others. 4. You shll not lter, modify, copy, or reverse engineer ny Reness Electronics product, whether in whole or in prt. Reness Electronics disclims ny nd ll libility for ny losses or dmges incurred by you or third prties rising from such ltertion, modifiction, copying or reverse engineering. 5. Reness Electronics products re clssified ccording to the following two qulity grdes: Stndrd nd High Qulity. The intended pplictions for ech Reness Electronics product depends on the product s qulity grde, s indicted below. "Stndrd": Computers; office equipment; communictions equipment; test nd mesurement equipment; udio nd visul equipment; home electronic pplinces; mchine tools; personl electronic equipment; industril robots; etc. "High Qulity": Trnsporttion equipment (utomobiles, trins, ships, etc.); trffic control (trffic lights); lrgescle communiction equipment; key finncil terminl systems; sfety control equipment; etc. Unless expressly designted s high relibility product or product for hrsh environments in Reness Electronics dt sheet or other Reness Electronics document, Reness Electronics products re not intended or uthorized for use in products or systems tht my pose direct thret to humn life or bodily injury (rtificil life support devices or systems; surgicl implnttions; etc.), or my cuse serious property dmge (spce system; underse repeters; nucler power control systems; ircrft control systems; key plnt systems; militry equipment; etc.). Reness Electronics disclims ny nd ll libility for ny dmges or losses incurred by you or ny third prties rising from the use of ny Reness Electronics product tht is inconsistent with ny Reness Electronics dt sheet, user s mnul or other Reness Electronics document. 6. When using Reness Electronics products, refer to the ltest product informtion (dt sheets, user s mnuls, ppliction notes, Generl Notes for Hndling nd Using Semiconductor Devices in the relibility hndbook, etc.), nd ensure tht usge conditions re within the rnges specified by Reness Electronics with respect to mximum rtings, operting power supply voltge rnge, het dissiption chrcteristics, instlltion, etc. Reness Electronics disclims ny nd ll libility for ny mlfunctions, filure or ccident rising out of the use of Reness Electronics products outside of such specified rnges. 7. Although Reness Electronics endevors to improve the qulity nd relibility of Reness Electronics products, semiconductor products hve specific chrcteristics, such s the occurrence of filure t certin rte nd mlfunctions under certin use conditions. Unless designted s high relibility product or product for hrsh environments in Reness Electronics dt sheet or other Reness Electronics document, Reness Electronics products re not subject to rdition resistnce design. You re responsible for implementing sfety mesures to gurd ginst the possibility of bodily injury, injury or dmge cused by fire, nd/or dnger to the public in the event of filure or mlfunction of Reness Electronics products, such s sfety design for hrdwre nd softwre, including but not limited to redundncy, fire control nd mlfunction prevention, pproprite tretment for ging degrdtion or ny other pproprite mesures. Becuse the evlution of microcomputer softwre lone is very difficult nd imprcticl, you re responsible for evluting the sfety of the finl products or systems mnufctured by you. 8. Plese contct Reness Electronics sles office for detils s to environmentl mtters such s the environmentl comptibility of ech Reness Electronics product. You re responsible for crefully nd sufficiently investigting pplicble lws nd regultions tht regulte the inclusion or use of controlled substnces, including without limittion, the EU RoHS Directive, nd using Reness Electronics products in complince with ll these pplicble lws nd regultions. Reness Electronics disclims ny nd ll libility for dmges or losses occurring s result of your noncomplince with pplicble lws nd regultions. 9. Reness Electronics products nd technologies shll not be used for or incorported into ny products or systems whose mnufcture, use, or sle is prohibited under ny pplicble domestic or foreign lws or regultions. You shll comply with ny pplicble export control lws nd regultions promulgted nd dministered by the governments of ny countries sserting jurisdiction over the prties or trnsctions. 10. It is the responsibility of the buyer or distributor of Reness Electronics products, or ny other prty who distributes, disposes of, or otherwise sells or trnsfers the product to third prty, to notify such third prty in dvnce of the contents nd conditions set forth in this document. 11. This document shll not be reprinted, reproduced or duplicted in ny form, in whole or in prt, without prior written consent of Reness Electronics. 12. Plese contct Reness Electronics sles office if you hve ny questions regrding the informtion contined in this document or Reness Electronics products. (Note 1) Reness Electronics s used in this document mens Reness Electronics Corportion nd lso includes its directly or indirectly controlled subsidiries. (Note 2) Reness Electronics product(s) mens ny product developed or mnufctured by or for Reness Electronics. (Rev.4.01 November 2017) SALES OFFICES Refer to " for the ltest nd detiled informtion. Reness Electronics Americ Inc Murphy Rnch Rod, Milpits, CA 95035, U.S.A. Tel: , Fx: Reness Electronics Cnd Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontrio Cnd L4C 9T3 Tel: Reness Electronics Europe Limited Dukes Medow, Millbord Rod, Bourne End, Buckinghmshire, SL8 5FH, U.K Tel: , Fx: Reness Electronics Europe GmbH Arcdistrsse 10, Düsseldorf, Germny Tel: , Fx: Reness Electronics (Chin) Co., Ltd. Room 1709 Quntum Plz, No.27 ZhichunLu, Hidin District, Beijing, P. R. Chin Tel: , Fx: Reness Electronics (Shnghi) Co., Ltd. Unit 301, Tower A, Centrl Towers, 555 Lngo Rod, Putuo District, Shnghi, P. R. Chin Tel: , Fx: Reness Electronics Hong Kong Limited Unit , 16/F., Tower 2, Grnd Century Plce, 193 Prince Edwrd Rod West, Mongkok, Kowloon, Hong Kong Tel: , Fx: Reness Electronics Tiwn Co., Ltd. 13F, No. 363, Fu Shing North Rod, Tipei 10543, Tiwn Tel: , Fx: Reness Electronics Singpore Pte. Ltd. 80 Bendemeer Rod, Unit #0602 Hyflux Innovtion Centre, Singpore Tel: , Fx: Reness Electronics Mlysi Sdn.Bhd. Unit 1207, Block B, Menr Amcorp, Amcorp Trde Centre, No. 18, Jln Persirn Brt, Petling Jy, Selngor Drul Ehsn, Mlysi Tel: , Fx: Reness Electronics Indi Pvt. Ltd. No.777C, 100 Feet Rod, HAL 2nd Stge, Indirngr, Bnglore , Indi Tel: , Fx: Reness Electronics Kore Co., Ltd. 17F, KAMCO Yngje Tower, 262, Gngnmdero, Gngnmgu, Seoul, Kore Tel: , Fx: Reness Electronics Corportion. All rights reserved. Colophon 7.0

### Understanding Basic Analog Ideal Op Amps

Appliction Report SLAA068A - April 2000 Understnding Bsic Anlog Idel Op Amps Ron Mncini Mixed Signl Products ABSTRACT This ppliction report develops the equtions for the idel opertionl mplifier (op mp).

More information

### Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Idel Opertionl Amplifiers Fll 2009 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

### Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Idel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

### (CATALYST GROUP) B"sic Electric"l Engineering

(CATALYST GROUP) B"sic Electric"l Engineering 1. Kirchhoff s current l"w st"tes th"t (") net current flow "t the junction is positive (b) Hebr"ic sum of the currents meeting "t the junction is zero (c)

More information

### DESIGN OF CONTINUOUS LAG COMPENSATORS

DESIGN OF CONTINUOUS LAG COMPENSATORS J. Pulusová, L. Körösi, M. Dúbrvská Institute of Robotics nd Cybernetics, Slovk University of Technology, Fculty of Electricl Engineering nd Informtion Technology

More information

### Synchronous Machine Parameter Measurement

Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions

More information

### Synchronous Machine Parameter Measurement

Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions

More information

### CHAPTER 2 LITERATURE STUDY

CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:

More information

### Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION

Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You

More information

### EET 438a Automatic Control Systems Technology Laboratory 5 Control of a Separately Excited DC Machine

EE 438 Automtic Control Systems echnology bortory 5 Control of Seprtely Excited DC Mchine Objective: Apply proportionl controller to n electromechnicl system nd observe the effects tht feedbck control

More information

### Application Note. Differential Amplifier

Appliction Note AN367 Differentil Amplifier Author: Dve n Ess Associted Project: Yes Associted Prt Fmily: CY8C9x66, CY8C7x43, CY8C4x3A PSoC Designer ersion: 4. SP3 Abstrct For mny sensing pplictions, desirble

More information

### The Discussion of this exercise covers the following points:

Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI

More information

### CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES

CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.

More information

### Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)

ICs for Cssette, Cssette Deck ANN, ANN Puse Detection s of Rdio Cssette, Cssette Deck Overview The ANN nd the ANN re the puse detection integrted circuits which select the progrm on the cssette tpe. In

More information

### Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator)

Three-Phse Synchronous Mchines The synchronous mchine cn be used to operte s: 1. Synchronous motors 2. Synchronous genertors (Alterntor) Synchronous genertor is lso referred to s lterntor since it genertes

More information

### A Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM

A ovel Bck EMF Zero Crossing Detection of Brushless DC Motor Bsed on PWM Zhu Bo-peng Wei Hi-feng School of Electricl nd Informtion, Jingsu niversity of Science nd Technology, Zhenjing 1003 Chin) Abstrct:

More information

### Simulation of Transformer Based Z-Source Inverter to Obtain High Voltage Boost Ability

Interntionl Journl of cience, Engineering nd Technology Reserch (IJETR), olume 4, Issue 1, October 15 imultion of Trnsformer Bsed Z-ource Inverter to Obtin High oltge Boost Ability A.hnmugpriy 1, M.Ishwry

More information

### Engineer-to-Engineer Note

Engineer-to-Engineer Note EE-297 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil

More information

### ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC

User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...

More information

### METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin

METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN Inventor: Brin L. Bskin 1 ABSTRACT The present invention encompsses method of loction comprising: using plurlity of signl trnsceivers to receive one or

More information

### Module 9. DC Machines. Version 2 EE IIT, Kharagpur

Module 9 DC Mchines Version EE IIT, Khrgpur esson 40 osses, Efficiency nd Testing of D.C. Mchines Version EE IIT, Khrgpur Contents 40 osses, efficiency nd testing of D.C. mchines (esson-40) 4 40.1 Gols

More information

### & Y Connected resistors, Light emitting diode.

& Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd

More information

### University of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 4143/5195 Electrical Machinery Fall 2009

Problem 1: Using DC Mchine University o North Crolin-Chrlotte Deprtment o Electricl nd Computer Engineering ECGR 4143/5195 Electricl Mchinery Fll 2009 Problem Set 4 Due: Thursdy October 8 Suggested Reding:

More information

### Synchronous Generator Line Synchronization

Synchronous Genertor Line Synchroniztion 1 Synchronous Genertor Line Synchroniztion Introduction One issue in power genertion is synchronous genertor strting. Typiclly, synchronous genertor is connected

More information

### MEASURE THE CHARACTERISTIC CURVES RELEVANT TO AN NPN TRANSISTOR

Electricity Electronics Bipolr Trnsistors MEASURE THE HARATERISTI URVES RELEVANT TO AN NPN TRANSISTOR Mesure the input chrcteristic, i.e. the bse current IB s function of the bse emitter voltge UBE. Mesure

More information

### Nevery electronic device, since all the semiconductor

Proceedings of Interntionl Joint Conference on Neurl Networks, Orlndo, Florid, USA, August 12-17, 2007 A Self-tuning for Rel-time Voltge Regultion Weiming Li, Xio-Hu Yu Abstrct In this reserch, self-tuning

More information

### Engineering: Elec 3509 Electronics II Instructor: Prof. Calvin Plett,

Engineering: Elec 3509 Electronics II Instructor: Prof. Clvin Plett, emil cp@doe.crleton.c Objective: To study the principles, design nd nlysis of nlog electronic circuits. Description: In this course,

More information

### 5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies

74 EEE TRANSACTONS ON POER ELECTRONCS, VOL. 3, NO. 2, APRL 988 A Comprison of Hlf-Bridge Resonnt Converter Topologies Abstrct-The hlf-bridge series-resonnt, prllel-resonnt, nd combintion series-prllel

More information

### MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion

More information

### A Development of Earthing-Resistance-Estimation Instrument

A Development of Erthing-Resistnce-Estimtion Instrument HITOSHI KIJIMA Abstrct: - Whenever erth construction work is done, the implnted number nd depth of electrodes hve to be estimted in order to obtin

More information

### Example. Check that the Jacobian of the transformation to spherical coordinates is

lss, given on Feb 3, 2, for Mth 3, Winter 2 Recll tht the fctor which ppers in chnge of vrible formul when integrting is the Jcobin, which is the determinnt of mtrix of first order prtil derivtives. Exmple.

More information

### Fuzzy Logic Controller for Three Phase PWM AC-DC Converter

Journl of Electrotechnology, Electricl Engineering nd Mngement (2017) Vol. 1, Number 1 Clusius Scientific Press, Cnd Fuzzy Logic Controller for Three Phse PWM AC-DC Converter Min Muhmmd Kml1,, Husn Ali2,b

More information

### Exponential-Hyperbolic Model for Actual Operating Conditions of Three Phase Arc Furnaces

Americn Journl of Applied Sciences 6 (8): 1539-1547, 2009 ISSN 1546-9239 2009 Science Publictions Exponentil-Hyperbolic Model for Actul Operting Conditions of Three Phse Arc Furnces 1 Mhdi Bnejd, 2 Rhmt-Allh

More information

### Lab 8. Speed Control of a D.C. motor. The Motor Drive

Lb 8. Speed Control of D.C. motor The Motor Drive Motor Speed Control Project 1. Generte PWM wveform 2. Amplify the wveform to drive the motor 3. Mesure motor speed 4. Mesure motor prmeters 5. Control

More information

### Polar Coordinates. July 30, 2014

Polr Coordintes July 3, 4 Sometimes it is more helpful to look t point in the xy-plne not in terms of how fr it is horizontlly nd verticlly (this would men looking t the Crtesin, or rectngulr, coordintes

More information

### Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):

SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween

More information

### TOSHIBA BiCD Integrated Circuit Silicon Monolithic TB6674FG

TB6674G TOSIBA BiCD Integrted Circuit Silicon Monolithic TB6674G Stepping Motor Driver IC TB6674G is stepping motor driver IC with MOS output trnsistors. The IC cn control two-phse stepping motor forwrd

More information

### This is a repository copy of Effect of power state on absorption cross section of personal computer components.

This is repository copy of Effect of power stte on bsorption cross section of personl computer components. White Rose Reserch Online URL for this pper: http://eprints.whiterose.c.uk/10547/ Version: Accepted

More information

### ECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design

ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers,

More information

### Compared to generators DC MOTORS. Back e.m.f. Back e.m.f. Example. Example. The construction of a d.c. motor is the same as a d.c. generator.

Compred to genertors DC MOTORS Prepred by Engr. JP Timol Reference: Electricl nd Electronic Principles nd Technology The construction of d.c. motor is the sme s d.c. genertor. the generted e.m.f. is less

More information

### TYPE N AND ON CARRIER REPEATERS-REPEATERED NIA HIGH-LOW TRANSISTORIZED REPEATER CONTENTS PAGE 1. GENERAL This section describes the physical and

BELL SYSTEM PRACTCES Plnt Series SECTON 362-4- 1 2 1 ssue 2, December 1969 AT&TCo Stndrd TYPE N AND ON CARRER REPEATERS-REPEATERED HGH-FREQUENCY LNE DESCRPTON-TYPE NA HGH-LOW TRANSSTORZED REPEATER CONTENTS

More information

### 2N6071A/B Series. Sensitive Gate Triacs. Silicon Bidirectional Thyristors TRIACS 4.0 A RMS, V

Preferred Device Sensitive Gte Trics Silicon Bidirectionl Thyristors Designed primrily for full-wve AC control pplictions, such s light dimmers, motor controls, heting controls nd power supplies; or wherever

More information

### Geometric quantities for polar curves

Roerto s Notes on Integrl Clculus Chpter 5: Bsic pplictions of integrtion Section 10 Geometric quntities for polr curves Wht you need to know lredy: How to use integrls to compute res nd lengths of regions

More information

### High Speed On-Chip Interconnects: Trade offs in Passive Termination

High Speed On-Chip Interconnects: Trde offs in Pssive Termintion Rj Prihr University of Rochester, NY, USA prihr@ece.rochester.edu Abstrct In this pper, severl pssive termintion schemes for high speed

More information

### (1) Non-linear system

Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems

More information

### Performance Comparison of Sliding Mode Control and Conventional PI Controller for Speed Control of Separately Excited Direct Current Motors

Journl of Science nd Technology Vol. 13, No. 2 Engineering nd Computer Sciences (ECS) Performnce Comprison of Sliding Mode Control nd Conventionl PI Controller for Speed Control of Seprtely Excited Direct

More information

### Study on SLT calibration method of 2-port waveguide DUT

Interntionl Conference on Advnced Electronic cience nd Technology (AET 206) tudy on LT clibrtion method of 2-port wveguide DUT Wenqing Luo, Anyong Hu, Ki Liu nd Xi Chen chool of Electronics nd Informtion

More information

### Alternating-Current Circuits

chpter 33 Alternting-Current Circuits 33.1 AC Sources 33.2 esistors in n AC Circuit 33.3 Inductors in n AC Circuit 33.4 Cpcitors in n AC Circuit 33.5 The LC Series Circuit 33.6 Power in n AC Circuit 33.7

More information

### Passive and Active DC Breakers in the Three Gorges-Changzhou HVDC Project

Pssive nd Active DC Brekers in the Three Gorges-Chngzhou HVDC Project Dg Andersson, Dr, nd Anders Henriksson, B.Sc.E.E, ABB, Sweden explined below) re Abstrct--A new type of DC breker, bsed on stndrd SF

More information

### Section 2.2 PWM converter driven DC motor drives

Section 2.2 PWM converter driven DC motor drives 2.2.1 Introduction Controlled power supply for electric drives re obtined mostly by converting the mins AC supply. Power electronic converter circuits employing

More information

### Passive and Active Hybrid Integrated EMI Filters

Pssive nd Active Hybrid Integrted EMI Filters J. Biel, A. Wirthmueller, R. Wespe, M.. Heldwein, J. W. Kolr Power Electronic Systems bortory Swiss Federl Institute of Technology Zurich, Switzerlnd Emil:

More information

### 2N6071A/B Series. Silicon Bidirectional Thyristors TRIACS 4.0 A RMS, V

Preferred Device Sensitive Gte Trics Silicon Bidirectionl Thyristors Designed primrily for full wve AC control pplictions, such s light dimmers, motor controls, heting controls nd power supplies; or wherever

More information

### Engineer-to-Engineer Note

Engineer-to-Engineer Note EE-236 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our

More information

### SOLVING TRIANGLES USING THE SINE AND COSINE RULES

Mthemtics Revision Guides - Solving Generl Tringles - Sine nd Cosine Rules Pge 1 of 17 M.K. HOME TUITION Mthemtics Revision Guides Level: GCSE Higher Tier SOLVING TRIANGLES USING THE SINE AND COSINE RULES

More information

### Direct AC Generation from Solar Cell Arrays

Missouri University of Science nd Technology Scholrs' Mine UMR-MEC Conference 1975 Direct AC Genertion from Solr Cell Arrys Fernndo L. Alvrdo Follow this nd dditionl works t: http://scholrsmine.mst.edu/umr-mec

More information

### Homework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week

Announcements Homework #1 due Mondy t 6pm White drop ox in Student Lounge on the second floor of Cory Tuesdy ls cncelled next week Attend your other l slot Books on reserve in Bechtel Hmley, 2 nd nd 3

More information

### Electronic Circuits I - Tutorial 03 Diode Applications I

Electronic Circuits I - Tutoril 03 Diode Applictions I -1 / 9 - T & F # Question 1 A diode cn conduct current in two directions with equl ese. F 2 When reverse-bised, diode idelly ppers s short. F 3 A

More information

### APPLICATION NOTE. Introduction. Developing an Equation for the General Case. The Equation of a Straight Line

APPLICATION NOTE A Cookbook Approach to Single Supply DCCoupled Op Amp Design AN9757 Rev.1.00 Introduction Using op amps on a split power supply is straight forward because the op amp inputs are referenced

More information

### Section Thyristor converter driven DC motor drive

Section.3 - Thyristor converter driven DC motor drive.3.1 Introduction Controllble AC-DC converters using thyristors re perhps the most efficient nd most robust power converters for use in DC motor drives.

More information

### USER S MANUAL. Reference Documents. Key Features. Amplifier Configuration. Power Supplies (Figure 1) ISL2819xEVAL1Z. (Figure 2) Evaluation Board

USER S MANUAL ISL2819xEVAL1Z Evaluation Board The ISL2819xEVAL1Z evaluation board is a design platform containing all the circuitry needed to characterize critical performance parameters of the ISL2819

More information

### 9.4. ; 65. A family of curves has polar equations. ; 66. The astronomer Giovanni Cassini ( ) studied the family of curves with polar equations

54 CHAPTER 9 PARAMETRIC EQUATINS AND PLAR CRDINATES 49. r, 5. r sin 3, 5 54 Find the points on the given curve where the tngent line is horizontl or verticl. 5. r 3 cos 5. r e 53. r cos 54. r sin 55. Show

More information

### Section 16.3 Double Integrals over General Regions

Section 6.3 Double Integrls over Generl egions Not ever region is rectngle In the lst two sections we considered the problem of integrting function of two vribles over rectngle. This sitution however is

More information

### Spiral Tilings with C-curves

Spirl Tilings with -curves Using ombintorics to Augment Trdition hris K. Plmer 19 North Albny Avenue hicgo, Illinois, 0 chris@shdowfolds.com www.shdowfolds.com Abstrct Spirl tilings used by rtisns through

More information

### Joanna Towler, Roading Engineer, Professional Services, NZTA National Office Dave Bates, Operations Manager, NZTA National Office

. TECHNICA MEMOANDM To Cc repred By Endorsed By NZTA Network Mngement Consultnts nd Contrctors NZTA egionl Opertions Mngers nd Are Mngers Dve Btes, Opertions Mnger, NZTA Ntionl Office Jonn Towler, oding

More information

### Design And Implementation Of Luo Converter For Electric Vehicle Applications

Design And Implementtion Of Luo Converter For Electric Vehicle Applictions A.Mnikndn #1, N.Vdivel #2 ME (Power Electronics nd Drives) Deprtment of Electricl nd Electronics Engineering Sri Shkthi Institute

More information

### Lecture 20. Intro to line integrals. Dan Nichols MATH 233, Spring 2018 University of Massachusetts.

Lecture 2 Intro to line integrls Dn Nichols nichols@mth.umss.edu MATH 233, Spring 218 University of Msschusetts April 12, 218 (2) onservtive vector fields We wnt to determine if F P (x, y), Q(x, y) is

More information

### Safety Relay Unit. Main contacts Auxiliary contact Number of input channels Rated voltage Model Category. possible 24 VAC/VDC G9SA-501.

Sfety Rely Unit The Series Offers Complete Line-up of Compct Units. Four kinds of -mm wide Units re ville: A -pole model, -pole model, nd models with poles nd OFF-dely poles, s well s Two-hnd ler. Simple

More information

### Soft switched DC-DC PWM Converters

Soft switched DC-DC PWM Converters Mr.M. Prthp Rju (), Dr. A. Jy Lkshmi () Abstrct This pper presents n upgrded soft switching technique- zero current trnsition (ZCT), which gives better turn off chrcteristics

More information

### Engineer To Engineer Note

Engineer To Engineer Note EE-68 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: dsp.support@nlog.com Or visit our

More information

### Section 17.2: Line Integrals. 1 Objectives. 2 Assignments. 3 Maple Commands. 1. Compute line integrals in IR 2 and IR Read Section 17.

Section 7.: Line Integrls Objectives. ompute line integrls in IR nd IR 3. Assignments. Red Section 7.. Problems:,5,9,,3,7,,4 3. hllenge: 6,3,37 4. Red Section 7.3 3 Mple ommnds Mple cn ctully evlute line

More information

### Interference Cancellation Method without Feedback Amount for Three Users Interference Channel

Open Access Librry Journl 07, Volume, e57 ISSN Online: -97 ISSN Print: -9705 Interference Cncelltion Method without Feedbc Amount for Three Users Interference Chnnel Xini Tin, otin Zhng, Wenie Ji School

More information

### 1. Driver Functional Principle Receiver Functional Principle... 4

COMMON INFORMATION RS-485 TB506 Rev.0.00 Abstract The RS-485 standard specifies the electrical characteristics of differential drivers and receivers in multipoint networks but does not explain their functional

More information

### Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation

Lecture 16: Four Qudrnt opertion of DC Drive (or) TYPE E Four Qudrnt chopper Fed Drive: Opertion The rmture current I is either positive or negtive (flow in to or wy from rmture) the rmture voltge is lso

More information

### REVIEW QUESTIONS. Figure For Review Question Figure For Review Question Figure For Review Question 10.2.

HAPTE 0 Sinusoidl Stedy-Stte Anlysis 42 EVIEW QUESTIONS 0. The voltge cross the cpcitor in Fig. 0.43 is: () 5 0 V () 7.07 45 V (c) 7.07 45 V (d) 5 45 V Ω 0.5 efer to the circuit in Fig. 0.47 nd oserve

More information

### Experiment 3: The research of Thevenin theorem

Experiment 3: The reserch of Thevenin theorem 1. Purpose ) Vlidte Thevenin theorem; ) Mster the methods to mesure the equivlent prmeters of liner twoterminl ctive. c) Study the conditions of the mximum

More information

### PB-735 HD DP. Industrial Line. Automatic punch and bind machine for books and calendars

PB-735 HD DP Automtic punch nd bind mchine for books nd clendrs A further step for the utomtion of double loop binding. A clever nd flexible mchine ble to punch nd bind in line up to 9/16. Using the best

More information

### APPLICATION NOTE. Introduction. Features. Theory of Operation. Conclusions. Typical 3.3V Performance

APPLICATION NOTE A Complete Analog-to-Digital Converter AN9326 Rev. 0 Introduction The current data acquisition marketplace has an ever increasing demand for integrated circuits capable of operating with

More information

### Modeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter

Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp176-181) Modeling of onduction nd witching Losses in Three-Phse Asymmetric Multi-Level

More information

### Ultra Low Cost ACCELEROMETER

Chip Scle Pckged Fully Integrted Therml Accelerometer MXC622xXC Rev,A 8/19/2011 Pge 1 of 13 Fetures Generl Description Fully Integrted Therml Accelerometer X/Y Axis, 8 bit, Accelertion A/D Output (± 2g)

More information

### FATIGUE BEHAVIOUR OF COMPOSITE JOINTS WITH HEXAGON BOLTS

FATIGUE BEHAVIOUR OF COMPOSITE JOINTS WITH HEXAGON BOLTS Romn Strikov nd Jokim Schön Deprtment of Aeronutics, Royl Institute of Technology SE-1 44 Stockholm, Sweden Structures nd Mterils Deprtment, Aeronutics

More information

### FIGURE 1. BASIC STABILIZED OSCILLATOR LOOP

APPLICATION NOTE High-Purity Sinewave Oscillators With FN1088 Rev 0.00 While a wide variety of circuits and components are used to generate sinewaves, it has always been a challenge to produce spectrally

More information

### Robustness Analysis of Pulse Width Modulation Control of Motor Speed

Proceedings of the World Congress on Engineering nd Computer Science 2007 WCECS 2007, October 24-26, 2007, Sn Frncisco, USA obustness Anlysis of Pulse Width Modultion Control of Motor Speed Wei Zhn Abstrct

More information

### DYE SOLUBILITY IN SUPERCRITICAL CARBON DIOXIDE FLUID

THERMAL SCIENCE, Yer 2015, Vol. 19, No. 4, pp. 1311-1315 1311 DYE SOLUBILITY IN SUPERCRITICAL CARBON DIOXIDE FLUID by Jun YAN, Li-Jiu ZHENG *, Bing DU, Yong-Fng QIAN, nd Fng YE Lioning Provincil Key Lbortory

More information

### 10.4 AREAS AND LENGTHS IN POLAR COORDINATES

65 CHAPTER PARAMETRIC EQUATINS AND PLAR CRDINATES.4 AREAS AND LENGTHS IN PLAR CRDINATES In this section we develop the formul for the re of region whose oundry is given y polr eqution. We need to use the

More information

### Math Circles Finite Automata Question Sheet 3 (Solutions)

Mth Circles Finite Automt Question Sheet 3 (Solutions) Nickols Rollick nrollick@uwterloo.c Novemer 2, 28 Note: These solutions my give you the nswers to ll the prolems, ut they usully won t tell you how

More information

### Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)

The slides contin revisited mterils from: Peter Mrwedel, TU Dortmund Lothr Thiele, ETH Zurich Frnk Vhid, University of liforni, Riverside Dtflow Lnguge Model Drsticlly different wy of looking t computtion:

More information

### Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses

Eliminting Non-Determinism During of High-Speed Source Synchronous Differentil Buses Abstrct The t-speed functionl testing of deep sub-micron devices equipped with high-speed I/O ports nd the synchronous

More information

### Device installation. AFR 1xx - Feature Description of the Smart Load. AFR1xx 145 % 200 %

KM systems, s.r.o. Dr. M. Horákové 559, 460 06 Lierec 7, Czech Repulic tel. +420 485 130 314, fx +420 482 736 896 emil : km@km.cz, url : www.km.cz sturtion of the mgnetic circuit of the VT. This often

More information

### Ultra Low Cost ACCELEROMETER

Chip Scle Pckged Digitl Therml Orienttion Sensing Accelerometer MXC6226XC Document Version D Pge 1 of 13 Fetures Generl Description Fully Integrted Therml Accelerometer X/Y Axis, 8 bit, Accelertion A/D

More information

### Direct Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28.

P U Z Z L E R If ll these pplinces were operting t one time, circuit reker would proly e tripped, preventing potentilly dngerous sitution. Wht cuses circuit reker to trip when too mny electricl devices

More information

### TABLE 1. POLYPHASE DECIMATE-BY-2.5 CLOCKS FUNCTION CIC

APPLICATION NOTE Use of HSP216 QPDC for CDMA Applications (IS-9 and CDMA2) AN9928 Rev. Description This document will explain how to use Intersil s Quad Programmable Down Converter, HSP216, for CDMA2 applications.

More information

### EE Controls Lab #2: Implementing State-Transition Logic on a PLC

Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre

More information

### Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12

9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering http://www.eee.hku.hk/~engg5 Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil

More information

### Postprint. This is the accepted version of a paper presented at IEEE PES General Meeting.

http://www.div-portl.org Postprint This is the ccepted version of pper presented t IEEE PES Generl Meeting. Cittion for the originl published pper: Mhmood, F., Hooshyr, H., Vnfretti, L. (217) Sensitivity

More information

### Analog computation of wavelet transform coefficients in real-time Moreira-Tamayo, O.; Pineda de Gyvez, J.

Anlog computtion of wvelet trnsform coefficients in rel-time Moreir-Tmyo, O.; Pined de Gyvez, J. Published in: IEEE Trnsctions on Circuits nd Systems. I, Fundmentl Theory nd Applictions DOI: 0.09/8.558443

More information

### First Round Solutions Grades 4, 5, and 6

First Round Solutions Grdes 4, 5, nd 1) There re four bsic rectngles not mde up of smller ones There re three more rectngles mde up of two smller ones ech, two rectngles mde up of three smller ones ech,

More information

### USER S MANUAL. ISL284xxEVAL1Z. Introduction. Reference Documents. Evaluation Board Key Features. Amplifier Configuration (Figure 2)

USER S MANUAL Evaluation Board User Guide AN9 Rev. Introduction The evaluation board is a design platform containing all the circuitry needed to characterize critical performance parameters of the ISL87

More information

### Effect of High-speed Milling tool path strategies on the surface roughness of Stavax ESR mold insert machining

IOP Conference Series: Mterils Science nd Engineering PAPER OPEN ACCESS Effect of High-speed Milling tool pth strtegies on the surfce roughness of Stvx ESR mold insert mchining Relted content - Reserch

More information

### 2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media,

005 IEEE. Personl use of this mteril is permitted. Permission from IEEE must be obtined for ll other uses, in ny current or future medi, including reprinting/republishing this mteril for dvertising or

More information

### X I, X R, X I, X R. Clock 1: X R (0) C R (3)+X R (1) C R (2)+X R (2) C R (1)+X R (3)C R (0

APPLICATION NOTE Complex Filtering with the AN948 Rev.00 Apr 998 How to Use to Implement Complex Filtering The architecture of the allows for filtering of complex inputs. The output of the filtering operation

More information