A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure

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1 sensors Article A Low-Noise X-ry Astronomicl Silicon-On-Insultor Pixel Detector Using Pinned Depleted Diode Structure Hiroki Kmehm 1, Shoji Kwhito 2, *, Sumeet Shresth 2, Syunt Nknishi 2, Keit Ysutomi 2, Ayki Tked 3, Tkeshi Go Tsuru 4 Ysuo Ari 5 ID 1 Inmtion Communiction Systems Engineering, Ntionl Institute Technology, Okinw College, Okinw , Jpn; hkme@okinw-ct.c.jp 2 Reserch Institute Electronics, Shizuok University, Shizuok , Jpn; sumeet@idl.rie.shizuok.c.jp (S.S.); snkni@idl.rie.shizuok.c.jp (S.N.); kysu@idl.rie.shizuok.c.jp (K.Y.) 3 Deprtment Applied Physics Electronic Engineering, University Miyzki, Miyzki , Jpn; tked@stro.miyzki-u.c.jp 4 Deprtment Physics, Kyoto University, Kyoto , Jpn; tsuru@cr.scphys.kyoto-u.c.jp 5 High Energy Accelertor Reserch Orgniztion, Tsukub, Ibrki , Jpn; ysuo.ri@kek.jp * Correspondence: kwhito@idl.rie.shizuok.c.jp; Tel.: Received: 1 November 2017; Accepted: 20 December 2017; Published: 23 December 2017 Abstrct: This pper presents novel full-depletion Si X-ry detector bsed on silicon-on-insultor pixel (SOIPIX) technology using pinned depleted diode structure, nmed SOIPIX-PDD. SOIPIX-PDD gretly reduces stry cpcitnce t chrge sensing node, drk detector, cpcitive coupling between sensing node SOI circuits. se fetures SOIPIX-PDD led to low red noise, resulting high X-ry energy resolution stble opertion pixel. bck-gte surfce pinning structure using neutrlized p-well t bck-gte surfce depleted n-well underneth p-well ll pixel re or thn chrge sensing node is lso essentil preventing hole injection from p-well by mking potentil brrier to hole, reducing drk from Si-SiO 2 interfce creting lterl drift field to gr signl electrons in pixel re into smll chrge sensing node. A prototype chip using 0.2 µm SOI technology shows very low redout noise 11.0 e rms, low drk density 56 pa/cm 2 t 35 C energy resolution 200 ev(fwhm) t 5.9 kev 280 ev (FWHM) t kev. Keywords: SOI X-ry detector; high energy resolution; low noise; bck-side surfce potentil pinning structure 1. Introduction X-ry stronomicl stellites require low-noise high-time-resolution high-sptil-resolution detectors. X-ry chrge-coupled devices (CCDs) re ly used s strd imging devices becuse y fer Fno-limited spectroscopic permnce (~120 ev in FWHM t 6 kev) with low redout noise bout 3 e rms [1,2]. However, X-ry CCDs suffers from poor time resolution ( few seconds) low dynmic rnge ( kev) [3]. To meet requirements both low noise high time-resolution, complementry metl oxide semiconductor (CMOS)-bsed event-driven type detectors re being developed. One techniques to implement CMOS event-driven detectors is to use hybrid detector structure which uses stcking silicon detector CMOS redout electronics through Indium bump interconnections [4]. However, hybrid CMOS detectors hve limittion on lrge pixel number, smll pixel size, high production yield. Anor technique CMOS event-driven detectors is to use monolithic CMOS detector technology. Monolithic CMOS detectors do not require ny mechnicl bump bonding between detector redout circuits. Pixel Sensors 2018, 18, 27; doi: /s

2 Sensors 2017, 17, Sensors technology. 2018, 18, Monolithic 27 CMOS detectors do not require ny mechnicl bump bonding between 2 17 detector redout circuits. Pixel size cn be reltively smll higher sptil resolution. silicon-on-insultor pixel (SOIPIX) detector technology being developed by High Energy size Accelertor cn be Reserch reltively Orgniztion smll higher (KEK, sptil Ibrki, resolution. Jpn) Lpis silicon-on-insultor Semiconductor, Inc. pixel (Kngw, (SOIPIX) detector Jpn) is technology good pltm being developed implementing by High monolithic Energy Accelertor CMOS event-driven Reserch Orgniztion detector [3]. (KEK, Ibrki, SOIPIX Jpn) is n ctive Lpis pixel Semiconductor, sensor bsed on Inc. (Kngw, semiconductor Jpn) pixel is detector good pltm relized with implementing CMOS fully monolithic depleted CMOS (FD-) SOI event-driven technology. detector [3]. SOIPIX is n ctive pixel sensor bsed on semiconductor 1 shows pixel detector cross-sectionl relized with view CMOS fully SOIPIX. depleted SOI (FD-) wfer SOI is technology. composed thick, high-resistivity 1 shows substrte cross-sectionl sensing view prt thin SOIPIX. Si lyer SOI CMOS wfer circuits is composed swiched thick, by high-resistivity buried oxide (BOX) substrte lyer. SOIPIX sensing utilizes prt buried thin p-well Si lyer (BPW) CMOS s sensing circuits prt swiched to detect by X-rys buried [5]. Using oxide (BOX) 0.2 μm lyer. CMOS fully SOIPIX depleted utilizes (FD) buried SOI technology, p-well (BPW) we hve s been sensing developing prt to detect n event-driven X-rys [5]. X-ry Using pixel (XRPIX) 0.2 µm CMOS series [6 9]. fully depleted Though ir (FD) bsic SOI technology, chrcteristics we hve hve been been developing grdully improved, n event-driven re still X-ry re issues pixel on (XRPIX) improvements series [6 9]. Though noise, chrge ir bsic correction chrcteristics efficiency, hve been resulting grdully X-ry improved, energy re resolution. still re issues ltest on version improvements XRPIX clled noise, chrge XRPIX3b correction uses efficiency, chrge-sensitive mplifier resulting (CSA) X-ry energy circuit resolution. in ech pixel to ltest increse version conversion XRPIX clled gin XRPIX3b reduce uses redout chrge-sensitive noise. mplifier XRPIX3b (CSA) hs chieved circuit in ech redout pixel noise to increse 35 e conversion gin reduce redout noise. XRPIX3b hs chieved redout noise 35 e rms energy resolution 320 ev (FWHM) t 6 kev [9]. detector structure used XRPIX3b, rms however, energy hs resolution difficulty 320 reduction ev (FWHM) t 6 sensing-node kev [9]. cpcitnce, detector structure problem used crosstlk XRPIX3b, between however, sensing hs node difficulty SOI reduction CMOS circuits, sensing-node drk cpcitnce, genertion problem t crosstlk between sensing node Si-SiO2 interfce under BOX. To solve SOI crosstlk CMOS problem, circuits, n SOIPIX drk technology genertion using t nested-well Si-SiO 2 interfce structure under hs been proposed BOX. To solve [10]. Though crosstlk this technique problem, n is effective SOIPIX technology reducing using crosstlk nested-well problem, structure nested-well hs been proposed structure [10]. still Though hs n issue this technique on lrge is effective cpcitnce reducing t sensing crosstlk node. problem, SOIPIX nested-well using double structure SOI lyers still hs recently n issue reported on is lrge n ttrctive cpcitnce device t sensing relizing node. low-noise SOIPIX detector using tht double exploits SOI lyers merits recently reported middle is n Si ttrctive lyer (middle device SOI) relizing reducing low-noise crosstlk detector by shielding tht exploits sensing merits node from middle Si SOI lyer circuits (middle SOI) reducing reducing sensing-node crosstlk cpcitnce by shielding with sensing structure node from depleted SOI substrte circuits Si surfce reducing sensing-node cpcitnce with structure depleted substrte Si surfce (Si-SiO2 interfce under BOX lyer) [11]. However, it still hs issues on drk (Si-SiO genertion 2 interfce t under depleted substrte BOX lyer) Si [11]. surfce, However, possibility it still hs issues signl on chrge drk loss by genertion trps t depleted Si surfce, substrte leding to Si surfce, degrded chrge possibility collection signl efficiency. chrge loss by trps t Si surfce, leding to degrded chrge collection efficiency. 1. cross-sectionl view SOIPIX. In order to relize n X-ry pixelted detector with high energy resolution bsed on SOIPIX technology, this pper proposes novel SOIPIX using pinned depleted diode structure. This pixel technology clled SOIPIX-PDD llows us to solve issues conventionl SOIPIXs ssocited with redout noise, noise, drk drk,, crosstlk, crosstlk, chrge chrge collection collection efficiency, efficiency, while hving while hving feture feture fully depleted fully depleted thick sensing thick sensing region region hle substrte hle substrte which iswhich commonly is commonly required required high energy high imging energy [12 14]. imging Thnks [12 14]. tothnks pinned to depleted pinned diode depleted structure diode hving structure fetures hving fetures pinned Si surfce pinned lyersi which surfce lsolyer ctswhich s n electro-sttic lso cts s shielding n electro-sttic lyer shielding depletedlyer buried chnnel depleted buried crrier collection chnnel tocrrier smll-cpcitnce collection to chrge smll-cpcitnce sensing node, chrge drksensing node, t substrte drk Si surfce, t substrte redout noise Si surfce, crosstlk redout noise re gretly crosstlk reduced. re This gretly structure reduced. is lso This effective structure is high lso effective chrge collection high efficiency high-speed response becuse signl crriers collected run in buried chnnel

3 Sensors 2017, 17, Sensors 2018, 18, chrge collection efficiency high-speed response becuse signl crriers collected run in buried chnnel with help lterl electro-sttic field but without touching to Si surfce. with help lterl electro-sttic field but without touching to Si surfce. rest this rest this pper describes pixel device structure, pixel circuits, implementtion evlution pper describes pixel device structure, pixel circuits, implementtion evlution results results SOIPIX-PDD, finlly conclusions. SOIPIX-PDD, finlly conclusions. 2. SOI Pixel Detector Using Pinned Depleted Diode Structure 2.1. Sensor Structure Implemented on High-Resistivity Substrte In conventionl SOIPIX s shown in 1, chrge sensing node is mde with BPW t bck-gte surfce high-resistivity Si substrte or prt bck-gte surfce is depleted. This depleted bck-gte surfce leds to lrge drk chrge loss due to interfce sttes. To To increse chrge chrge collection collection efficiency, efficiency, size size detector detector BPW must BPW be incresed must be incresed resulting cpcitnce resulting cpcitnce detector is incresed, detector is leding incresed, to leding lrge cpcitnce to lrge cpcitnce sensing node. sensing cpcitive node. coupling cpcitive between coupling between SOI circuits SOI circuits buried BPW my buried cuse BPW nmy dditionl cuse noise n dditionl fset. noise To reduce fset. cpcitive To reduce coupling cpcitive between coupling sensing between node (BPW) sensing node SOI circuits, (BPW) nested-well SOI circuits, structure nested-well bsed on structure SOIPIX bsed hs on been SOIPIX proposed hs [10,15]. been proposed However, [10,15]. nested-well However, structure nested-well uses lrge-size structure sensing uses lrge-size plte mdesensing with neutrlized plte mde BPWwith creted neutrlized underneth BPW creted buried n-well underneth (BNW) buried n-well cpcitnce (BNW) sensing cpcitnce node becomes sensing pretty lrge. node becomes pretty lrge. SOIPIX using pinned pinned depleted depleted diode diode structure, structure, SOIPIX-PDD, SOIPIX-PDD, is developed is developed to improve to improve detector permnce detector permnce compred with compred conventionl with SOI conventionl pixel detector SOI while pixel mintining detector while fundmentl mintining merit fundmentl SOIPIX merit [16]. SOIPIX 2 shows [16]. cross-sectionl 2 shows cross-sectionl view SOIPIX-PDD. view For SOIPIX-PDD. X-ry imging, For X-ry highimging, negtivehigh voltge negtive is pplied voltge t is pplied bckside t bckside detector detector ttining fully ttining depleted fully thick depleted substrte. thick Asubstrte. BPW is med A BPW onis med bckside on bckside BOX pinning BOX bck-gte pinning voltge bck-gte voltge SOI trnsistors SOI totrnsistors fixed bis to fixed V BB2. bis BPW VBB2. cts s BPW shielding cts s shielding lyer between lyer between chrge sensing chrge node sensing node SOI circuits, SOI preventing circuits, preventing extr noise extr fset noise genertion fset by genertion coupling. by coupling. 2. Cross-sectionl view SOIPIX-PDD. 2. Cross-sectionl view SOIPIX-PDD. sufficiently highly-doped BPW s neutrl region is effective reducing drk genertion t Si-SiO2 2 interfce under BOX, becuseit it works like like pinned pinned photodiode in CCD in CCD or or CMOS CMOS imge imge sensors sensors [17]. [17]. A BNW A BNW med med under under BPW BPW is depleted is depleted this lyer thiscts lyer s cts buried s buried chnnel chnnel to gr to crriers gr crriers generted generted in pixel in into pixel into sensing sensing node (n+) node (n+) to improve to improve chrge chrge collection collection efficiency, efficiency, becuse becuse lterl electric lterl field electric is creted field isin creted this chnnel in thiss chnnel shown s in shown potentil in prile X1-X1 problem crrier trpping t Si-SiO2 interfce under BOX in

4 Sensors 2018, 18, Sensors 2017, 17, potentil prile X 1 -X 1 problem crrier trpping t Si-SiO 2 interfce under BOX in conventionl SOIPIX SOIPIX is solved is solved by by buried chnnel structure. One importnt design issue is to minimize lekge from from BPW BPW to to bck-side bck-side p+ lyer p+ by lyer creting by creting sufficient sufficient potentil brrier potentil ϕ b brrier to holes b sto shown holes in s shown 2. in Cross-sectionl view SOIPIX-PDD with multiple buried wells. SOIPIX-PDD shown shown in in 2 uses 2 uses single single BNW BNW creting creting chnnel chnnel with lterl with electric lterl field. electric If field. pixel If sizepixel is very size lrge, is very electric lrge, field electric creted field by this creted BNWby only this my BNW not only be sufficient my not be gring sufficient chrges gring withinchrges time to within meet time required to meet X-ry required photon incidentl X-ry photon rte incidentl >1 MHz. rte In order >1 to MHz. crete In order sufficiently to crete lrge sufficiently lterl electric lrge lterl field inelectric wholefield detector in whole volume, detector multiple volume, buried-well multiple structure buried-well structure PDD s shown PDD ins shown 3 is in used. In3 this used. detector, In this detector, lterl electric lterl fieldelectric in chnnel field in is creted chnnel byis two creted buriedby p-well two buried (BPW1p-well BPW2) (BPW1 three BPW2) buried n-well three (BNW1, buried BNW2 n-well (BNW1, BNW3) BNW2 re used. BNW3) Since re BNW3, used. Since BNW2 BNW3, BNW1BNW2 under BPW BNW1 re under depleted, BPW chrge re sensing depleted, cpcitnce chrge sensing detector cpcitnce is only due to detector PN junction is only between due to BPW PN junction n+ between prt BPW BNW ner n+ n+, high prt chrge-to-voltge BNW ner conversion n+, high gin chrge-to-voltge resulting conversion low redout gin noise re relized. resulting low redout noise re relized Simultion Potentil Priles Designed SOIPIX-PDD Bsed on pinned depleted diode with multiple buried wells, pixel detector X-ry energy spectrum mesurements is designed its potentil priles re simulted by device simultor SPECTRA. 4 shows pixel lyout pttern pttern detector. detector. pixel size pixel size detector detector is 36 μm is 36 µm μm. A 36 p+ µm. lyer Ais p+ med lyer t is med boundry t boundry pixel to bis pixel BPW1 to bis pinning BPW1 bck-gte pinning bck-gte SOI circuits to SOI VBB2. circuits pttern to V BB2 edges. pttern multiple edgesburied p-/n-wells multiple buried re locted p-/n-wells t 1.5 μm re locted BNW1 t 1.5 (octgonl, µm BNW1 positive (octgonl, tone), t positive 2.7 μm tone), BPW1 t 2.7 µm (octgonl, BPW1 negtive (octgonl, tone), negtive 9 μm tone), t BPW2 9 µm(octgonl, BPW2 (octgonl, negtive tone), negtive 13.5 μm tone), 13.5 BNW2 µm (octgonl, BNW2 (octgonl, positive tone). positive tone). BNW3 covers BNW3 ll covers pixel llre pixel (36 μm re 36 (36 μm). µm 36 thickness µm). thickness sensor lyer sensor (p-type lyer substrte) (p-type is 200 substrte) μm. is 200 voltges µm. pplied voltges t pplied sensing node t (n+), sensing bck-gte node (n+), bck-gte SOI (p+, BPW1), SOI (p+, substrte BPW1), bckside substrte p+ (Vbck) bckside re set to p+ 3 V, (V bck 4 V ) re (= VBB2) set to 3 V, 15 4 V (= (= VBB), V BB2 respectively. ) 15 V (= V BB ), respectively.

5 Sensors 2018, 18, Sensors 2017, 17, Sensor-lyer Sensor-lyer ptterns ptterns dimensions dimensions buried buried n-/p-wells. n-/p-wells. 5 shows simulted potentil priles priles designed designed SOIPIX-PDD SOIPIX-PDD with multiple with multiple buried wells. buried wells. 5,b show 5,b potentil show distribution potentil distribution verticl cross-sections verticl cross-sections long Z 1 -Z 1, Zlong 2 -Z 2, Z1-Z1, Z 3 3 Z2-Z2, Z 4 Z3-Z3 4 Z4-Z4 3. entire 3. sensor entire lyer sensor is fully lyer depleted is fully from depleted surfce from to surfce bckside. to bckside. 5b is zoomed 5 (b) potentil is zoomed distribution potentil from distribution depth from surfce depth to 10 µm. surfce In cross-section to 10 μm. In Z 4 cross-section -Z 4, potentil Z4-Z4, prile tht potentil crriers prile generted tht crriers in deep generted inside in silicon deep is directly inside trnsferred silicon is to directly n+ trnsferred sensing node. to In n+ sensing cross-sections node. In Z 1 -Z cross-sections 1, Z 2 -Z 2 Z 3 Z1-Z1, 3 Z2-Z2 bck-gte Z3-Z3, surfce is pinned bck-gte to surfce pplied is pinned voltge to (= 4 pplied V) to voltge BPW1, (= while 4 V) creting to BPW1, potentil while brrier creting ϕ b potentil lrger thn brrier 2 V, b which lrger is sufficiently thn 2 V, which lrge to is prevent sufficiently hole lrge injection to prevent from hole BPW1. injection As shown from in BPW1. 5b, As shown ctul in potentil 5b, ctul neutrl potentil region neutrl BPW1 (= region 4.4 V) includes BPW1 Fermi (= 4.4 potentil V) includes 0.4 Fermi V. In potentil cross-sections 0.4 V. In Z 2 -Z cross-sections 2, Z 3 -Z 3 Z Z2-Z2, 4 4 Z3-Z3 crriers Z4-Z4, generted t crriers deep inside generted silicon t deep is once inside coming silicon to is ner once surfce coming (buried to chnnel) ner surfce n (buried horizontlly chnnel) trnsferred n to horizontlly n+ sensing node trnsferred through to chnnel. n+ sensing node 6 shows through horizontl chnnel. potentil 6 priles shows t horizontl cross-sections potentil Xpriles 1 -X 1 t X 2 -X cross-sections 2. potentil X1-X1 prile X2-X2. X 2 2 shows potentil bck-gte prile (BPW1) X2-X2 shows is pinned to bck-gte 4.4 V. As (BPW1) shown is pinned potentil to 4.4 V. X 1 As -X 1 shown, lterl in electric potentil field is med X1-X1, to collect lterl photoelectrons electric field is in med pixel to to collect n+ photoelectrons sensing node. in pixel 7 is to 2-D potentil n+ sensing plot node. t ner Si 7 substrte is 2-D potentil surfce (Z plot = 0 t to ner 10 µm). Si substrte simulted surfce 2-D potentil (Z = 0 to plot 10 μm). SOIPIX-PDD simulted using 2-D potentil multi-well plot structure SOIPIX-PDD shows tht ll using electrons multi-well generted structure from shows tht surfce ll to bottom electrons generted pixel re from gred surfce to to n+ bottom sensing node pixel through re gred depleted to 3-D n+ potentil sensing prile node through (X-Y-Z) depleted detector, 3-D relizing potentil high prile chrge (X-Y-Z) collection efficiency detector, which relizing is indicted high chrge by collection shpe efficiency potentil which prile is tht indicted collect by crriers shpe generted potentil in prile entire 3-D tht volume collect crriers pixel generted into in n+ sensing entire 3-D node. volume pixel into n+ sensing node. () (b) 5. Simulted Verticl Potentil Priles, () Z = 0 to 200 µm, (b) Z = 0 to 10 µm. 5. Simulted Verticl Potentil Priles, () Z = 0 to 200 μm, (b) Z = 0 to 10 μm.

6 Sensors 2018, 18, Sensors 2017, 17, Sensors 2017, 17, Sensors 2017, 17, Simulted Horizontl Potentil Priles. 6. Simulted Horizontl Potentil Priles. 6. Simulted Horizontl Potentil Priles. 6. Simulted Horizontl Potentil Priles. () () (b) (b) 7. 2-D (X-Z) Equipotentil plot () Bird s Eye View 2-D (X-Z) Potentil (b). () (b) Potentil 7. 2-D (X-Z) Equipotentil plot()() Bird s Bird seye EyeView View 2-D 2-D (X-Z) 7. 2-D (X-Z) Equipotentil plot (X-Z) Potentil(b). (b). cpcitnce n+ sensing node denoted by CD cn be estimted by qusi-fermi level 7. 2-D (X-Z) Equipotentil plot () Bird s Eye View 2-D (X-Z) Potentil (b). cpcitnce n+ sensing node denoted by CD cncpcitnce be estimtedby qusi-fermi level is given by: chnge resulting chnge ccumulted electrons. CD cpcitnce n+ sensing node denoted by CD cn estimtedby qusi-fermi level is given by: chnge resulting chnge ccumulted electrons. be cpcitnce CD cpcitnce n+ sensing node denoted by C D cn be estimted by qusi-fermi level Q sig chnge resulting chnge ccumulted cpcitnce CD is given by: CD =electrons. (1) chnge resulting chnge ccumulted electrons. Qsig cpcitnce CD is given by: Δ V Nfermi CD = (1) ΔQ sig Nfermi QVsig C = (1) From simultion results 8, CD is estimted where, Qsig is qusi-ccumulted electrons.dc (1) D = V N f ermi Δ V 19 Nfermi sig N is qusi-ccumulted From simultion results 8, CD is estimted towhere, be CD =Q(q sig)/ VNfermi = (1.602 electrons ,900)/ ff. to be C D = (q Nsig)/ VNfermi = ( ,900)/ ff. where, QsigQis electrons. estimted to sig qusi-ccumulted is qusi-ccumulted electrons.from From simultion simultionresults results 8, 8, CCDD is estimted where, 19 19,900)/ ff. 19 be C =C (qd N )/ V = ( todbe = (qsig N sig)/ V Nfermi = 10 19,900)/ ff. = Nfermi 8. Estimtion CD. 8. Estimtion CD. 8. Estimtion CD. 8. Estimtion CD.

7 Sensors 2017, 17, Chrge-Sensitive Amplifier Design Low-Noise Pixelted Detectors Sensors 2018, 18, shows equivlent circuits chrge-sensitive mplifier (CSA) in pixel 3. including Chrge-Sensitive model Amplifier SOI Design substrte detector. Low-Noise In Pixelted SOIPIX-PDD, Detectors SOI substrte detector is modeled with two diodes, D1 D2, stry cpcitnce CD t n+ chrge sensing node substrte detector. 9 shows equivlent chrge-to-voltge circuits conversion chrge-sensitive gin mplifier CSA is given (CSA) by in pixel including model SOI substrte detector. In SOIPIX-PDD, SOI substrte detector is modeled with two diodes, D 1 D 2, stry cpcitnce CG D AMP G = t n+ chrge sensing node substrte C q detector. chrge-to-voltge conversion gin C + C + CSA Gis given by (2) D where CI is input cpcitnce internl Gmplifier, G C = q AMP CFB is feedbck cpcitnce (2) CSA, GAMP is DC open-loop gin Cinternl D + C I + mplifier, C FB G AMP q is elementry chrge. If GAMP >>1, it is pproximted s: where C I is input cpcitnce internl mplifier, C FB is feedbck cpcitnce CSA, G AMP is DC open-loop gin internl mplifier, q q is elementry chrge. If G AMP >>1, GC = (3) it is pproximted s: C G C = q FB (3) conversion gin is solely determined by C CFB with lrge gin internl mplifier, ree very sensitive CSA is relized if CFB is designed to be very smll. I FB AMP () (b) (c) 9. Equivlent circuits CSA in pixel. () Model CSA including those substrte 9. Equivlent circuits CSA in pixel. () Model CSA including those detector, (b) internl mplifier, (c) Equivlent redout circuits chin including pixel peripherl. substrte detector, (b) internl mplifier, (c) Equivlent redout circuits chin including pixel peripherl. conversion gin is solely determined by C FB with lrge gin internl mplifier, ree very sensitive CSA is relized if C timing pixel opertion FB is designed to be very smll. is shown in 10. CSA with pinned depleted timing pixel opertion is shown in 10. CSA with pinned depleted diode diode detector (PDD) cn be used n event-driven type pixel using n in-pixel comprtor s detector (PDD) cn be used n event-driven type pixel using n in-pixel comprtor s used in [9]. used in [9]. To evlute detector s bsic chrcteristics, simple integrtion type opertion is To evlute detector s bsic chrcteristics, simple integrtion type opertion is used here. A PMOS reset trnsistor is used better dynmic rnge. After reset switch is turned f, re is

8 used here. A PMOS reset trnsistor is used better dynmic rnge. After reset switch is turned f, re is chrge injection from reset trnsistor. chrge injection by reset trnsistor is controlled by proper choice trnsistor size low-level voltge pplied to reset trnsistor. operting point mplifier is shifted to reltively low level 0.9 V by chrge injection t output mplifier. Sensors 2018, 18, After reset opertion, reset level CSA output is smpled t smple--hold cpcitor CS, n detector ( CSA) wits n event X-ry injection during chrge ccumultion injectiontime fromshown reset in trnsistor. 10. After chrge tht, injection signl by level reset trnsistor CSA output is controlled is smpled byt proper CS gin. choice Using switched-cpcitor trnsistor size low-level CDS circuit voltge in pplied peripherl to reset circuits, trnsistor. CDS (correlted operting point double smpling) mplifier is cncelling shifted to reltively reset noise low level CSA 0.9 Vcn by be crried chrge out. injection To do tthis, output reset mplifier. signl levels CSA output smpled in CS re red out to peripherl CDS circuit. 10. Pixel Timing Digrm. use very smll cpcitnce CFB After reset opertion, reset level CSA resulting output high isconversion smpled tgin smple--hold re effective cpcitor reducing C noises superimposed fter CSA such s those n in-pixel source follower buffer, S, n detector ( CSA) wits n event X-ry injection during ccumultion peripherl redout time shown circuits, in output 10. buffer Aftermplifier, tht, signl A-to-D level converter. CSA output n, is smpled noise t C S gin. CSA is Using dominted switched-cpcitor by cpcitnce CDS circuit inchrge peripherl sensing node circuits, CDS PDD (correlted detector double smpling) design internl cncelling mplifier. reset noise input-referred CSA cn noise be crried designed out. To docsa this, shown reset in signl 9 is levels pproximtely CSAexpressed output smpled s: in C S re red out to peripherl CDS circuit. use very smll cpcitnce C FB resulting high conversion gin re effective 2 1 ξ N AkT B f T CDS reducing noises superimposed Nn= fter CSA such + s ε + ln G 2 those n in-pixel source follower buffer, (4) peripherl redout circuits, output buffer C mplifier, βf C S βfa-to-d converter. τcsa n, noise CSA is dominted by cpcitnce chrge sensing node PDD detector design where ξa is excess rml noise fctor internl mplifier, TCDS time difference internl mplifier. input-referred noise designed CSA shown in 9 is pproximtely two smples in correlted double smpling opertion used in reset noise cncelling expressed s: CSA, Nf flicker noise coefficient input trnsistor internl mplifier, ε = Euler s constnt, kb Boltzmnn s constnt 2 1 T ξ bsolute temperture, βf N n = A k B T + N ( f ε + ln T ) CDS feedbck fctor (4) CSA given by: G C β F C S β 2 F τ CSA where ξ A is excess rml noise fctor internl C mplifier, T CDS time difference FB two smples in correlted double smpling βf = (5) C opertion FB + CD + used C in reset noise cncelling CSA, I N f flicker noise coefficient input trnsistor internl mplifier, ε = Euler s constnt, τcsa k B time Boltzmnn s constnt tht constnt determines T response bsolute time temperture, CSA βwhich F feedbck is given by fctor CSA given by: S τcsa= C β F = FB (6) (5) C FB + gma C D βf+ C I where τ CSA gma is time trns-conductnce constnt tht determines internl response mplifier time [18,19]. CSA which first is given second by terms in squre root Eqution (4) is due to rml flicker (1/f) noises CSA, respectively. Eqution. (4) indictes tht noise is much τ CSA dependent = C S on βf or rtio CFB to CD + CI. For (6) g ma β F low-noise CSA, reduction CD CI is very importnt while using smll CFB high where g ma is trns-conductnce internl mplifier [18,19]. first second terms in squre root Eqution (4) is due to rml flicker (1/f) noises CSA, respectively. Eqution (4) indictes tht noise is much dependent on β F or rtio C FB to C D + C I. For low-noise CSA, reduction C D C I is very importnt while using smll C FB high conversion gin. eft highly-sensitive substrte detector described in Section 2 reduces C D. input

9 Sensors 2017, 17, Sensors 2018, 18, conversion gin. eft highly-sensitive substrte detector described in Section 2 reduces CD. input cpcitnce internl mplifier CI is inversely proportionl to size (chnnel length cpcitnce internl mplifier C I is inversely proportionl to size (chnnel length (L) times (L) times chnnel width (W)) input trnsistor (MP1 9b). flicker noise coefficient Nf is chnnel width (W)) input trnsistor (MP1 9b). flicker noise coefficient N f is lso lso inversely proportionl to size (LW) MP1 if noises due to or trnsistors (MP2, MN2, inversely proportionl to size (LW) MP1 if noises due to or trnsistors (MP2, MN2, MN3) re not influenced. ree re exists n optiml choice size MP1 to minimize MN3) re not influenced. ree re exists n optiml choice size MP1 to minimize input-referred noise depending on CD, CFB or prmeters tht influence Eqution (4). input-referred noise depending on C D, C FB or prmeters tht influence Eqution (4). 11 shows clculted input-referred noise s function trnsistor size MP1 with CD 11 shows clculted input-referred noise s function trnsistor size MP1 with C D s s prmeter. prmeter. In In this this clcultion, clcultion, CFB C FB =1.5 =1.5 [ff], [ff], TCDS T CDS = = 11 [ms], [ms], τ CSA τ CSA =0.2 =0.2 µs, μs, CS C S = 240 = [ff] 240 [ff] or prmeters or prmeters re picked re up picked by up PDK by PDK 0.2 µm SOI technology. 0.2 μm SOI According technology. to According simultion results to simultion PDD detector, results C D is PDD estimted detector, to becd 3.2is ff. estimted From to be ff. with From optimum 11 trnsistor with size (WL optimum = 0.36 trnsistor µm 2 ), size noise (WL level = μme 2 ), rms. noise expected. level However, 4.1 e rms. this expected. noise is criticlly However, incresed this noise if is criticlly flicker noise incresed trnsistors if flicker is lrger noise thn trnsistors tht usedis inlrger this clcultion. thn tht used in usethis lrger clcultion. trnsistor use size leds lrger to lower trnsistor flicker size noise leds to robust lower flicker to noise noise increse. robust design to noise increse. CSA implementtion design CSA uses WL implementtion = 1.0 µm 2 MP1 uses WL = 1.0 expected μm 2 noise MP1 level is 4.5expected e rms. noise level is 4.5 e rms. 11. Input-referred Noise s Function LW MP1 CCD. D. 4. Implementtion Mesurements An experimentl chip to evlute pixel permnce SOIPIX-PDD ws mnufctured using µmμm SOI SOI technology technology s summrized s summrized in Tble 1. in Tble 121. shows 12 chip shows microphotogrph chip microphotogrph sensor chip. chip sensor includes chip. 6 6 chip = 36includes types 6 pixel 6 = rrys 36 types ech pixel which rrys hsech 8 (V) which 7 (H) pixels hs 8 (V) respective 7 (H) pixels redout respective circuits s redout shown incircuits s 12b. shown pixel in size is12b. 36 µm pixel 36 µm. size All is 36 μm circuits 36 μm. test All elements circuits re implemented test elements in re chipimplemented die size 4.45 in mm chip 4.45die mm. size In 4.45 following mm 4.45 mesurement mm. In results, following 8 mesurement 7 pixel rry results, strd 8 design 7 pixel whose rry detector strd dimensions design whose circuit prmeters detector dimensions re described circuit in Section prmeters 3 is used. re described in Section 3 is used. Process Tble 1. SOIPIX Process Technology µm FD-SOI CMOS Technology with Substrte-Detector Process Substrte thickness 200 µm Wfer type FZ-p (Floting Zone, p-type) Substrte Resistivity >25 kωcm

10 Sensors 2018, 18, Sensors 2017, 17, () Photo microgrph (b) Block digrm circuits Implemented Implemented chip. chip Bsic Chrcteristics SOI Pxel with Pnned Depleted Diode Structure 4.1. Bsic Chrcteristics SOI Pxel with Pnned Depleted Diode Structure Bsic chrcteristics proposed pixel using SOI technology with PDD structure s Bsic chrcteristics proposed pixel using SOI technology with PDD structure s substrte detector re mesured. In following mesurement results if not stted, pplied substrte detector re mesured. In following mesurement results if not stted, pplied bckside bis (VBB) is 60 V, surfce-side bck-gte bis (VBB2) is 2 V, power supply voltge bckside bis (V BB ) is 60 V, surfce-side bck-gte bis (V BB2 ) is 2 V, power supply voltge nlog/digitl pixel circuits is 3V. pixel loction (x = 2, y = 5) if not stted is picked up nlog/digitl pixel circuits is 3V. pixel loction (x = 2, y = 5) if not stted is picked up pixel chrcteriztion becuse verge noise level is obtined t this pixel s shown in pixel chrcteriztion becuse verge noise level is obtined t this pixel s shown in 17 below. 17 below. implemented pixel hs event-driven circuits using comprtor logic gtes toger with Tble 1. SOIPIX Process Technology. chrge mplifier nlog redout circuits cse testing n event-driven type X-ry energy spectrum mesurements [20]. In mesurement 0.20 µm FD-SOI results CMOS throughout technology this pper, however, Process function event detection event-drivenwith mesurements Substrte-Detector is not used Process becuse scope this pper is to chrcterize Substrte bsic thickness pixel permnce. 200 μm Wfer type FZ-p (Floting Zone, p-type) Linerity Conversion Gin Substrte Resistivity >25 k cm 13 shows linerity mesurement pixel two bckside bises (V BB ) 10 V 60 V. implemented A white light pixel generted hs event-driven intensity-scnned circuits using by comprtor n LB-8611A precision logic gtes lighting toger box (Kyoritsu, with chrge Tokyo, mplifier Jpn) is used nlog redout linerity circuits mesurements. cse testing light is n illuminted event-driven from type bckside X-ry energy spectrum chip. With mesurements thick (200 µm) [20]. high-resistivity In mesurement (25 kωcm) results substrte, throughout substrte this ispper, fully depleted however, by Vfunction BB higher event thn detection 14.4 V. For V BB event-driven 10 V, mesurements linerity sensitivity is not used is poor becuse becuse scope incomplete this pper depletion is to chrcterize substrte. With bsic pixel fully-depleted permnce. bising V BB = 60 V, good linerity is obtined in output rnge up to 0.6 V Linerity 14 shows Conversion noise s Gin function signl mplitude mesurement conversion gin. Photon shot noise is used mesurement conversion gin [21]. From cross point 13 shows linerity mesurement pixel two bckside bises (VBB) 10 signl voltge shot noise voltge, conversion gin is mesured to be 70 µv/e. V 60 V. A white light generted intensity-scnned by n LB-8611A precision lighting box (Kyoritsu, Tokyo, Jpn) is used linerity mesurements. light is illuminted from

11 becuse incomplete depletion substrte. With fully-depleted bising VBB = 60 V, becuse incomplete depletion substrte. With fully-depleted bising VBB = 60 V, good linerity is obtined in output rnge up to 0.6 V. good linerity is obtined in output rnge up to 0.6 V. 14 shows noise s function signl mplitude mesurement conversion 14 shows noise s function signl mplitude mesurement conversion gin. Photon shot noise is used mesurement conversion gin [21]. From cross point gin. Photon shot noise is used mesurement conversion gin [21]. From cross point signl shot noise voltge, conversion gin is mesured to be 70 μv/e. Sensors 2018, voltge 18, signl voltge shot noise voltge, conversion gin is mesured to be 70 μv/e. 13. Linerity pixel output to light intensity Linerity Linerity pixel pixeloutput outputtotolight lightintensity. intensity. 14. Noise versus signl conversion gin mesurement. 14. Noise versus signl conversion gin mesurement. 14. Noise versus signl conversion gin mesurement Drk DrkCurrent Current Drk Current 15 15shows shows temperture temperturedependence dependencedrk drk SOIPIX-PDD. SOIPIX-PDD. drk drk 15 shows temperture dependence drk SOIPIX-PDD. drk conventionl SOI pixel [9] is lso shown comprison. For comprison t mbient conventionl SOI pixel [9] is lso shown comprison. For comprison t conventionl SOI pixel [9] is lso shown comprison. For comprison t C, temperture round 25round SOIPIX-PDD hs 100 times drk density thn tht mbient temperture 25 C, SOIPIX-PDD hs smller 100 times smller drk density mbient temperture round 25 C, SOIPIX-PDD hs 100 times smller drk density thn tht conventionl SOI pixel. This showsthis shows effectiveness pinned depleted structure conventionl SOI pixel. effectiveness pinneddiode depleted diode thn tht conventionl SOI pixel. This shows effectiveness pinned depleted diode using neutrlized BPW lyer creted just under BOX to fill surfce with holes reduction structure using neutrlized BPW lyer creted just under BOX to fill surfce with holes structure using neutrlized BPW lyer creted just under BOX to fill surfce with holes C, or reduction drk.. temperture rnge higher rnge thn 5 smller [1/K] For drk For temperture higher thn thn 5 C, 3.6/1000 or smller thn reduction drk. For temperture rnge higher thn 5 C, or smller thn in3.6/1000 Arrhenius it follows line ctivtion energy drk 0.56 ev, hlfis [1/K] inplot, Arrhenius plot, it tht follows line tht ctivtion energyis drk 3.6/1000 [1/K] in Arrhenius plot, it follows line tht ctivtion energy drk is 0.56 b 1.12 ev)b silicon, dominnt drktht componentdrk is still due ev,gp (=hlf gp (=indicting 1.12 ev) tht silicon, indicting dominnt 0.56 ev, hlf b gp (= 1.12 ev) silicon, indicting tht dominnt drk to SRH genertion detector. For temperture rnge smller thn 5 C, or lrger thn 3.6/1000 [1/K] in Arrhenius plot, temperture dependency tends to sturte it tkes 56 [pa/cm2 ] t 35 C. reson this limittion drk reduction t low temperture is not cler t moment, but possible reson is lekge p-mos trnsistor used resetting sensing node. This is becuse trp-ssisted b-to-b tunneling, which is ten mjor mechnism lekge MOS trnsistor, hs smll temperture dependence.

12 component is still due to SRH genertion detector. For temperture rnge smller thn thn 5 C, 5 C, or or lrger lrger thn thn 3.6/1000 [1/K] [1/K] in in Arrhenius plot, plot, temperture dependency tends tends to to sturte it tkes it tkes [pa/cm 2 ] t 2 ] t C. C. reson this this limittion drk drk reduction t t low low temperture is is not not cler cler t t moment, but but possible reson is is lekge p-mos trnsistor used used resetting sensing node. node. This This is is becuse trp-ssisted b-to-b tunneling, which is is ten ten mjor mjor mechnism lekge MOS MOS trnsistor, hs hs smll smll temperture dependence. Sensors 2018, 18, Temperture dependence drk drk. 16 mp drk t 25 C 35 C shows shows mp mp distribution distribution drk drk mesured mesured t 25 t C 25 C 35 C. 35 C. men men re ] ] (= 4.3% men t 25 C men strd strd devition devition re 1200 re [pa/cm 1200 [pa/cm 2 ] 2 ] 51.6 [pa/cm 51.6 [pa/cm 2 ] (= 2 4.3% ] (= 4.3% men men vlue) vlue) t 25 t C 25 C 56 2 ] ] (= 12.6% men t 35 C. 56 [pa/cm 56 [pa/cm 2 ] 2 ] 6.3 [pa/cm 6.3 [pa/cm 2 ] (= 2 ] 12.6% (= 12.6% men men vlue) vlue) t 35 t 35 C. C. () () t t C C (b) (b) t t C C Pixel-to-pixel Pixel-to-pixel devition devition drk drk Redout Noise Noise Redout Noise shows mesured input-referred redout noise noise ll ll pixels. verge 17 shows mesured input-referred redout noise ll 8 7 pixels. verge vlue vlue vlue noise noise is e rms e rms minimum mximum noises re re rms e rms e rms, e rms, noise is 11.0 e rms minimum mximum noises re 8.6 e rms 14.3 e rms, respectively. respectively. Compred with with conventionl SOI SOI pixel pixel whose redout noise noise is is e rms e rms [9], [9], Compred with conventionl SOI pixel whose redout noise is 35 e rms [9], redout noise SOIPIX-PDD is reduced to one-third tht. redout noise clculted by Eqution (4) designed prmeters (C FB = 1.5 [ff], T CDS = 1 [ms], τ CSA = 0.2 µs, CS = 240 [ff])) is 4.5 e rms t 107 µv/e. With mesured conversion gin in 14, i.e., 70 µv/e, redout noise using Eqution (4) is clculted to be 5.8 e rms if CFB = 2.3 [ff]. In ny wy, mesured redout noise is bigger thn clculted noise. reson incresed redout noise is considered to be n increse in C D,

13 Sensors 2017, 17, redout noise SOIPIX-PDD is reduced to one-third tht. redout noise clculted by Eqution (4) designed prmeters (CFB = 1.5 [ff], TCDS = 1 [ms], τcsa=0.2 s, CS = 240 [ff])) is 4.5 Sensors e rms t 2018, 10718, μv/e 27. With mesured conversion gin in 14, i.e., 70 μv/e, redout 13noise 17 using Eqution (4) is clculted to be 5.8 e rms if CFB = 2.3 [ff]. In ny wy, mesured redout noise is bigger thn clculted noise. reson incresed redout noise is considered to be n increse n increse in C FB due to prsitic cpcitnce, coupling power supply noise through power in CD, n increse in CFB due to prsitic cpcitnce, coupling power supply noise through ground lines substrtes. power ground lines substrtes. 17. Mp input referred noise [e rms] n 8 7 pixel rry with cooling t 35 C. Highlighted 3 3 pixel rryis is used X-ry energy spectrum mesurement. A A pixel (x (x = = 2, 2, y = 5) shown by by red-colored box box is used is used mesurement mesurement single pixel single events. pixel Adjcent events. 8 pixels Adjcent shown8 by pixels yellow-colored shown by boxes yellow-colored re used boxes eliminting re used events eliminting chrge splitting events to plurl chrge pixels. splitting to plurl pixels X-ry Eergy Sectrum 4.2. X-ry Eergy Sectrum To evlute pixel permnce X-ry energy spectrum mesurement, prticulr pixel (x = 2, To y evlute = 5) 8 pixel 7 pixel permnce rry is used X-ry energy mesurement spectrum single mesurement, pixel events. prticulr djcent pixel eight (x = 2, pixels y = 5) re used 8 7 pixel eliminting rry is events used chrge mesurement splitting to plurl single pixels. events. To do this, djcent if pixel eight pixels spectrum re used mesurement eliminting hsevents n event chrge by checking splitting wher to plurl if signl pixels. isto lrger do this, thnif event pixel threshold, spectrum mesurement only if signls hs n event ll djcent by checking eight pixels wher re smller if signl thn is given lrger threshold, thn i.e., event threshold, split threshold, only event if is counted signls s ll mesured djcent eight energy pixels level re in smller spectrum. thn given 18 shows threshold, i.e., 241 Am X-ry split threshold, spectr single event pixel is counted events obtined s mesured with energy SOIPIX-PDD level in chip spectrum. fter dt reduction 18 shows nlyses 241 Am X-ry givenspectr in [20]. Since single pixel mesurement events obtined system uses with 14-bit SOIPIX-PDD A/D converter chip with fter dt nlog reduction rnge 2 V, nlyses 1 ADU given corresponds in [20]. to Since bin mesurement 122 µv n system energy uses bin 14-bit 6.54A/D ev with converter conversion with nlog gin rnge 70 µv/e 2 V, 1 ADU ω (= corresponds energy required to bin to liberte 122 μv one electron-hole n energy bin pir) ev ev/e with. conversion 18. Ingin this mesurement, 70 μv/e ω (= X-ry energy event required only tto liberte pixel (x one = electron-hole 2, y = 5) djcent pir) pixels ev/eshown. by18. yellow-colored In this mesurement, zone in X-ry 17 isevent considered only t pixel evlution (x = 2, y = 5) single pixel djcent events. 8 pixels shown energyby resolution yellow-colored SOIPIX-PDD zone in is is ev considered (2.01%) in FWHM evlution t kev. In single this pixel mesurement, events. energy event threshold, resolution split threshold SOIPIX-PDD energy is 280 ev bin(2.01%) spectrum in FWHM re t set to 10 kev. ADU In this (= 65mesurement, ev), 10 ADU (= 65event ev) threshold, 1.3 ADU split (= 8.5 threshold ev), respectively. energy In bin conventionl spectrum SOIPIX, re s set given to 10 ADU in [20], (= 65 ev), FWHM 10 ADU 1500 (= 65 ev ev) (10.8%) 1.3 t ADU kev (= 8.5 ev), respectively. 241 Am ws obtined, In conventionl indicting SOIPIX, effectiveness s given in [20], SOIPIX-PDD FWHM improving 1500 ev (10.8%) energy t resolution kev by fctor 241 Am ws more obtined, thn 5. Anor indicting good effectiveness in SOIPIX-PDD SOIPIX-PDD when compred improving with energy conventionl resolution SOIby pixels fctor is very-smll more thn tiling 5. Anor structures good effect energy in spectrum SOIPIX-PDD to lower-energy when compred side which with is possibly conventionl cusedsoi by pixels signl is chrge very-smll loss in tiling sensor structures lyers [9]. result energy spectrum 18 shows to lower-energy proposedside detector which hs is high possibly chrge cused collection by efficiency signl chrge or smll loss signl in chrge sensor loss lyers thnks [9]. to result employment 18 shows pinned depleted proposed diode detector structure. hs high chrge oreticl collection limitefficiency energyor resolution smll signl (FWHM) chrge loss detector thnks cn to be found using: FE E(eV) = 2.354ω ω + σ2 (7)

14 Sensors 2017, 17, Sensors 2017, 17, employment pinned depleted diode structure. oreticl limit energy resolution employment pinned depleted diode structure. oreticl limit energy resolution (FWHM) detector cn be found using: (FWHM) detector cn be found using: Sensors 2018, 18, 27 FE Δ EeV FE 2 EeV (( )) = 2.354ω + σ (7) ω (7) where where FF is is Fno Fno fctor fctor (0.11 (0.11 silicon), silicon), EE is is energy energy incident incident X-ry x-ry photon, photon, σσ is is mesured where is redout Fno noise. fctor With (0.11 mesured silicon), noise is energy pixel (x = 2, incident y = 5), i.e., x-ry 11.0 photon, e, energy is mesured redout noise. With mesured noise pixel (x = 2, y = 5), i.e., 11.0 e resolution mesured using redout noise. With (7) is mesured to be noise 200 ev pixel t (x 2, 5), i.e., 11.0, energy, energy resolution using Eqution (7) is clculted to be 200 ev (1.43%) t E = kev. ree, re is resolution using Eqution (7) is clculted to be 200 ev (1.43%) or t thn kev. redout ree, noise. re In is fctor furr improvement energy resolution or thn redout noise. In fctor furr improvement 18, becuse rdition energy source resolution irrdites or from thn surfce redout side noise. In SOI mesurement 18, becuse rdition source irrdites from surfce side SOI pixel, mesurement re still exists possibility 18, becuse signl rdition chrge source loss due irrdites to recombintion from surfce side neutrl BPW SOI pixel, re still exists possibility signl chrge loss due to recombintion in neutrl lyer pixel, re SOIPIX-PDD still exists detector. possibility signl chrge loss due to recombintion in neutrl BPW lyer SOIPIX-PDD detector. BPW lyer SOIPIX-PDD detector demonstrtes conversion gin gin µv/e μv/e by shot noise 19 demonstrtes conversion gin to gree with mesured signl voltges to μv/e Am s chrcteristic obtined by shot noise mesurement to obtined by shot noise mesurement to gree with mesured signl voltges to X-ry lines 13.95, 17.74, gree with mesured signl voltges to kev. In 18, spectrl pek Am s chrcteristic X-ry lines 13.95, 17.74, 20.8 Am s chrcteristic X-ry lines 13.95, 17.74, kev. In 18, spectrl pek probbly due to chrcteristic X-ry line line kev kev 26.3 kev. In 18, spectrl pek probbly due to chrcteristic X-ry line 59.5 kev is is observed observed t t pulse pulse height height ADU. ADU. This This pulse pulse height height corresponds to to VV s s output output is observed t pulse height 7700 ADU. This pulse height corresponds to 0.94 s output signl signl voltge, voltge, while while implemented pixel hs output voltge linerity up upto to V s sshown shownin signl voltge, while implemented pixel hs output voltge linerity up to 0.6 s shown in in chrcteristic X-ry line 59.5 kev cnnot be be exctly mesured becuse pulse pulse 13. chrcteristic X-ry line 59.5 kev cnnot be exctly mesured becuse pulse height height is is outside outside liner liner rnge rnge designed designed detector. detector. ree ree dt dt point point kev kev is height is outside liner rnge designed detector. ree dt point 59.5 kev not is not included included in is not included in Mesured Mesured X-ry X-ry spectr spectr Am Am s s s single-pixel single-pixel events events using using SOIPIX-PDD. SOIPIX-PDD. 1 1 ADU ADU is is is µv/e μv/e μv/e (2 (2 (2 V/14 bit). bit). bit) Confirmtion conversion gin gin with with mesured X-ry X-ry spectr spectr Confirmtion conversion gin with mesured X-ry spectr Am. Am. Am. 20 shows 55 Fe X-ry spectr single pixel events using pixel(x = 2, y = 2) SOIPIX-PDD detector different chip from tht used mesurement s bis voltge V BB V BB2 re set t 60 V, 2.7 V, respectively. A very good energy resolution

15 Sensors 2017, 17, Sensors 2018, 18, shows 55 Fe X-ry spectr single pixel events using pixel(x = 2, y = 2) SOIPIX-PDD detector different chip from tht used mesurement s 13 to 19. bis voltge VBB VBB2 re set t 60 V, 2.7 V, respectively. A very good energy resolution (FWHM) (FWHM) ev ev (3.6%) (3.6%) t 5.9 t kev 5.9 kev very very smll smll tiling tiling re obtined. re obtined. Mn-K (5.9 Mn-K kev) (5.9 kev) Mn-K (6.4 Mn-K kev) (6.4 lines kev) re lines definitely re definitely discriminted. discriminted Mesured X-ry X-ry spectr 55 Fe Fe s s single-pixel events using SOIPIX-PDD Permnce Comprison Tble 2 shows 2 shows comprison conventionl conventionl SOIPIX SOIPIX (XRPIX (XRPIX series) series) SOIPIX-PDD. SOIPIX-PDD. Using SOIPIX-PDD, Using SOIPIX-PDD, redout redout noise noise drk drk re significntly re significntly reduced reduced resulting resulting X-ry spectroscopic X-ry spectroscopic permnce permnce gretly improved gretly improved when compred when compred with conventionl with conventionl SOIPIX detectors. SOIPIX Though detectors. it isthough not shown it is innot shown Tble 2, in chrcteristic Tble 2, X-ry chrcteristic spectrl line X-ry with spectrl very smll line tiling with very becuse smll tiling high chrge becuse collection high chrge efficiency collection is nor efficiency dvntge is nor dvntge SOIPIX-PDD. SOIPIX-PDD. Tble Comprison with conventionl SOIPIX (XRPIX series) SOIPIX-PDD. SOIPIX SOIPIX Type Type XRPIX1 XRPIX1[20] XRPIX2b-A [9] [9] XRPIX3b-CSA [9] SOIPIX-PDD Conversion Conversion gin gin Redout Redout noise noise 129 e rms 129 e rms 68 e rms 68 e rms 35 e rms 35 e rms rms 11.0 e rms Drk Drk N. N. A. A. N. N. A. A C C na/cm C C Energy Energy resolution resolution (FWHM@5.9 kev) kev) N. N. A. A. N. A. 320 ev (5.4%) eV (3.6%) Energy Energy resolution resolution 1500 ev 1500 ev (10.8%) (FWHM@13.95 (FWHM@13.95 kev) kev) (10.8%) (~1500 ev)* N. A. 280 ev (2.0%) * *Numericl vlue vlue energy energy resolution resolution is not reported, is not but reported, it is estimted but it from is estimted grph from X-ry energy grph spectr X-ry Am given in [9]. energy spectr 241 Am given in [9]. 5. Conclusions 5. Conclusions A novel SOI pixel detector using pinned depleted diode structure (SOIPIX-PDD) hs been A novel SOI pixel detector using pinned depleted diode structure (SOIPIX-PDD) hs been presented in this pper. SOIPIX-PDD relizes low redout noise due to smll chrge sensing presented in this pper. SOIPIX-PDD relizes low redout noise due to smll chrge sensing node cpcitnce, low drk due to pinned Si surfce t Si-SiO node cpcitnce, low drk due to pinned Si surfce t 2 interfce detector under Si-SiO2 interfce detector BOX lyer high chrge collection efficiency with buried chnnel crrier collection. under BOX lyer high chrge collection efficiency with buried chnnel crrier implemented chip demonstrtes tht SOIPIX-PDD pixels hs high-conversion gin collection. implemented chip demonstrtes tht SOIPIX-PDD pixels hs high-conversion 70 µv/e, low noise 11.0 e rms, low drk 56 pa/cm 2 t 35 C, good energy gin 70 μv/e, low noise 11.0 e rms, low drk 56 pa/cm 2 t 35 C, good energy resolution in mesured chrcteristic X-ry lines, e.g., 200eV(FWHM) t 5.9 kev 280 ev resolution in mesured chrcteristic X-ry lines, e.g., 200eV(FWHM) t 5.9 kev 280 ev (FWHM) t kev. (FWHM) t kev.

16 Sensors 2018, 18, Acknowledgments: We cknowledge vluble dvice gret work by personnel LAPIS Semiconductor Co., Ltd. This study ws supported by Jpn Society Promotion Science (JSPS) KAKENHI Grnt-in-Aid Scientific Reserch on Innovtive Ares (Y.A.), (S.K.), (T.G.T.) Gr-in-Aid Young Scientists (B) 15K17648 (A.T.). This study ws lso supported by VLSI Design Eduction Center (VDEC), University Tokyo in collbortion with Cdence Design Systems, Inc., Mentor Grphics, Inc. uthors would like to thnk Nobukzu Ternishi Keiichiro Kgw Shizuok University Ikuo Kurchi High Energy Accelertor Reserch Orgniztion (KEK) helpful discussion. Author Contributions: Shoji Kwhito, Tkeshi Go Tsuru Ysuo Ari proposed device concept provided overll guidnce project. Hiroki Kmehm, Shoji Kwhito, Sumeet Shresth, Keit Ysutomi, Ayki Tked Tkeshi Go Tsuru designed detector. Hiroki Kmehm Syunt Nknishi Tkeshi Go Tsuru mesured chip. Hiroki Kmehm Shoji Kwhito drfted mnuscript. Conflicts Interest: uthors declre no conflict interest. References 1. Koym, K.; Tsunemi, H.; Dotni, T.; Butz, M.W.; Hyshid, K.; Tsuru, T.G.; Mtsumoto, H.; Ogwr, Y.; Ricker, G.R.; Doty, J.; et l. X-ry imging spectrometer (XIS) on bord Suzku. Publ. Astron. Soc. Jpn. 2015, 59, [CrossRef] 2. Grmire, G.P.; Butz, M.W.; Ford, P.G.; Nousek, J.A.; Ricker, G.R., Jr. Advnced CCD Imging Spectrometer (ASICS) instrument on Chr X-ry Observtory. In X-ry Gmm-ry Telescopes Instruments Astronomy; Trumper, J.E., Tnnbum, H.D., Eds.; SPIE: Bellinghm, WA, USA, 2003; pp Ari, Y.; Miyoshi, T.; Unno, Y.; Tsuboym, T.; Terd, S.; Ikegmi, Y.; Ichimiy, R.; Kohriki, T.; Tuchi, K.; Ikemoto, Y.; et l. Development SOI pixel process technology. In Nucler Instruments Methods in Physics Reserch Section A: Accelertors, Spectrometers, Detectors Associted Equipment; Elsevier: Amsterdm, Nerls, 2011; Volume 636, pp. S31 S Griffith, C.V.; Flcon, A.D.; Prieskorn, Z.R.; Burrows, D.N. Speedster-EXD: A new event-driven hybrid CMOS X-ry detector. J. Astron. Telesc. Inst. 2016, 2, [CrossRef] 5. Ari, Y.; Miyoshi, T.; Unno, Y.; Tsuboym, T.; Terd, S.; Ikegmi, Y.; Kohriki, T.; Tuchi, K.; Ilemoto, Y.; Ichimiy, R.; Iked, H.; et l. Development SOI monolithic pixel detectors. In Nucler Instruments Methods in Physics Reserch Section A: Accelertors, Spectrometers, Detectors Associted Equipment; Elsevier: Amsterdm, Nerls, 2010; Volume 623, pp Nkshim, S.; Ryu, S.G.; Tsuru, T.G.; Tked, A.; Ari, Y.; Miyoshi, T.; Ichimiy, R.; Ikemoto, Y.; Immur, T.; Ohmoto, T.; et l. Progress in development monolithic ctive pixel detector X-ry stronomy with SOI CMOS technology. Phys. Procedi 2012, 37, [CrossRef] 7. Tsuru, T.G.; Mtsumur, H.; Tked, A.; Tnk, T.; Nkshim, S.; Ari, Y.; Mori, K.; Tkenk, R.; Nishiok, Y.; Tkyoshi, K.; et l. Development permnce Kyoto s X-ry stronomicl SOI pixel (SOIPIX) sensor. In Spce Telescopes Instrumenttion 2014: Ultrviolet to Gmm Ry; Interntionl Society Optics Photonics: Montrel, QC, Cnd, Tked, A.; Ari, Y.; Ryu, S.G.; Nkshim, S.; Tsuru, T.G.; Immur, T.; Ohmoto, T.; Iwt, A. Design evlution n SOI pixel sensor trigger-driven X-ry redout. IEEE Trns. Nucl. Sci. 2013, 60, [CrossRef] 9. Tked, A.; Tsuru, T.G.; Tnk, T.; Uchid, H.; Mtsumur, H.; Ari, Y.; Mori, K.; Nishiok, Y.; Tkenk, R.; Kohmur, T. Improvement spectroscopic permnce using chrge-sensitive mplifier circuit n X-ry stronomicl SOI pixel detector. J. Instrum. 2015, 10, C [CrossRef] 10. Okihr, M.; Ksi, H.; Miur, N.; Kuriym, N.; Ngtomo, Y.; Htsui, T.; Omodni, M.; Miyoshi, T.; Ari, Y. Progress FD-SOI technology monolithic pixel detectors. In Proceedings 2012 IEEE Nucler Science Symposium Medicl Imging Conference (NSS/MIC), Anheim, CA, USA, 27 October 3 November 2012; pp Hshimoto, R.; Ari, Y.; Igrshi, N.; Kumi, R.; Miyoshi, T.; Kishimoto, S. Test results counting type SOI device new X-ry re detector. In Proceedings AIP Conference; Americn Institute Physics: Melville, NY, USA, 2016; p Luxtermnn, S.; Vngplly, V. A Fully Depleted Bckside Illuminted CMOS Imger with VGA Resolution 15-micron Pixel Pitch. In Proceedings IEEE Interntionl Imge Sensor Workshop, Snowbird, UT, USA, June 2013.

17 Sensors 2018, 18, Htsui, H.; Omodni, M.; Kudo, T.; Kobyshi, K.; Immur, T.; Ohmoto, T.; Iwt, A.; Ono, S.; Kirihr, Y.; Kmeshim, T.; et l. A direct detection X-ry CMOS imge sensor with 500 µm thick high resistivity silicon. In Proceedings IEEE Interntionl Imge Sensor Workshop, Snowbird, UT, USA, June Sekiguchi, Y.; Ari, Y.; Hmgki, H.; Gunji, T. Development SOI pixel sensor environmentl rdition monitor. RIKEN Accel. Prog. Rep. 2014, 47, Fhim, F.; Deptuch, G.; Holm, S.; Sheni, A.; Lipton, R. Monolithic ctive pixel mtrix with binry counters ASIC with nested wells. J. Instrum. 2013, 8, C [CrossRef] 16. Kmehm, H.; Shresth, S.; Ysutomi, K.; Kgw, K.; Tked, A.; Tsuru, T.G.; Ari, Y.; Kwhito, S. Fully depleted SOI pixel photo detectors with bckgte surfce potentil pinning. In Proceedings IEEE Interntionl Imge Sensor Workshop, Vls, Nerls, 8 11 June Ternishi, N.; Kohno, A.; Ishihr, Y.; Ari, K. No imge lg photodiode structure in interline CCD imge sensor. In Proceedings Interntionl Electron Devices Meeting, Sn Frncisco, CA, USA, December 1982; pp Kwhito, S.; Seo, M.W. Noise reduction effect multiple-smpling-bsed signl-reduction circuits ultr-low Noise CMOS imge sensors. Sensors 2016, 16, [CrossRef] [PubMed] 19. Kwhito, S.; Itoh, S. Noise clcultion model nlysis high-gin redout circuits CMOS imge sensors. In Proceedings Electronic Imging, Sn Jose, CA, USA, Jnury Ryu, S.G.; Tsuru, T.G.; Nkshim, S.; Tked, A.; Ari, Y.; Miyoshi, T.; Ichimiy, R.; Ikemoto, Y.; Mtsumoto, H.; Immur, T.; et l. First permnce evlution n X-ry SOI pixel sensor imging spectroscopy intr-pixel trigger. IEEE Trns. Nucl. Sci. 2011, 58, [CrossRef] 21. Nkmur, J. (Ed.) Imge Sensors Signl Processing Digitl Still Cmer; CRC: Boc Rton, FL, USA, 2005; pp by uthors. Licensee MDPI, Bsel, Switzerl. This rticle is n open ccess rticle distributed under terms conditions Cretive Commons Attribution (CC BY) license (