The egan FET Journey Continues
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1 The egan FET Journey Continues Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium Nitride Based Point of Load Converter David Reusch and Johan Strydom Efficient Power Conversion Corporation EPC - The Leader in egan FETs 1
2 Agenda Overview of Current Technology Parasitic Impact on Performance Conventional Layout Comparison Optimal Layout for egan FETs Experimental Results Summary EPC - The Leader in egan FETs 2
3 Why Gallium Nitride? EPC - The Leader in egan FETs 3
4 Ideal Hard Switching T VR T CF V IN V DS I OFF I DS V GS V PL V TH t EPC - The Leader in egan FETs 4 4
5 40V Device Comparison FOM=(Q GD +Q GS2 )*R DSON (nc*ω) Q GS2 Q GS2 Q GS2 Q GS2 Q GS2 Q GD Q GD Q Q GD GD Q GD egan FET MOSFET 1 MOSFET 2 MOSFET 3 MOSFET 4 V DS =20 V, I DS = 20 A EPC - The Leader in egan FETs 5
6 Buck Converter Parasitics C in T SR L S : Common Source Inductance L : High Frequency Power Inductance Power Loss(W) Power Loss vs Parasitic Inductance Ls L Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, F S =1 MHz, I OUT = 20 A EPC - The Leader in egan FETs 6 6
7 Packaging Evolution Power Loss (W) SO-8 LFPAK DirectFET LGA egan Device Loss Breakdown 90 82% 18% Package Die 73% 27% 47% 53% V IN =12V V OUT =1.2V I OUT =20A F S =1MHz 18% 82% SO-8 LFPAK DirectFET LGA Efficiency (%) SO-8 LFPAK DirectFET LGA Switching Frequency (MHz) EPC - The Leader in egan FETs 7
8 Layout Impact on Efficiency Efficiency (%) Measured Efficiency 40V MOSFET 3x3mm LFPAK L 3nH L 0.4nH L 1.0nH L 1.6nH L 2.9nH Output Current (I OUT ) V IN =12 V, V OUT =1.2 V, F S =1 MHz, L=150 nh Experimental Prototype L LOOP 0.4 nh EPC - The Leader in egan FETs 8 8
9 Layout Impact on Peak Voltage L 1.0 nh L 0.4 nh 70% Overshoot 30% Overshoot Switching Node Voltage V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=150 nh EPC - The Leader in egan FETs 9 9
10 Conventional Lateral Layout Top View Side View EPC - The Leader in egan FETs 10
11 Conventional Vertical Layout Top View Side View Bottom View EPC - The Leader in egan FETs 11
12 Proposed Optimal Layout Top View Side View Top View Inner Layer 1 EPC - The Leader in egan FETs 12
13 Layout Comparisons Lateral Vertical Optimal Single Sided PCB Capability Yes No Yes Field Self Cancellation No Yes Yes Inductance Independent of Board Thickness Yes No Yes Shield Layer Required Yes No No EPC - The Leader in egan FETs 13
14 Layout Inductance Comparison Parasitic Inductance (nh) Inner Layer Distance 4 mils 12 mils 26 mils Board Thickness (mil) Top View Vertical Power Optimal Power Lateral Power Test Cases Board Thickness (mils) Inner Layer Distance (mils) Design Design Design Design EPC - The Leader in egan FETs 14
15 Power Loss Comparison Power Loss (W) Lateral Power Optimal Power Vertical Power High Frequency Inductance (L LOOP ) V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 EPC - The Leader in egan FETs 15
16 Voltage Overshoot Comparison Voltage Overshoot (%) Lateral Power Optimal Power Vertical Power High Frequency Inductance (L LOOP ) V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 EPC - The Leader in egan FETs 16
17 Switching Speed Comparison egan FET dv/dt (V/nS) Optimal Power Lateral Power Vertical Power High Frequency Inductance (L LOOP ) V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh T/SR: EPC2015 Driver LM5113 EPC - The Leader in egan FETs 17
18 Efficiency Comparison Efficiency (%) V MOSFET Vertical Design 1 Optimal Design 1 Vertical Design 1 Lateral Design Output Current (I OUT ) V IN =12 V V OUT =1.2 V F S =1 MHz L=300 nh GaN T/SR: EPC2015 Driver LM5113 EPC - The Leader in egan FETs 18
19 egan FET vs. MOSFET Si MOSFET egan FET 3 V/ div V IN =12 V V OUT =1.2 V I OUT =20 A F S =1 MHz L=300 nh egan FET T/SR: EPC2015 MOSFET T:BSZ097N04 SR:BSZ040N04 EPC - The Leader in egan FETs 19
20 EPC9107 Demonstration Board V IN =12-28 V V OUT =3.3 V I OUT =15 A F S =1 MHz 2 x EPC2015 V IN =28 V Switching Node Voltage V IN =28 V I OUT =15 A 5 V/ div EPC - The Leader in egan FETs 20
21 Summary egan FETs improve performance in high switching frequency converters: Lower FOM (Q GD +Q GS2 )*R DSON Lower Package Parasitics PCB Layout Limits Performance Optimizing Layout Enhances Performance EPC - The Leader in egan FETs 21
22 The end of the road for silicon.. is the beginning of the egan FET journey! EPC - The Leader in egan FETs 22
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T C =25 unless otherwise specified
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This paper was originally presented at the Power Electronics Technology Exhibition & Conference, part of PowerSystems World 2005, held October 25-27, 2005, in Baltimore, MD. To inquire about PowerSystems
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