Hybrid Synchronous DC-DC Buck Power Converter using Si and GaN Transistors

Transcription

1 1 Hybrid Synchronous DC-DC Buck Power Converter using Si and GaN Transistors Mohammad H. Hedayati 1, Pallavi Bharadwaj 2, Vinod John 2 1 School of Engineering, University of Aberdeen 2 Department of Electrical Engineering, Indian Institute of Science mh49929@gmail.com, pallavi.9b@gmail.com, vjohn@ee.iisc.ernet.in Abstract Usage of power converters in a vast variety of equipments from cellphones, laptops to automobiles, aeroplanes and satellites is increasing. Different synchronous buck converter configurations are considered in this work using Silicon (Si) devices and Gallium Nitride (GaN) devices of equal current ratings. The performance of these converters in terms of power losses and overall efficiency are compared. It is shown that the usage of GaN devices instead of Si devices reduces the power losses and improves the overall efficiency of the power converter. A hybrid synchronous buck converter topology consisting of one Si device and one GaN device is shown to have the lowest rated power loss for switches with similar ratings. The usage of GaN device as active switch and the Si device as synchronous diode is beneficial and has the highest efficiency among the possible converter configurations with an improvement in efficiency by 3-5% for rated conditions. Index Terms DC-DC power converters, synchronous operation, Si and GaN power FETs. I. INTRODUCTION Due to the significant merits offered by wide band gap devices, GaN based power devices are expected to offer high power density, highly efficient, and cost effective power conversion technology [1]. Various research efforts have been in the direction of their optimal utilisation by, for example, miniaturization of point-of-load dc-dc converters by the use of high switching frequency [2], [3]. The use of GaN power FETs in synchronous buck converter has resulted in improved converter efficiencies [4] [6], even at very high switching frequencies, ranging upto hundreds of MHz [7], [8]. To further enhance power density at high switching frequencies, ZVS operation of GaN devices has also been considered [9]. However, high switching frequencies have additional challenges in terms of increased effect of circuit parasitics on device voltage stress and power loss [3], [1]. To reduce circuit parasitics and improved thermal performance, a 3-D direct-bonded-copper PCB design is presented in [11]. Apart from PCB design, usage of devices with low switching losses at high frequency can reduce power loss and smaller sizes can be achieved. Superiority of GaN power FETs over Si devices has been shown by increased efficiency of GaN based power converters [2]. However GaN power FETs suffer from high reverse This work is supported by the Department of Electronics and Information Technology, Government of India, under a project titled Investigation on gallium nitride (GaN) devices for power electronics switching applications and design and development of high frequency GaN converter topology as part of National Mission on Power Electronics Technology phase-ii. conduction drop, to overcome which, a three level driving point method is proposed in [12]. Another approach is to use fast switching GaN and low R DS,on Si MOSFET, combined in a synchronous buck converter [13]. This approach is also explored in the present work, however the basis of GaN and Si device selection is equivalent current ratings as compared to lowest available R DS,on in [13]. Use of equal current rating switches is important for the design of the point of load converter s, where the range of input voltage can vary from close to the output voltage to much higher values, based on the application in which the converter is used. Various converter topologies with all possible combinations of Si MOSFET and enhancement mode GaN power FET, selected on the basis of consistent ratings, are compared for maximising efficiency. Power loss modelling has been achieved using least square fit of the measured data, the results of which show that out of the four possible topologies, the proposed hybrid converter provides good performance in terms of high efficiency. When the GaN transistor is used as an active switching device and a Si MOSFET is used as the synchronous rectifier device, an efficiency improvement of 3-5% is obtained. This is shown to be attributable to the combined low reverse conduction loss of the Si transistor and low switching loss of the GaN transistor in the hybrid converter approach. This is also verified by temperature measurement of the transistors. II. SYNCHRONOUS BUCK CONVERTER An efficient way of converting a dc voltage to a lower dc voltage level is to use dc-dc buck converter. In normal dc-dc buck converter an active switch and a diode along with the passive components, inductor L and capacitor C, are used to switch the current and reduce the voltage level to a desired voltage level. This is shown in Fig. 1. It is possible to enhance the efficiency of normal dc-dc buck converter by adopting an active switch MOSFET in place of the diode. This is due to the lower voltage drop across the MOSFET compared to the diode. This configuration is called synchronous dc-dc buck converter and is shown in Fig. 1. The switches in the buck converter can operate at high frequency in the range of hundreds of khz to MHz, which can help reduce the size and cost of the LC filter. Si technology is well advanced and converters with Si devices are mature. New technologies such as silicon carbide /16/$31. c 216 IEEE

2 PV PV Vs1 Vs2 Vs3 Is Lf Lf Lf s4 Vi1 s6 Vi2 s2 Vi3 c RL π ɸ β2 ω θ α converters are designed so as to convert an input voltage ranging from 6 V to 2 V and output voltage of 3.3 V. The power rating of this converter is 33 W. The switching frequency is chosen to be 1 MHz. An LTC3833 chip is used π as the controller. This controller can work up to 2 MHz. The Si MOSFET and egan FET were chosen according to the β required converter ratings of V and 33 A. Additionally, the switches are very fast and can be switched in the MHz range. Designing the PCB layout is challenging at higher switching θ frequency [3] and this is discussed in the subsection III-B. 1 L 2 C 3 TABLE II THE FOUR BUCK CONVERTER CONFIGURATIONS STUDIED. M rs L C M rs I s Fig. 1. Dc-dc buck converter showing normal buck converter and, synchronous buck converter. (SiC) and GaN open a window in the power electronic area. Adopting new technology can be beneficial however, many challenges I s are there for the new design that have to be taken care. In this work different dc-dc power converters with Si and GaN devices are designed and fabricated. The converters are tested at different operating conditions and the results are compared with each other, which shows that the proposed configuration is 3-5% more efficient at rated power, than other possible configurations. In the proposed hybrid synchronous buck converter the maximum case temperature is seen to be reduced by o C compared to a full Si transistor configuration. III. HARDWARE DESIGN AND IMPLEMENTATION TABLE I DETAILS OF THE FABRICATED SYNCHRONOUS BUCK CONVERTER Configuration Si T Si B GaN T GaN B Si T GaN B GaN T Si B A. GaN and Si MOSFET power loss Comment Si converter with both Si switches GaN converter with both GaN switches Hybrid converter with Si as active switch and GaN as synchronous rectifier switch Most efficient hybrid converter with GaN as active switch and Si as synchronous rectifier switch In synchronous buck converter, top device Q 1 operates in forward conduction mode and bottom device Q 2 operates in reverse conduction mode, as marked in Fig. 1. The structure of VDMOS is shown in Fig. 2, wherein the forward or reverse conduction is through the transistor channel when the device is gated high and reverse conduction is through the inherent body diode when the gate is low. The structure of a lateral transistor is shown in Fig 2. A simplified equivalent circuit of a MOSFET is shown in Fig. 2. During forward biased operation of the transistor, current flows from drain to source. Effective voltage across channel can be written as: V GS = V Gon I D R 1 (1) Vs1 Vs1 g Configuration Si switch GaN switch Inductor Filter Capacitor Controller V in V out I out F sw Comment Si4456dy, V, 33 A EPC-GaN-215, V, 33 A SRN26-1RY, 1 µh, 24 A Tantalum - 6TPC33MA, 2 33 µf, 6.3 V Ceramic - GRM31CRJ17ME39L, 2 µf, 6.3 V LTC V 3.3 V 1 A 1 MHz A synchronous buck power converter is designed which can operate with egan power FET as well as Si MOSFET. Details of the synchronous buck converter are provided in Table I. Based on possible device combinations, as to which device is placed in top device position of control switch, marked as Q 1 in Fig. 1, and which device is placed in the bottom device position of synchronous diode, marked as Q 2 in Fig. 1, four boards are populated. All other components and layout are kept identical except for the four cases corresponding to the transistor combinations, and are listed in Table II. The However, when reverse bias is applied and the direction of drain current reverses, then the effective voltage across the channel is written as: V GS = V Gon + I D (R 1 + R g ) (2) Therefore even during reverse conduction when the gate is given a positive voltage with respect to source, conduction takes place through the channel and the conduction sees a higher effective gate voltage, which results in lower on state drop. However for GaN the forward and reverse conduction is boosted by the 2D electron gas property. Hence the effect of higher effective gate voltage is not seen to provide benefits in the reverse conduction characteristics of egan FET [14]. To prevent voltage source from shorting during switching transition, a blanking or dead time is provided in all voltage source synchronous converter legs. During this duration, body diode of the MOSFET conducts, but for GaN HEMT, the channel again conducts, but for conduction, I D R 1 drop has to be greater than V T H V Goff for the transistor to reverse conduct. Therefore in GaN device operation V Goff is typically recommended to be zero volts. A negative V Goff can further g

3 3 S S G Gate N + N + P P N- Drift N + D S G D Gate N + N + V Gon P substrate G N-drift S ' S '' R 1 R g R 2 I D Fig. 2. Cross-section of VDMOS structure, lateral MOSFET structure. V Simplified equivalent resistive circuit of MOSFET during forward A bias operation. V A Vdd D PV R 1 L 2 C 3 M rs Vdd I s R 1 loop between the switches, must be minimized as shown in Fig. 3. This parasitic inductance can result in over voltage PV Fig. 3. PCB parasitic inductance of high di/dt loop, layout of the PCB used for the laboratory converters. across the devices and damage them. This is taken care by placing the devices and the high frequency capacitor, C HF L 2 C close to 3 each other as shown in Fig. 3. Additionally, the second layer of the PCB is chosen to be ground plane, this helps to reduce the parasitic inductance further more. The fabricated PCBI M s with Si devices Si T Si B and GaN devices GaN rs T GaN B are shown in Fig. 4 and, respectively, and are based on the guidelines from [15] and [16]. increase the reverse conduction drop that occurs during the dead time. Therefore typical Si power MOSFETs have better reverse conduction properties as compared to GaN HEMTs. This is also observed in experimental results presented in Section IV, based on which a hybrid converter topology is proposed wherein GaN device acts as top active switch and Si MOSFET is used for reverse synchronous operation in buck converter. As far as gate drive losses are concerned, gate charge of HEMT structure is typically lower than Si MOSFET [14]. Therefore the switching losses are lower in GaN devices compared to Si MOSFETs. Also the fixed gate driving loss is lesser in a GaN converter. Reverse recovery of Si MOSFET occurs due to the conduction of body diode during blanking time. GaN devices do not have body diode, therefore reverse recovery losses are absent in GaN converters. Overall, the forward conduction, gate drive and switching losses are better in GaN HEMTs and reverse conduction characteristics of Si MOSFETs are comparatively better. Hence, the GaN T Si B hybrid converter configuration from Table II should have better performance in terms of power loss. This is confirmed by the experimental results in Section IV and power loss modelling in Section V. B. PCB Design At high switching frequency, the parasitics of the PCB play a significant role. This should be kept in mind and the PCB is designed such that these parasitics are minimized. For instance, the parasitic inductance of the PCB in the high di/dt IV. EXPERIMENTAL RESULTS All the four boards with different device combinations, as mentioned in Table II, are tested with three different input voltages of 6 V, 1 V and 2 V from no load to full load conditions and the results are discussed below. A. Power Loss Measurement The power losses are measured by subtracting the output power from input power. The power loss is then normalized using the rated output power of 33 W. The results are shown in Fig. 5. As the input voltage V in is increased, the losses in the GaN T GaN B converter is seen to be lower than that of a Si T Si B converter. It can be seen that the least power loss at loaded condition in all the tests corresponds to the converter with top GaN device and bottom Si device. By comparing the Si converter and Si T GaN B converter, it can be observed that the GaN devices do not perform well when they are used as synchronous diodes at loaded conditions. A loss reduction of 5% is observed under worst case condition of rated power and high input voltage. B. Efficiency Test The efficiency of the power converters are calculated at different loading condition. The results are shown in Fig. 6. It can be seen that the GaN T Si B converter has the highest efficiency at loaded condition in all the cases. This confirms that the usage of GaN devices for the active switch enhances the overall efficiency of the power converters. An efficiency improvement of 5% is observed at rated power and high input voltage.

4 P Loss /P Omax (%) P Loss /P Omax (%) P Loss /P Omax (%) Fig. 5. Normalized power loss of the four converter configurations at different loading condition. V in = 6V, V in = 1V, V in = 2V. Efficiency (%) 2 Efficiency (%) 2 Efficiency (%) 2 Fig. 6. Efficiency of the four converter configurations at different loading condition. V in = 6V, V in = 1V, V in = 2V. C. Temperature Measurements The surface temperature of the switching devices was measured at different loading conditions. The results are shown in Fig. 7 and Fig. 8, for top and bottom switches respectively. It can be seen that for the proposed hybrid GaN T Si B converter top and bottom device temperatures are minimum, for a major range power operation, except for Fig. 8, where bottom Si MOSFET is seen to have lower temperature in Si T Si B, as compared to bottom Si MOSFET temperature in GaN T Si B converter. A temperature reduction of o C is observed for the top device under worst case temperature conditions of rated power and high input voltage. D. Effect of Input voltage It has been observed that as the input voltage increases, efficiency falls, power losses increase and device temperatures rise. A worst-case temperature of 18 o C is observed for top device of Si T Si B converter operating at rated power and 2 V input voltage compared to 56 o C under same conditions but 6 V input. V. POWER LOSS MODELLING The relative switching and conduction loss comparisons can be evaluated by fitting the loss curves for the four synchronous buck converter configurations indicated in Table II. The power loss is expressed as a function of input dc bus voltage V dc and output load current I o as shown in (3). Conduction loss, switching loss and other parasitic loss comparisons can be made from such a model, indicating the merits of the different configurations. Here the power loss is broadly subdivided into constant loss component represented by K. K 1 I o represents the fixed drop component often encountered in semiconductors such as diodes. K 2 V dc represents the power lost in fixed bias control ICs. Further, K 3 Io 2 represents the conduction loss in series resistive components. The contribution of power lost in parallel shunt resistances is represented by K 4 Vdc 2. The switching losses are represented by the last term given by K 5 V dc I o. P Loss = K +K 1 I o +K 2 V dc +K 3 I 2 o +K 4 V 2 dc+k 5 V dc I o (3) The coefficients K i, where iɛ[, 5], can be evaluated by the application of least square minimisation of the error function [17], which in turn is formulated from the measured power loss corresponding to different voltage and current conditions. In present case, the above mentioned parameters are extracted with the use of lsqlin function of the optimisation toolbox of MATLAB [18], which is based on a reflective Newton optimisation method. The results are normalized to obtain a loss budget breakup for different power converters, and are presented in Table III and Table IV. The results are presented in percentage of the rated power P r. The quality of curve-fit is clearly indicated by the low value of curve-fit error, which is defined as (4). Σ N j=1 Error = (P m P cf ) 2 Pr 2 % (4) N

5 Temp-Top ( o C) 9 7 Temp-Top ( o C) 9 7 Temp-Top ( o C) Output Power(W) 3 3 Fig. 7. Temperature of the top device (Q 1 in fig. 1) of the converters at different loading condition. V in = 6V, V in = 1V, V in = 2V. Temp-Bottom ( o C) Temp-Bottom ( o C) Temp-Bottom ( o C) Fig. 8. Temperature of the bottom device (Q 2 in fig. 1) of the converters at different loading condition. V in = 6V, V in = 1V, V in = 2V. where, N is the number of measurements, P m is the measured power and P cf is the power estimated by curve-fit. Power loss for minimum and maximum voltage (6 V - 2 V) are given by the range of power loss represented as P LV min V max. It can be observed that switching losses in the GaN converter is lower than that of the Si converter. However, in this voltage and current rating, the Si device has lower conduction drop as can be observed from k 1 and k 3 factors. The proposed hybrid GaN T Si B converter has low conduction and switching loss. Out of the four converter configurations, maximum efficiency at rated power is seen to be higher for GaN T Si B hybrid converter case in both low voltage and high voltage range. TABLE III POWER LOSS MODELLING PARAMETERS OBTAINED WITH LEAST SQUARE OPTIMISATION ON NORMALIZED DATA FOR GaN T GaN B AND Si T Si B CONVERTERS GaN T GaN B Si T Si B K =.15.15%-.15% K =.29.29%-.29% K 1 = %-1.57% K 1 =..%-.% K 2 =. 1.9%-3.64% K 2 = %-3.76% K 3 = %-5.87% K 3 = %-4.56% K 4 =..%-.% K 4 =.5.17%-1.84% K 5 = %-6.48% K 5 = %-7.27% Resnorm Resnorm Error.18% Error.2% Power loss 1.63%-17.71% Power loss 8.33%-17.72% Efficiency 9.39%-84.95% Efficiency 92.31%-84.75% TABLE IV POWER LOSS MODELLING PARAMETERS OBTAINED WITH LEAST SQUARE OPTIMISATION ON NORMALIZED DATA FOR HYBRID GaN T Si B AND Si T GaN B CONVERTERS GaN T Si B Si T GaN B K =.81.81%-.81% K =.53.53%-.53% K 1 =..%-.% K 1 = %-2.26% K 2 =.5.9%-.3% K 2 =.11.2%-.67% K 3 =.8 5.8%-5.8% K 3 =.3 3.%-3.% K 4 =.18.%-6.61% K 4 =.7.23%-2.57% K 5 =..%-.% K 5 = %-9.63% Resnorm Resnorm Error.22% Error.19% Power loss 6.58%-12.% Power loss 9.91%-19.46% Efficiency 93.83%-88.65% Efficiency 9.98%-83.71% VI. CONCLUSION Replacing the switches of a dc-dc buck converter with GaN devices can help increase the efficiency of the converter when the switching frequency is high. However, this is not the best efficiency that one can get from the converter with high switching frequency. It is observed that the GaN devices do not perform better than Si devices when they are used as a synchronous diode. Hence, the best solution is to use GaN device for active switch and Si device as synchronous diodes. This is confirmed by experimental power loss and temperature measurements. This argument is also supported by the power loss modelling, achieved using the least square fit of the measured data. This modelling highlights the factor

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