A Novel Concept in Integrating PFC and DC/DC Converters *

Transcription

1 A Novel Concept in Integrating PFC and DC/DC Converters * Pit-Leong Wong and Fred C. Lee Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 406 USA Abstract-Many projects have researched single-stage power factor correction (PFC), looking for ways to simplify the circuitry. However, the reduction of control dimensions in single-stage PFC circuits generates common problems such as variable bus voltage, inferior power factor and high switch stresses. This paper proposes a new concept in integrating PFC and DC/DC converters. The control dimensions are not reduced. Therefore, the power factor is not sacrificed because of the output voltage regulation. The bus voltage can also be controlled. Based on this concept, a family of circuits can be derived. Simulation results are presented to verify the concept. Calculation and analysis show that this concept can also improve the system s overall efficiency. I. INTRODUCTION In order to reduce the impact on the electrical networks, power factor correction (PFC) is required in power supplies. The conventional methods are the two-stage approaches, which only add a PFC circuit before the DC/DC converter to shape the input current. However, the two-stage approaches increase both the complexities and the costs of the power supplies, since there are more components and control circuits involved in the systems. Lots of researches have been conducted to integrate the PFC circuits and the DC/DC converters. These single-stage PFC approaches are able to reduce the complexity of the whole system, but the system s performance is compromised. The drawbacks of the conventional single stage PFC include inferior power factor, higher component stress, lower overall efficiency, variable bus voltages, etc. The past research projects have tried to overcome these drawbacks, but none of them was effective. The reason for the ongoing problems is that there are philosophical defects in the single-stage concept. For the power supplies with PFC, there are basically two different requirements: to shape the input currents and to regulate the output voltages. The controls to achieve these two loops are not always the same for all the input voltage ranges and power levels. For the two-stage approaches, there are two control dimensions in the systems. Each of the two requirements can be satisfied by the corresponding control. Thus, the power factor and the DC regulation can be achieved for all the input voltage ranges and power levels. However, for the single-stage approaches, there is only one control dimension in the system. Usually, the control only deals with the DC regulation of the output voltages. The power factor of the input current has to be achieved freely by careful design of the components in the circuit. Thus, the design of the components is critical to the performances of the circuits. The resonant concept has been very popular. However, as for any method, the component design only gives optimal performance at a certain point. When the operation point changes, the performance has to be sacrificed. The input voltage ranges and output power levels of the PFC circuit are always so wide that the performances cannot be satisfactory for some operation regions. Because these philosophical defects of the single-stage PFC concept cannot be overcome, after so many years of * This work was supported by ASCOM, and made use of the ERC shared facilities supported by the National Science Foundation under award number EEC

2 intensive research, the concept is only utilized in some low power level applications in which the circuit performances are not critical. For the higher power level applications in which the requirements of the input power factor and the efficiency are high, there is no chance for the single-stage PFC concept. This paper presents a novel concept at integrating the PFC and DC/DC stages in order to reduce the complexity and improve the efficiency of the whole system. However, it is conceptually different from the existing single-stage concept. There are two control dimensions in the proposed concept. Thus, the power factor of the circuit is not compromised for all the operation ranges. The bus voltage can also be controlled as it is in the two-stage approaches. With the proposed concept, a family of converters can be derived. II. DERIVATION OF THE PROPOSED CONCEPT The concept starts with the simplification of the two-stage approaches. A common two-stage approach for the server application with power level of kw and above is shown in Fig.. The PFC stage is a boost converter, and the DC/DC stage is a full bridge converter. The bus capacitor with voltage is used to seperate these two stages. main current path when the circuit operates at low-line input with the range switch Q on. Q Fig.. Half-bridge PFC circuit with range switch. As shown in Fig., the body diodes of the MOSFETs work in the same way as the output diode in the boost converters. Due to the inferior reverse recovery characteristics of the body diode, the half-bridge PFC is impractical to operate in continuous current mode (CCM) without soft-switching techniques. Zero-voltage transition (ZVT) is a soft-switching technique with superior performance for MOSFETs. To implement ZVT for the half-bridge PFC, another leg and a resonant inductor are required, as shown in Fig. 3. Of course, this topology is too complicated to be practical. Together with the DC/DC stage, there are eight MOSFETs in the circuit. L Main switches Aux. switches v s L L r L r N p PFC stage DC/DC stage Fig.. A common two-stage PFC circuit. One drawback of the boost PFC is the low efficiency at low line where the input current is large. The two series diodes in the rectifier bridge are the main cause of the low-line efficiency defect. There are three semiconductor devices, two rectifier diodes and one switch or output diode, in the main current path of the boost PFC. The half-bridge or totem-pole topologies, proposed by Salmon [], as shown in Fig., can reduce the semiconductor devices to two in the Fig. 3. Half-bridge PFC circuit with ZVT soft-switching. The topology of the half-bridge PFC combined with the ZVT circuit is similar to that of the full-bridge DC/DC converter. The proposed concept combines these two full-bridges, as shown in Fig. 4. In order to control the input power factor and regulate the output voltage, there requires two control dimensions as discussed previously. The two switches on the same leg are always complementary to each other. There is only one control dimension for one leg. For the two legs in the full-bridge topology, two control dimensions are required. The proposed concept utilizes the control dimension of the duty cycle to deal with the input

3 power factor, and utilizes the control dimension of the phase shift between the two legs to deal with the output voltage regulation. If the two controls are totally independent of each other, the input power factor and the output voltage regulation will not be compromised. S S 4 i L L r L i N p p S S 3 Fig. 4. Combination of the half-bridge PFC and the full-bridge DC/DC. However, the duty cycle control of the leg and the phase shift between the two legs are not totally decoupled. Analysis of the relationship between these two control dimensions follows. For Fig. 4, during the turn-on of S, either S3 or S4 can be on. Only when both S and S4 are on can the bus voltage be applied to the transformer. Assuming the duty cycle ratio of S is D, the duty cycle ratio that applies to the transformer cannot be larger than D. Moreover, the duty cycle ratio of S is (-D). Because the voltage-second of the transformer needs to be balanced for each switching cycle, the maximum duty cycle ratio applied to the transformer cannot be larger than Min(D, -D). In order to fully utilize the transformer, a larger duty cycle ratio is preferred. Thus, for the legs, duty cycle ratios around 0.5 with a narrow range are preferred. However, in order to achieve good power factor, the duty cycle ratio of the PFC stage needs to vary according to the input voltages. For the boost PFC circuit operating in CCM or boundary current mode, the duty cycle ratio needs to approximately follow Formula, in which V inp is the peak value of the input voltage, is the average value of the bus voltage, and ω is the radian frequency of the input line. For the half-bridge PFC circuit with the range switch Q open, the MOSFET S works as the boost switch, and the MOSFET S works as the boost diode during the positive half-line cycle. For the negative half-line cycle, S works as the boost switch, and S works as the boost diode. During the positive half-line cycle, the duty cycle ratio of S should also follow Formula. The maximum duty cycle ratio is close to one, which is too large for the concept to be practical. V V in inp D = = sinωt () V V B B Fortunately, when the range switch Q is on, the duty cycle ratio approximately follows Formula. The maximum duty cycle ratio is close to 0.5. D = V V in B = V V inp B sinωt The duty cycle ratio varies during a half-line cycle as shown in Fig. 5. For both cases of the range, switch Q is on and off. The range switch is off when the input line voltage is high, and the range is on when the line voltage is low. The duty cycle ratio also varies with the input voltage ranges. By switching the range switch Q, the maximum PFC duty cycle ratio can be reduced =400VDC V in =80, 0, 65 VAC T is off time =400VDC V in =90, 0, 30 VAC T is on time Fig. 5. PFC duty cycle ratio over a half line cycle. As discussed previously, the minimum PFC duty cycle ratio also needs to be limited. By increasing the bus voltage, the minimum PFC duty cycle ratio can be increased. With the calculation of Formula, the bus voltage needs to be increased to 500VDC to limit the minimum PFC duty cycle ratio to be larger than 0.5 for all the input voltage ranges. By ()

4 switching the range switch Q at the appropriate instants, the PFC duty cycle ratio ranges can be limited to 0.5~0.75, as shown in Fig. 6. In this case, the maximum duty cycle applied to the transformer is 0.5. Considering the bi-directional utilization of the transformer, the maximum voltage-second applied to the transformer is 0.5. The range switch Q needs to be switched twice in a line cycle as shown in Fig. 6. The switching frequency is 0Hz. For such a low switching frequency, the switching loss is small, and slow switches can be used =500VDC V in =80, 0, 65 VAC time =500VDC V in =90, 0, 30 VAC time Fig. 6. Reduction of the PFC duty cycle ratio ranges. III. IMPROVEMENTS OF THE CONCEPT As mentioned previously, due to the inferior reverse recovery performances of the MOSFET body diodes, it is impractical for the half-bridge PFC circuit to work in CCM without soft-switching. Moreover, one of the major benefits of the full-bridge DC/DC topology is that the phase-shift soft-switching can be implemented easily. The proposed concept also seeks the possibility of implementing soft-switching without adding more components. The body diode reverse recovery problems happen when the circuit tries to force the synchronous current to commutate through the MOSFET. During the period when MOSFET S works as the boost rectifier, the input current i L flows through S from source to drain, as shown in Fig. 4. The reverse recovery of MOSFET S may burn the switches when MOSFET S tries to turn on in the next switching cycle. In order to avoid this reverse recovery problem, the input current i L flowing through S needs to be commutated before the turn-on of MOSFET S in the next switching cycle. During the period when MOSFET S works as the boost rectifier, there is a period in which MOSFET S3 is turned on so that the bus voltage can be applied to the transformer. During this period, the load current is reflected to the primary side of the transformer as the current i p shown in Fig. 4. The currents i L and i p flow through MOSFET S from different directions. If the current i p is larger than the current i L, the body diode of MOSFET S does not carry any current at all before the turn on of MOSFET S. Thus, the reverse recovery problem is solved and the PFC circuit can work in CCM. In this case, the net current flows through MOSFET S from drain to source. There needs to be a gate signal to turn on MOSFET S during the period. The gate signal of MOSFET S needs to be removed before the turn-on of MOSFET S in the next switching cycle. Due to the parasitic inductance L r shown in Fig. 4, MOSFET S is turned on at zero voltage following the same phase-shift soft-switching mechanism as in the full-bridge DC/DC topologies. In the positive half-line cycle, MOSFET S works as the boost rectifier. When MOSFET S is turned off, the input current flows through the body diode of MOSFET S. The drain-to-source voltage is reduced to zero before the gate signal is applied to MOSFET S. Thus, MOSFET S is also turned on at zero voltage. The zero voltage turn-on of MOSFETs S3 and S4 can also be achieved due to the same mechanism as in the phase-shift full-bridge DC/DC topologies. For the negative half-line cycle, the operation is similar, unless the roles of MOSFETs S and S are exchanged. In this case, the reverse recovery problems of the half-bridge PFC can be solved and zero-voltage turn-on can be achieved for all four MOSFETs in the converter. The premise is that the reflect load current i p needs to be larger

5 than the input current i L. For the low input voltages, the peak input current is larger. Calculation shows that, in order to achieve soft-switching for all the input voltage ranges, the DC/DC stage has to work in discontinuous current mode (DCM) in order to increase the reflected load current so that current i p can be larger than the input current i L for all the cases. Of course, increasing the ripples of the input current i L can also help to achieve soft-switching. However, neither solution is desirable in terms of conduction losses in the MOSFETs. Increasing of the input current ripple also imposes stresses on the input filters. The problem is caused by the large input current. If the input current can be reduced, soft-switching will be much easier to achieve. The circuit in Fig. 4 has two legs. If both legs can be utilized for the PFC stage, the input current can be reduced to half. This concept is shown in Fig. 7. There are actually two sets of half-bridge PFC circuits interleaved. Each input inductor carries half of the total input current. The input inductor current is also the current that flows through the MOSFET body diodes, which is what needs to be soft-switched. Compared with the circuit shown in Fig. 4, only half of the input current needs to be soft-switched. The premise of soft-switching is much easier to meet. Thus, the DC/DC stage can be designed to work in CCM. Moreover, the interleaving characteristics of the two half-bridge PFC converters reduce the total input current ripple. For the same input current ripple requirements, the inductor current ripples in Fig. 7 can be much larger than those in Fig. 4. As discussed previously, increasing of the inductor current ripple can also help the MOSFETs achieve soft-switching of. / Q / v s S S 4 L in - V in + L r N p b L in S S 3 Fig. 7. Interleaving PFC stages to improve circuit performances. Compared to the circuit shown in Fig. 4, the circuit in Fig. 7 has superior performance. The penalty is that one more a input inductor needs to be used, which increases the complexity of the circuit. Fortunately, integrated inductor technologies allow the two input inductors to be built on the same magnetic core in order to reduce the component count of the circuit [4, 5]. IV. CIRCUIT OPERATION AND SIMULATION RESULTS To illustrate circuit operation, the key waveforms are shown in Fig. 8. The waveforms are for the positive half-line cycle, during which MOSFETs S and S3 work as the boost switches. The waveforms for the negative half line cycle are similar, unless MOSFETs S and S4 work as the boost switches. The gate signals of the MOSFETs on the same leg are always complementary to each other with a dead time to achieve soft-switching. S S S3 S4 V ab Vs Ir If Fig. 8. Key waveforms of the circuit operation. The duty cycle ratios of S and S3 modulate according to the input current waveforms, following a control mechanism similar to those in boost PFC converters. The duty cycle ratio modulations of S and S3 are the turn-off edge modulation, represented by the arrows in Fig. 8. The turn-on edges of the gate signals of S and S3 marked with circles in Fig. 8 are to control the phase shift between the two legs, which is the voltage-second applied to the transformer. Only when both the MOSFETs on the diagonal (S/S4 and S/S3) are on can the bus voltage be applied to the transformer, represented by the waveform of V ab in Fig. 8. During a line cycle, although the duty cycle of S and S3 vary due to PFC control, the voltage-second applied to the transformer is always the phase

6 shift between the two legs, which can be made constant in each switching cycle so that regulated output voltages can be achieved. The current through the primary side of the transformer is the waveform i r shown in Fig. 8. The waveform explains the soft-switching of the MOSFETs, as discussed previously. During the positive half-line cycle, the soft-switching of S and S4 is much easier to achieve than that of S and S3, due to the current bias caused by the input current. For the negative half-line cycle, the soft-switching of S and S3 is easier. Due to the soft-switching of all the MOSFETs in the circuit, both the PFC and DC/DC circuits can work in CCM. The waveforms shown in Fig. 8 are valid for both cases in which the range switch Q is either on or off. As shown in Fig. 6, the range switch Q needs to be switched twice in a line cycle when the duty cycle ratio reaches 0.5 or A control circuit can easily implement this function by monitoring the error signal in the control loop. The duty cycle ratio jumps when Q switches. A feed forward compensation circuit can offset this jump in the control to enable the circuit to work smoothly. The detail design of the controller is not included in this paper. The simulation waveforms with close-loop controller are shown in Fig. 9. The duty cycle ratio is limited within the range of 0.5~0.75. Although there are jumps of the duty cycle ratio, the input current is still smooth with perfect power factor. Input current Fig. 9. and input current waveforms. In order to compare the efficiency of the proposed circuit in Fig. 7 with the conventional approach shown in Fig., simulations are carried out for both cases. The breakdown of the conduction losses in semiconductors is shown in Table. The losses in Table are the average value over a line cycle. The operating point for both cases is Vin=VAC rms, Vo=48VDC, and Po=kW. The bridge duty cycle ratio closest to 0.5 gives better overall efficiency. For the conventional approach, because there is no limitation for the duty cycle ratio, the duty cycle ratio is set to be 0.45 in the simulation. For the proposed circuit, because the maximum duty cycle ratio for the bridge is 0.5, the duty cycle ratio is set to be 0. in the simulation. For each case, the duty cycle ratio has a margin of 0.05 to its maximum value for the soft-switching losses and the transient considerations. Actually, for the applications in which hold-up time is required such as in computer power suppliers, the maximum duty cycle ratio should be reduced for hold-up time. However, for the proposed circuit, the maximum duty cycle ratio is not affected by the hold up time. The maximum duty cycle ratio is limited because of the PFC requirements of the input current. During hold-up time, when the input voltage is lost, there is no need of PFC. During the period, the duty cycle ratio can be increased to 0.5. Thus, the duty cycle ratio design for the steady state is not affected. Table. Semiconductor conduction losses breakdown (W) Input diodes PFC switches Bridge switches Sec. diodes Cond. losses Conventional Proposal For the items in Table, the input diodes are the four diodes in input rectifier bridge in the conventional approach. For the proposed circuit, the number of the input diodes is reduced to two. Moreover, the two diodes carry currents for only a part of the line cycle. Thus, the conduction losses of the input diodes are reduced by half in the proposed circuit. The PFC switches in the conventional approach are the boost switch and the boost rectifier. For the proposed circuit, the PFC switch is the range switch Q. Because it conducts only during the part of the line cycle in which the input current is small, the conduction losses of switch Q are much smaller than those of the PFC switches in the conventional approaches. Moreover, switch Q in the proposed circuit switches at 0Hz. The switching losses should be much

7 smaller than those of the PFC switches in conventional approaches. Because the duty cycle ratio of the proposed circuit is smaller than that in the conventional circuit, the four bridge switches of the proposed converter have larger conduction losses. For the existing single-stage PFC circuits, the switches usually carry the sum of the current in the PFC and DC/DC stages. The conduction losses of the switches are much larger than those of the conventional circuits in the DC/DC stage. The situation is different in the proposed circuit. For the proposed circuit as shown in Fig. 7 in the positive half-line cycle, the currents through switches S and S4 are i ( i L p ), and the currents through switches S and S3 are i ( i + L ), where i p is the reflected load current and i L is the p input PFC current. For the negative half line cycle, the current through S and S3 are ( i i L ), and the currents p through switches S and S4 are ( i + i L ). For the p conventional circuit, the currents through all the switches are i p. The bridge switches in the proposed circuit have larger conduction losses because they deal with both the input PFC and the output voltage regulation. The secondary rectifiers in the proposed circuit have slightly larger conduction losses, which is also due to the smaller bridge duty cycle ratio. In summary, Table shows that in total, the semiconductor conduction losses in the proposed circuit are about 7W less than in the conventional two-stage approach. Moreover, in the conventional two-stage circuit, the switching losses of the boost PFC are a significant part of the total losses. In the proposed circuit, the bridge switches are soft-switched, which minimizes the switching losses. These are the major performance improvements of the proposed circuit. Compared with the existing single-stage PFC circuits, the proposed circuit has perfect input power factor, fixed bus voltage, soft-switching, and better overall efficiency than the two-stage approaches. Because the proposed circuit has more control dimensions than the existing single-stage circuits, it does not have the insurmountable problems faced by the single-stage circuits. Of course, the controller of the proposed circuit is more complicated than those in the single stage converters. IV. CONCEPT EXTENSIONS The basic concept of the proposed circuit is to increase the control dimensions of the circuit by modifying the control mechanism so that the performances of the circuit are not compromised when integrating the PFC stage and the DC/DC stage. The circuit shown in Fig. 7 is based on the full-bridge DC/DC converters. The two-switch forward is also a very common DC/DC topology for applications with a power level around kw. The proposed concept can also be applied to the two-stage forward topologies. This topology is shown in Fig. 0. Switches S, S and diodes D, D form the two-switch forward DC/DC topology. Switch S, diode D and input inductor Lin are a set of boost PFC circuits. Switch S, diode D and input inductor Lin are another set of boost PFC circuits. When both the switches S and S are on, the bus voltage is applied to the transformer. For the positive half line cycle, only the set of PFC circuit with switch S and D work for input power factor correction. Switch S is turned on for a fixed duty cycle ratio during the period when switch S is on to regulate the output voltages. The reset of the transformer happens when both switches are off and the diodes are on. During the negative half-line cycle, only the set of PFC circuits with switch S and D work for input PFC. Switch S is controlled to regulate the output voltages. VB / Q - V in + / D S v L s in L in S b N p D Fig. 0. Application of the concept in two-switch forward DC/DC circuit. Switch Q works the same way as it does in the circuit shown in Fig. 7. The duty cycle ratio range for the PFC circuit is also limited to 0.5~0.75. Thus, the maximum duty cycle ratio for the transformer is 0.5. There is sufficient time a

8 for the transformer to reset. The PFC circuits in Fig. 0 eliminate a diode in the input current path as is done by the half-bridge PFC circuits to improve the efficiency of the PFC circuits. Because the body diodes of the MOSFETs are not used for the PFC rectifier, the PFC circuit can work in CCM even without soft-switching. As discussed previously, S switches during the positive half-line cycle, which generates some negative currents in the input inductor Lin. However, because the duty cycle ratio of S is always smaller than that of the PFC, the negative currents are very small compared to the total input current. Simulation shows that the impact of the negative current on the input power factor is negligible. Compared to the circuit in Fig. 7, the major advantage of the circuit in Fig. 0 is the simplicity. The two MOSFETs are reduced. However, the power level of the circuit in Fig. 0 is limited for the same reasons it is limited in the two-switch forward DC/DC topologies. V. CONCLUSION This paper presents a new way to integrate PFC and DC/DC converters. The number of control dimensions of the proposed concept is not reduced as it is in existing single-stage PFC circuits. Thus, the proposed concept can avoid the problems that the existing single stage PFC circuits cannot overcome, such as variable bus voltage and inferior input power factor. The proposed concept has the same perfect input power factor and fixed bus voltages as the two-stage PFC approaches. Moreover, the soft-switching of the MOSFETs in the proposed concept enables the half-bridge PFC topology to work in CCM without extra soft-switching circuits. Simulation results show that the proposed concept has lower overall conduction loss in the semiconductors. This is an excellent way to further improve the overall efficiency of the state-of-the-art PFC and DC/DC circuits. The concept can also be extended to the two-switch forward DC/DC topology. The derived circuit based on the two-switch forward DC/DC topology is simpler, and also generates CCM input current, but the performance is not as good. REFERENCES [] J. Salmon, Techniques for minimizing the input current distortion of the current-controlled single-phase boost rectifier, APEC 99 [] G. Hua, C.S. Leu and F.C. Lee, Novel zero-voltage-transition PWM converters,'' IEEE Power Electronics Specialists Conf. (PESC) Rec., June 99, pp [3] W. Chen, F. C. Lee, M. Javanovic and J. Sabate, A comparative study of a class of full bridge zero-voltage-switched PWM converter, APEC 995, pp [4] Pit-Leong Wong and Fred C. Lee, Interleaving to reduce reverse recovery loss in power factor correction circuits, CPES Annual Seminar 000, and IAS 000. [5] W. Chen and F. C. Lee, Integrated inductor scheme for multi-module interleaved quasi-square-wave DC/DC converter, APEC 999.