IBM Technology Symposium

Transcription

1 IBM Technology Symposium Impact of Input Voltage on Server PSU- Efficiency, Power Density and Cost Design. Build. Ship. Service. Sriram Chandrasekaran November 13, 2012

2 Presentation Outline Redundant Server PSU Performance Metrics Efficiency, Power Density, Features Architectural Overview of Server PSU Overview of Converter Topologies Impact of input voltage on PSU Metrics AC Input voltage High line/low line 277Vac Dual input AC DC Input voltage 380Vdc 260Vdc 48Vdc 2

3 Redundant Server PSU Performance Metrics Efficiency 80 PLUS Certification 230V Internal Redundant % of Rated Load 10% 20% 50% 100% 80 PLUS Bronze % 85% 81% 80 PLUS Silver % 89% 85% 80 PLUS Gold % 92% 88% 80 PLUS Platinum % 94% 91% 80 PLUS Titanium 90% 94% 96% 91% Processed Power Density: > 40W/in 3 Features Sleep Mode Operation High Accuracy Reporting No-load input power Peak power profiles with throttling Event Recording Field-upgradability of firmware 3

4 FlexPower 3kW PSU 230Vin PSU Efficiency (%) % Load % Load Efficiency

5 PSU Block Diagram 1-φAC VAC EMI Filter Rectifier & Inrush Control Boost PFC (80 ~100kHz) Isolated DC/DC (80 ~100kHz) ~400V ORing FETs V 1 = 12V To power supply Bias & standby (80-100kHz) ORing FETs V sb = 12V Control Isolation Communication V hk To system 5

6 Control Block Diagram Boost PFC FET gating signals, Relay drive Primary and secondary side FET gating signals System V AC Digital PFC control Input current Bus voltage Switching Frequency Primary side monitoring and communication PFC Power & RMS algorithms Primary side digital controller Bus voltage, rectified current Isolation barrier Analog or Digital Control IC Voltage/current analog control DC/DC Controller Digital Isolator Output voltage, current signals PM Bus Digital Load share DC Algorithms Housekeeping and black box 8 bit Silabs Micro controller Secondary side microcontroller 6

7 Converter Topologies Design. Build. Ship. Service.

8 Power Factor Correction (AC Bulk Vdc) Conventional Boost PFC Bridgeless Boost PFC D CH DC 1 L B1 D A1 R 1 DC 1 L LB1 D A1 D A2 C H L B2 C R SA1 C H N S A1 S A2 R 2 DC 2 DC 2 Robust, time tested topology DCM, BM (Boundary Mode), CCM Interleaving for higher power Innovations Soft switching variations Magnetics design Control Higher efficiency EMI compliance is challenging Innovations EMI compliance Magnetics Design Control 8

9 Isolated DC/DC Conversion (Bulk Vdc 12V) Primary side PWM Single Stage (1) Phase-shifted Full Bridge (2) Half-Bridge (3) 2T forward Two-Stage (1) Boost + Half-bridge (50% duty cycle) (2) Buck + Half-bridge (50% duty cycle) Resonant Frequency modulated LLC (1) Boost + fixed frequency LLC (2) Buck + fixed frequency LLC Interleaving variations for higher power and ripple cancellation Secondary side Synchronous Rectification Current doublers Coupled inductors Center-tapped/single winding variations 9

10 Impact on Input Voltage on PSU Design. Build. Ship. Service.

11 Single Phase AC Input Universal line (90Vac 264Vac): <1000W High line only (180Vac 264Vac): >1000W, >30W/in 3 High line/de-rated low line 277Vac 11

12 Single Phase AC Input 1-φAC AC DC EMI + PFC DC BUS (400V nom) DC DC Isolated DC/DC V o = 12V DC REVERSE AIR FLOW FORWARD AIR FLOW Impact of input voltage range is dominant on design of the PFC power train Efficiency and power density 120Hz ripple on DC bus E-cap life Second order impact on DC/DC design from air-flow direction Packaging and Layout 12

13 277Vac 277Vac is Line-Neutral (Y) from 480Vac Line-Line ( ) input Input voltage max is 277Vac+10% = 305V Higher efficiency and density due to lower input current Front-End AC inlet X and Y caps 305V rated safety caps are available in the market now Rectifier/PFC Stage Peak Rectified 305Vac = 430Vdc Voltage rating switching devices can stay at 600V is Vbulk < 480V (80% derating) 500V rated bulk capacitance required High V bulk results in lower C bulk for given hold-up spec PF and THD impact due to lower input current 13

14 277Vac DC/DC Stage No change to primary side if Vbulk < 480V 600V/650V devices can continue to be used For PWM topologies, SR FET voltage rating may increase from 60V to 75V Device portfolio not as broad in the 75V space Cost and efficiency impact No impact to SRs for resonant topologies SR Voltage rating is 2X output voltage 14

15 277Vac Hold-up Capacitance Requirement C = 2P 1 o,max k C V 2 bus, nom η Vn D o t max 2 t H Bulk capacitance/watt for 10ms of hold-up P o Maximum output power t H Hold-up time, 10ms V bus,nom Bulk full load D max Max allowable duty cycle,45% V o Output voltage, 12.2V V dropout Drop out voltage, V o n t /D max n t Transformer turns ratio, 12:1 k C capacitor derating factor, 80% η DC/DC Stage efficiency, 96% 33% reduction in C bulk Bulk capacitance requirement is reduced at higher Vbulk. Availability of 500V caps (105C, 2000hr) is limited Best option is to build a series/parallel cap bank Impact to power density Largest capacitance in 30x50 can size is 300uF Large drop in foil gain results in reduction of C/m 2 voltage rating increases from 450V to 500V 15

16 277Vac PFC Efficiency Improvement PFC Efficiency comparison at 3kW Modulation range of bulk voltage as a function of load is limited with 277Vac Gains at light loads are insignificant due to dominant switching losses PFC design is optimized for reduced current at 277Vac Density advantage Higher inductance boost choke Bulk cap availability is the limiting factor for increasing density 16

17 Dual Redundant AC Input AC input fed into PSU through two AC inlets (FEED1 and FEED2) FEED 1 is the default input PSU monitors both AC inputs continuously PSU should switch to FEED 2 in the event of AC FAIL on FEED 1 PSU should switch back to FEED 1 when good AC is available Density and Cost impact due to AC Transfer Circuitry (Relay network) Monitoring and Control circuitry No efficiency impact 17

18 Dual Redundant AC Input AC Transfer Circuit L1 RLY_LINE L1 N1 L2 N2 L AC_DETECT L2 N1 RLY_NEUT RLY0 PRI_RTN N PSU N2 RLY1 PRI_RTN 18

19 DC Input PSU 380Vdc High Voltage DC Input 2006 study from Lawrence Berkeley labs showed 7% reduction in input power Hold-up requirements will dictate size of front-end 160Vdc 265Vdc Pass-through from Standby Power System 48Vdc PSU to operate from AC input and DC input. In the event of AC failure, DC input will be made available with specified duration PSU will power up within specified duration after availability of GOOD DC power 36VDC 72VDC input (from battery bank) Reverse polarity protection Hold-up time of 2ms -8ms High current makes design of front-end challenging 19

20 DC Input PSU Block Diagram Vdc EMI Filter Inrush Control & Reverse Polarity Protection or Bridge Rectifier Front-end Boost (80 ~100kHz) Isolated DC/DC (80 ~100kHz) ORing FETs V 1 = 12V To power supply Bias & standby (80-100kHz) ORing FETs V sb = 12V Control Isolation Communication V hk To system 20

21 High Voltage 380Vdc Input Efficiency improvement of front-end boost due to Elimination of Bridge Rectifier Near Unity Step-up ratio from 380Vdc to 430Vdc max ~99% Density Improvement due to reduced input current No significant change in PSU architecture Simplified RMS detection and control algorithms on front-end MPPF/MPF high voltage caps used for DM and CM filtering No impact to DC/DC stage or AUX stage 21

22 Front-End Boost Efficiency (3kW) Vin = 380V, Vo = 420V, fs= 60kHz Efficiency estimations are based on best-available component models 22

23 High Voltage 380Vdc Input - Connectors We have looked at Positronics connectors as an option We also expect front-loading designs where input/output terminals are on same connector system 23

24 DC Input PSU (165Vdc 260Vdc) 160Vdc 265Vdc Pass-through from Standby Power System PSU to operate from AC input and DC input In the event of AC failure, DC input will be made available with specified duration PSU will power up from DC input within specified duration from instant of availability of GOOD DC power No change in PSU architecture AC detection/metering algorithm has to accommodate DC input for Determining turn-on/turn-off thresholds Reporting Input power/voltage/current 24

25 DC Input PSU (48VDC) Counterparts of AC input PSUs in same form factor at same or lower power levels Reduced hold-up time (2ms to 8ms) Reverse Polarity Protection is required Achieving high densities at higher power levels (>1000W) is a challenge due to high input current 25

26 Input fuse and EMI Filter Common-Mode Choke based on UU-core At 36Vin/3kW input current is ~85A For every mω, power loss is 7.225W 4in of 14AWG wire has a resistance of 1mΩat 75C Multi-filar magnet wire or copper stampings UU-core geometry results in better window utilization Low L/High C filter to minimize turns, hence copper loss 26

27 Integrated Boost Choke for Front-End g 1 g 2 g 3 φl1 φl2 φl3 φ φ C L 2 φ L 3 φ C DT s φ C 4 D T s 3 T s 3 boost chokes integrated within a single ferrite core assembly (54mm(L) x 24mm (W) x 40mm (H)) Flux and currents are interleaved resulting low core and copper loss Fluxes are interleaved in ~72% of core volume (very low core loss) Per phase inductance of 28uH 27

28 Estimated Efficiency at 48Vdc/3kW 96 PSU Efficiency (%) % Load % Eff % Load PSU efficiency is dominated by conduction loss due to high input and output currents As a result, efficiency peaks at light loads and decreases down to 100% load due to I 2 R loss 28

29 Summary Impact of input voltage on redundant server PSU architecture and metrics were covered. No significant changes in power converter topologies other than obvious updates to component selection Higher input voltages lead to higher efficiency Density improvements are dictated by advancements in component technologies (1) 500V E-cap availability for 277Vac designs (2) High current front-end designs for 48Vdc designs High Voltage DC input PSUs are more efficient and simpler designs Require re-architecting of the power delivery infrastructure to server rack 29