Gallium Nitride Based Power Electronic Devices and Converters NPEC 2015, Session 17, Tutorial 3,

Transcription

1 Gallium Nitride Based Power Electronic Devices and Converters NPEC 2015, Session 17, Tutorial 3, DC-DC Converters Based on Silicon and GaN Devices Dr. G Narayanan EE Dept., IISc Bangalore

2 DC DC Buck Converter A buck converter comprises of: A switching network that produces a pulsed voltage waveform Passive elements (L and C) for filtering purpose Ideally, no energy loss in switches, L and C Power switching converters are quite efficient GaN devices expected to improve the efficiency further

3 Pulsed Voltage Applied Without Filtering For a resistive load, current waveform has the same shape as the voltage waveform Current waveform is not smooth and has a high ripple content Filtering is required

4 Inductive Filter With an inductive filter, the current waveform is smoother and has less ripple content. Average voltage across L is zero. The entire average voltage gets applied across the load. Considerable portion of the ripple voltage in the applied waveform is dropped across the inductor.

5 LC Filter Capacitor C across the load provides a path for the ripple current through L Mainly DC current flows through the load; the ripple current through L is triangular For an acceptable ripple, L and C reduce with increase in switching frequency

6 Single-Pole Double-Throw Switch for Buck Conversion The load (with filter) should be connected directly across the dc source during one interval. The load should be shorted in the other interval. A single-pole double-throw (SPDT) switch is required.

7 DC-DC Buck Converter with a Generic Single- Pole Double-Throw switch Transistor is switched on and off with certain duty ratio D at a frequency f Diode comes into conduction (freewheels) when the transistor is turned off Conduction and switching losses in transistor and diode; total device loss determines heat sink size If switching energy loss is lower, switching frequency could be higher. Higher the switching frequency, lower the filter size

8 Synchronous Buck Converter Two transistors are switched in a complementary fashion Forward conduction loss in the first switch, reverse conduction loss in the second switch, switching losses in both; device loss decides heat sink size If switching energy loss is lower, switching frequency could be higher. Higher the switching frequency, lower the filter size

9 Voltage Buck Converter is a Current Boost Converter V IN I IN = V OUT I OUT OR V OUT / V IN = I IN / I OUT

10 A Current Buck Converter

11 Voltage Boost Converter I IN L P T 2 i + V IN C + V OUT - T 1 -

12 Electronic Realization of the SPDT Switch in Boost Converter

13 An Ideal Switch No voltage drop during conduction (forward drop) No leakage current in blocking state Instantaneous transition between on and off states No energy loss since either voltage or current is always zero True for on-state, off-state and also switching transitions

14 Wish List for Any New Device Reduced forward conduction drop Leakage current and blocking state loss should continue to be negligible Faster device turn-on and turn-off under inductive switching condition Reduced switching energy loss for every transition Reduced total power loss in the active device Compatible diode with low forward drop and reverse recovery loss OR, low reverse conduction drop of the device

15 List of GaN High Electron Mobility Transistors (HEMT) and their Si Counterparts A. Pal, Study on GaN based power semiconductor devices, ME Project Report, IISc, June 2015.

16 Comparison of commercial Si and GaN (normally off) devices Source: A. Pal and G. Narayanan, A survey on commercially available GaN based power electronic switches and GaN-based high-performance dc-dc converters, Technical Report, URL:

17 Comparison of commercial Si and GaN (normally off) devices contd. Source: Same as before Device capacitances and charges are greatly reduced with GaN; hence lower switching transitions times and higher switching frequency (500 khz 2 MHz)

18 Loss in transistor and diode in dc-dc buck converter P = DI R, + ( E + E ) f + V I 2 T o DS on on off sw in DSS P = (1 D) I V + E f D o D rr sw GaN device has marginally lower Rds, very low Eon and Eoff, significant leakage current Idss, and high reverse conduction drop Advantages: Very low Eon and Eoff; very fast switching transitions; higher switching frequency; smaller filter components

19 Typical switching transitions i v v i t Instantaneous power loss is v*i Peak instantaneous power = V*I Energy loss is area under product curve Energy loss depends on V, I and transition times Low transition times for GaN t

20 Gate-charge characteristic

21 Turn-on transition device voltage and gate voltage Anirban Pal, Study on GaN based power semiconductor devices, ME Project Report, IISc, June 2015.

22 Turn-off transition device voltage and gate voltage

23 Size and packaging of GaN Dimensions are in mm as opposed to cm Impressive size reduction Land grid array (LGA) package Fingers to be connected at board level Package is more complicated to handle at board level PCB and related technologies required are more challenging From device datasheet

24 Heat flow paths and thermal equivalent circuit for GaN device Some heat flows out through the Si substrate Rest (most) of the heat flows down through solder bars Heat gets spread over the drain and source pads in the PCB. (PCB is the heat sink!) Heat spreads to other PCB layers through epoxy and/or vias Heat finally gets convected into atmosphere

25 Thank you! Questions?

26 Gallium Nitride Based Power Electronic Devices and Converters NPEC 2015, Session 17, Tutorial 3, Practical GaN based DC-DC Converter V Chandrasekar Power Electronics Group CDAC-Thiruvananthapuram vvcsekar@cdactvm.in

27 Outline of Presentation Introduction to DC-DC Converter system Requirement of SMPC Challenges in GaN Based SMPC Selection of components Recommended Layout practices Specification and schematics Performance Evaluation Demonstration of a DC-DC converter system

28 Requirement of SMPC SMPC Operate stably at Higher Voltage,at Higher temperature &at High frequency No harm to Human body( no hazardous materials ) Recent Trends in SMPC are High Power density Performance Enhancement with Device materials Packaging of Converters Silicon Carbide & Gallium Nitride Two very important wide band gap materials showing great promise for the future for both switching and RF power applications are Gallium Nitride (GaN) and Silicon Carbide (SiC) Yole & NIT Japan

29 GaNSMPC Impact of GaN properties and its performance convergence EPC

30 Block Diagram of the SMPS POWER CIRCUIT INPUT (12V) OUTPUT T (3.3V) GATE DRIVE INTERFACE CIRCUIT PWM CONTROLLER

31 Specification of DC-DC converter Description of Parameter Value of Parameter Input Voltage Min 11.4 VDC Voltage Max 12.6 VDC Current Max * 530mA Output Voltage 3.3VDC Maximum Current 1.8 A Voltage tolerance 4% Ripple 5.0 % Load Regulation 1.0 % Maximum Power 6W Over Voltage VDC Protection Efficiency Better than 92% Description of Value of Parameter Parameter Losses, Max* 480mW Cooling Natural Cooled Power Density ~10 W/inch3 EMC CISPR 11 Safety CE Environmental IEC60571 Control Type Analog Control Application Target Power Supply for Digital Controller Frequency of >500kHz < 1MHz Operation Operational -10 to +70 degc Temperature Relative humidity 95% max Enclosure Encapsulated Enclosure

32 Challenges in DC-DC Converter Design of high immune controller and gate driver for GaN devices PCB Design of High frequency power and control circuits Design of passive and reactive components for high frequency environment Thermal design and encapsulation of the Converter

33 Switching Device comparison Parameters IRF7470 EPC2014C (Silicon MOSFET) (egan HEMT) Drain tosource voltage, V ds 40V 40V Continuousdrain current, I d 10A 10A Maximum Gate Source Voltage ± 12V -4V/6V On state Resistance 30 mohm 16mOhm Reverse body diode voltage V 1.8V Gate threshold 0.8-2V V Si-MoSFET Gate-to-Source Charge nC 0.7nC Internal gate resistance - 0.4Ω Gate to source leakage 200nA 2mA Body diode reverse recovery nC None charge Avalanche capable Yes Not rated Package SO-8 ( 4.8mmx5.8mm) LGA (1.087mmx1.702mm) 1.087mm 1.702mm egan HEMT

34 Selection of components Components Salient Features Package eganfet EPC2014C Enhancement mode Power Transistor LTC 3833 Step down DC/DC Controller LM5113 Half Bridge Gate Driver V DS =40V, R DS(on) =16mOhm, I D = 10A Ultra Low Q g Vin Range = 4.5 V to 38V High output accuracy Differential output sensing Frequency Prog. 200kHz 2MHz Fast Load Transient Response 5A, 100V Independent Hi & Lo side inputs 1.2/5A peak source / sink current Internal bootstrap voltage clamp Fast Propagation times ( 28nsTyp) VCC UVLO optimized for egan(3.5v) LGA ( Land Grid Array) 20-pin QFN ( 3mmx4mm) DSBGA ( 2mmx2mm)

35 Gate Drive Recommendations Gate voltage should not exceed 6V Separate pull up and pull down gate path Use single point to ground to avoid mixing high currents with gate drive and control currents Provide low gate drive impedance to prevent undesired turn on Gate driver should have Low inductance SMD package Output impedance 0.5Ω or less Operate down to 4.5V supply voltage Peak output current >5A at 5V supply Better than 5nS rise and fall times with 1nF load

36 Gate Drive Recommendations Reduce gate loop inductance Place driver close to the device(shorter than 0.5 inch) Place gate drive and return paths on top of one another Keep the gate drive and return path lengths minimum Small outline SMD package drivers with minimum lead inductance Limiting zenerdiodes are not recommended because of its capacitive effects

37 Suggested Layouts by the manufacturer Suggested Layout No of Layers Filled-via dual-sided termination 4 layers or more Dual-sided termination 4 layers or more Single-sided termination 2 layers or more Performance Cost Single sided Dual sided

38 PCB Layout of EPC egan HEMT EPC Recommended PCB Layout PCB Layout of CDAC fabricated DPT PCB Filled-Via-Dual sided

39 egansmps-layout details Pad to pad spacing -6mils Via to via spacing - 6mils Drill size -6mils Drill annular ring - 8mils 4 layer PCB with solder mask and legend on 1.6mm glass epoxy ENIG finish with PTH and SMD components, 70microns copper thickness, BBT testing required. Impedance matching not required. Track to track, track to via, track to pad, via to via, via to pad, pad to pad clearance: 6mils, All vias should be non conductively filled, Via size: drill-6mils, annular ring 8-mils.

40 Recommended Layout Practices GaN FETs placed close to the PWM driver Minimizing the loop length and area of bootstrap capacitor circuit Optional gate resistor is provided for damping the oscillations Drain and source connections are routed in alternate planes to minimize the inductance Double sided terminations to enhance current carrying capacity Gate-source circuit and drain-source circuits are placed orthogonal to reduce coupling between the circuits Routing is replaced with copper pour 2oz copper is used in all layers to ensure the lowest possible connection resistance In controller circuit, differential pairs of signals are routed as close to identical to eliminate the effect of noise injection

41 Recommended Layout Practices Parallel plate overlap Coplanar plate overlap The inductance per unit length for the coplanar arrangement is approximately 5.7 times higher than the parallel plate configuration

42 PCB Layers of GaNSMPS Inner2 Top Bottom Inner1

43 PCB Layout Guidelines The via set located in between the two egan FETs provides a reduced length high frequency loop inductance path leading to lower parasitic inductance. The via set located beneath the SR egan FET provides reduced resistance during the SR egan FET freewheeling period, reducing conduction losses. The interleaving of the via sets with current flowing in opposing direction allows for reduced eddy and proximity effects, reducing AC conduction losses.

44 Thermal Management The backside of the device is isolated. So heat sink can be mounted directly on the die RθJC 3.6 C/W RθJB 9.3 C/W RθJA 80 C/W Dual die under one heat sink and thermal pad

45 DPT test DPT is used for obtaining the switching characteristics of the Device under Test (DUT) at the desired voltage and current without thermal limitation. DPT is also used in the study to verify the impact of parasitic capacitances and inductances on the switching characteristics of the device. The Parasitics Considered are: Source inductance Ls Gate inductance Lg Drain inductance Ld Gate Resistance Rg Parasitics may lead to Excessive voltage overshoots across the gate-source Damping of the gate to source voltage Ringing in Vgs, Vds& Id The optimized values of the parasitics are Ls = 50 ph Lg = 0.5 nh Ld = 50 ph Rg = 1Ω

46 Power Circuit- GaN SMPS

47 Control Circuit GaN SMPS

48 Performance Evaluations Oscilloscope details HDO6104 (Teledyne Lecroy make), 1 GHz, 2.5 GS/s, 4 Channels, 12-bit HD Digital Oscilloscope Probe details ZD1000 (Teledyne Lecroymake), 1000 MHz Differential Probe PP018 (Teledyne Lecroymake), 500 MHz Passive Probe ADP 305 (Teledyne Lecroy make), 1kV, 100 MHz High-Voltage Differential Probe CP031 (Teledyne Lecroymake), 30A, 100 MHz Current Probe Regulated DC Power Supply LQ6324T (Aplabmake) TEST SETUP

49 Performance Evaluations 250kHz Time Scale : 200ns/div ChC1: V GS of Top Switch (2V/div) ChC2: V GS of Bottom Switch Time Scale : 200ns/div ChC1: V DS of Bottom Switch (8V/div) ChC2: V GS of Bottom Switch (5V/div)

50 Performance Evaluations 250kHz Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC2: V DS of Bottom Switch (10.0 V/div) ChC3: Inductor Current (500 ma/div) Inductor Current Ripple : 339 ma Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC3: Inductor Current (500 ma/div) ChC4: V DS of Top Switch (10.0 V/div) Inductor Current Ripple : 342 ma

51 Performance Evaluations 250kHz Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC2: V DS of Bottom Switch (10.0 V/div) ChC3: Output Current (500 ma/div) Average Output Current : 1.576A

52 Performance Evaluations 500kHz Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC2: V DS of Bottom Switch (10.0 V/div) ChC3: Inductor Current (500 ma/div) Inductor Current Ripple : 203 ma Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC3: Inductor Current (500 ma/div) ChC4: V DS of Top Switch (10.0 V/div) Inductor Current Ripple : 232 ma

53 Quantitative performance Sl# Input Output Efficiency Voltage V Current A Power W Voltage V Current A Power W % Initial level

54 Performance Evaluations 500kHz Time Scale : 1 μs/div ChC1: Output Voltage Vo (2.0 V/div) ChC2: V DS of Bottom Switch (10.0 V/div) ChC3: Output Current (500 ma/div) Average Output Current : 1.566A

55 Photographs Design1 TOP SIDE BOTTOM SIDE Design2

56 Details of Demonstration Components of SMPC Double pulse Test Board Synchronous Buck DC-DC Converter board

57 Acknowledgements NaMPET-II an initiative of DeitY Project title Investigations on Gallium Nitride (GaN) devices for Power Electronic switching applications and Design and Development of a high frequency GaN converter Joint development by CDAC Trivandrum & IISc ( Dept of EE, CeNSE, DESE) Bangalore

58 Demonstration of DC-DC Converter Thank You

59

60 Thank You

61 Introduction to GaN Devices Comparison of Semiconductor Material Characteristics Operates stably at Higher Voltage Operates stably at Higher temperature of 500deg C Operates stably at High frequency of 100GHz No harm to Human body( no hazardous materials ) NIT-Japan

62 PCB Fabrication agencies ACME CIRCUITS HIQ PRECISION MICROPAK PC PROCESS SHOGINI SUNNY CIRCUITS TECHNOLOGY PCBPOWER FINE LINE CIRCUITS LTD GENUS ELECTROTECH LTD ASCENMT CIRCUITS PVT LTD EPITOME COMPONENTS SULAKSHANA CIRCUITS LTD AT&S PRISM CIRCUITRONICS Purchase Requisition date : Purchae Order date : 12/08/2015

63 . Gate pull down resistance and impedance Condition to avoid Miller turn on Time constant of the circuit is, Should be limited Where, Z pull-down includes Gate resistance, R g Pull down resistance, R sink Loop Inductance

64 Gate pull up resistance Q GD is much lower compared to Si MOSFETs eg: 40V 10A, Si MOSFET(IRF7470TRPBF), Q GD = 44nC, GaN HEMT(EPC2014C), Q GD = 2.5nC) Fast turn on compared to Si MOSFETs High dv/dtcan create shoot-through during the hard switching transition Gate drive pull up resistor minimize transition time Adjust the switch node voltage overshoot and ringing Better EMI Should not induce unwanted losses Anti parallel diode is not used because of low threshold voltage

65 Gate drive dead time No reverse recovery losses Higher body diode forward voltage drop Diode conduction losses are significant at low voltage and high frequency Dead band control reduce diode conduction interval

66 Gate Drive Supply Regulation Discrete egan FET gate-driver solution with high-side and low-side supply voltage matching LM5113: Half-Bridge Gate Driver Optimized for egan FETs

67 Effect of Common source inductance Equivalent partial power circuit showing the di/dt effect of hard turn-on hard turn-on of complementary device showing effect of CSI ringing. Opposes gate drive voltage during di/dt Increase turn on and turn off times Reduces efficiency CSI, C GS, R sink forms an LCR resonant tank Ringing in the gate voltage

68 Electroless Nickel Immersion Gold Advantages: Flat Surface No Pb Good for PTH (Plated Through Holes) Long Shelf Life Disadvantages: Expensive Not Re-workable Black Pad / Black Nickel Damage from ET Signal Loss (RF) Complicated Process