Recommended External Circuitry for Transphorm GaN FETs. Zan Huang Jason Cuadra

Transcription

1 Recommended External Circuitry for Transphorm GaN FETs Zan Huang Jason Cuadra Application Note Rev. 1.0 November 22, 2016

2 Table of Contents 1 Introduction 3 2 Sustained oscillation 3 3 Solutions to suppress the sustained oscillation 5 4 Verifying the solution 9 5 Conclusion 10 2

3 1 Introduction Transphorm gallium nitride (GaN) FETs provide significant advantages over silicon (Si) superjunction MOSFETs, offering lower gate charge, faster switching speeds, and smaller reverse recovery charge. GaN FETs exhibit in-circuit switching speeds in excess of 150V/ns, compared to current silicon technology at less than 50V/ns. The fast switching of GaN devices reduces current-voltage cross-over losses and enables high frequency operation while simultaneously achieving high efficiency. However, the accompanying high di/dt during switching, combined with parasitic inductances, generates noise voltages in the circuit. This noise can interfere with the VGS of the device, and in the worst case, creates sustained oscillation which must be prevented for safe operation of the circuit. In this application note, we suggest adding a drain and a gate ferrite bead to prevent the oscillation. Known good values of ferrite beads are provided for each of our devices in a hard-switching half-bridge circuit, which is the most prone to sustained oscillation. 2 Sustained oscillation In a half-bridge circuit with high speed devices on both the high and low side, there are three steps to yield the sustained oscillation on the high side during low-side device turn-on, and vice versa. STEP 1: VGS CHANGE DUE TO HIGH DV /DT Consider the turn-on event of the low-side device (Q2) in Figure 1. The half-bridge output node falls from VDC to 0, at some rate of dvds/dt. The voltage across the high-side device Q1 rises from 0 to VDC at the same rate. The high-side device (Q1) gate capacitance Cgs is charged through Cgd and the fast-rising dv/dt. This voltage increases VGS of the high-side device, reducing off-voltage margin (VGS gets closer to VTH). Figure 1. Low-side device turn-on transient 3

4 STEP 2: VGS CHANGE DUE TO HIGH DI/DT When the low-side GaN FET (Q2) turns on, the high-side GaN FET drain current decreases at some rate of negative di/dt. This high negative di/dt multiplied by stray inductance Ls in the PCB layout produces a voltage VLS which also reduces the off-voltage margin of the FET (Figure 2). Lpcb Ld Coss Rg Vgs Vg_off Lrtn Cb il Ls + VLs Lf Ld Coss Ls Lpcb Figure 2. High di/dt an large Ls cause the FET have less off bias voltage margin The equation of first and second steps can be described by the below equation: VGS_FET = Vg_off + F * VDS - VLs = Vg_off + F * VDS + (-Ls *di/dt) Where F is the feedback factor of VDS to VGS. STEP 3: OSCILLATIONS DUE TO LARGE VOLTAGE RINGING Transphorm GaN devices are designed with a low ratio of Cgd to Cgs, minimizing the Miller effect. The oscillation usually cannot be sustained unless VGS is pulled close to the threshold voltage VTH. However, if VTH is reached, the device will operate in the linear region with transconductance gm: ID = (VGS - VTH) * gm The large gain in the feedback loop that includes external stray capacitance Cgd_ext (Figure 3), coupled with the nearly 180 degree phase shift of VGS and VDS, can cause a sustained oscillation. 4

5 Figure 3. Circuit feedback loop that includes Cgd_ext 3 Solutions to suppress the sustained oscillation To avoid sustained oscillation, it is important to guarantee that the gate stays off when the complementary device is turning on, and/or any potential oscillation is de-q d (the Q of any resonant tank is kept overdamped). This can be achieved with three required steps and a combination of three options: REQUIRED: OPTIMIZE PCB LAYOUT to minimize Cgd_ext, which strongly affects parasitic turn-on due to dv/dt. NOTE: This is required even for single-ended non-half-bridge designs. REQUIRED: USE A FERRITE BEAD IN THE GATE. A table of recommended ferrite beads is provided in Table 1. Recommended BOM for Transphorm devices in hard-switching bridge setup. This bead must be mounted very close to the gate lead of the device. NOTE: This is required even for single-ended nonhalf-bridge designs. HIGHLY RECOMMENDED: ADD A DRAIN FERRITE BEAD (Figure 4 and Figure 5). A drain ferrite bead de-q s the resonant tank formed by the Coss of the devices and the inductance in the power loop (drain, source, and bypass capacitor PCB trace inductance), by acting like a series damping resistance at the tank resonant frequency. Typical resonant frequency for the tank ranges from 50MHz to 200MHz because parasitic inductance varies according to PCB layout. The ferrite bead impedance at 100MHz is the important specification. NOTE: This is recommended even for single-ended non-half-bridge designs. 5

6 Figure 4. Inserting a drain ferrite bead in each or TO-247 device in a half-bridge Either a through hole ferrite bead slipped onto the drain lead or an SMD ferrite bead can be used. Part numbers for both types are shown in Table 1Table 1. Recommended BOM for Transphorm devices in hardswitching bridge setup. Figure 5. Inserting a drain ferrite bead in each SMD device The recommended part numbers are SMD beads. Note in the case of SMD FETs, the drain bead in the high-side device is placed in the source so the large Drain tab, where the heat comes out, is connected to an uninterrupted PCB copper pour for good heat dissipation. (The low-side device is a source tab for low EMI). Note also that the high-side gate drive is returned directly to the source pin. 6

7 The ferrite bead part numbers in Table 1 have been extensively tested and are verified to prevent oscillation without excessive voltage overshoot, up to each device s full rated current. Note that Tranpshorm devices have a repetitive peak drain voltage rating VTDS which is 150V greater than the maximum continuous drain voltage (for more, see the Drain Voltage and Avalanche Ratings application) note.) The test circuit is a half-bridge setup driven by a Si Labs SI8273 high speed, high- and low-side driver. Table 1. Recommended BOM for Transphorm devices in hard-switching bridge setup Device(s) Package TPH3202Px TPH3202Lx TPH3206Px TPH3206Lx TPH3208PS Gate Ferrite Bead (Ω) 60Ω (MMZ1608Y600B) 120Ω (MMZ1608Q121BTA00) 220Ω (MPZ1608S221ATA00) 330Ω (MPZ1608S331ATA00) Drain Ferrite Bead (Ω) Not required (Wurth) MPZ2012S300ATD25 6A (TDK) BLM21SN300SN1D 8.5A (Murata) BLM31PG330SH1L 6A (Murata) (Wurth) (Fair Rite) 330Ω (MPZ1608S331ATA00) MPZ2012S300ATD25 6A (TDK) BLM21SN300SN1D 8.5A (Murata) BLM31PG330SH1L 6A (Murata) TPH3208Lx TPH3212PS 180Ω (MMZ1608S181ATA00) (Wurth) (Fair Rite) TPH3205WS1 TO-247 Includes internal FB External FB (40-60Ω) optional (Wurth) MPZ2012S300ATD25 6A (TDK) BLM21SN300SN1D 8.5A (Murata) BLM31PG330SH1L 6A (Murata) TPH3207WS1 TO-247 Includes internal FB External FB (40-60Ω) optional MPZ2012S300ATD25 6A (TDK) BLM21SN300SN1D 8.5A (Murata) BLM31PG330SH1L 6A (Murata) Notes: 1. The recommended drain bead value is 4mΩ DCR, FB; if SMD bead RMS current is exceeded and more current capability is needed, use 2 or 3 pieces 8.5A FB in parallel 7

8 OPTION 1: ADD NEGATIVE VG_OFF VOLTAGE Vg_off = -2V to -5V. A simple AC-coupled negative gate drive circuit is shown in Figure 6. driver Figure 6. Negative gate drive circuit As in Figure 6, assume the supply voltage of the driver IC is 12V. The 7.5V zener (D1) clamps the on gate voltage to 7.5V + 0.7V = 8.2V (which is enough to ensure full enhancement of the gate) and charges C1 to about -3.8V (12V - 8.2V). The minimum off state negative gate drive voltage will be -3.8V. A 4.7V Zener (D2) is used instead of a 1N4148 diode because any leading-edge spike or overshoot (ringing) on the turn-on edge of the gate drive would cause the voltage on C1 to creep up at every turn-on edge, causing the on-voltage drive to drop well below 8.2V. The 4.7V Zener clamps the negative drive (and thus the capacitor voltage) to a maximum of 4.7V + 0.7V = 5.4V. This is also sets the maximum voltage on C1, by discharging it slightly at the turn-off edge if 5.4V is exceeded. 12V - 5.4V = 6.6V sets the minimum on voltage. Note that the sum of the two Zener voltages plus 0.7V, i.e., 4.7V + 7.5V + 0.7V = 12.9V in this example, must be greater than the supply voltage (12V) or else the capacitor will be charged or discharged heavily at every switching cycle. A combination of an 8.2V and 4.3V Zener will also work. For a 15V supply use 11V and 4.7V. Note: DO NOT attempt to use a reverse diode for gate turn off. This reduces the gate off-voltage margin. R1 driver D1 Figure 7. DO NOT use diode in path of gate drive circuit it raises the off gate voltage, reducing margin against parasitic turn-on TL072 X1 8 IRF530 Q1

9 OPTION 2: REDUCE THE TURN-ON DV/DT to avoid parasitic turn-on by lowering the gate drive voltage (but stay 8V), or choose a driver with reduced turn-on current drive i.e., higher turn-on drive impedance. OPTION 3: ADD AND RC SNUBBER TO DAMP THE RINGING ENERGY The drain ferrite bead is very effective in preventing the oscillation without affecting circuit efficiency. However, it does create some VDS voltage overshoot and thus in some cases is not a preferred solution. Under such circumstances, an external RC snubber for each device can be used to damp the ringing energy and prevent the sustained oscillation (Table 2). Note: the gate ferrite bead is always required either using a drain FB or RC snubber. Table 2. Recommended BOM for Transphorm devices when using an external RC snubber instead of a drain ferrite bead Device(s) Package TPH3202Px TPH3202Lx TPH3206Px TPH3206Lx TPH3208PS TPH3208Lx TPH3212PS Gate Ferrite Bead (Ω) RC Snubber Network 60Ω (MMZ1608Y600B) None 120Ω (MMZ1608Q121BTA00) 220Ω (MPZ1608S221ATA00) 330Ω (MPZ1608S331ATA00) None 330Ω (MPZ1608S331ATA00) 47pF + 7.5Ω 180Ω (MMZ1608S181ATA00) 47pF + 7.5Ω TPH3205WS2 TO-247 Includes internal FB External FB (40-60Ω) optional 47pF/100pF + 7.5Ω TPH3207WS2 TO-247 Includes internal FB External FB (40-60Ω) optional 100pF + 10Ω Notes: 2. 47pF RC snubber allows switching to 36A; for extra margin with a less-than-ideal layout, use a 100pF capacitor; the switching loss difference is very small 4 Verifying the solution In order to verify margin against oscillation, examine the VDS waveform at the turn-on and turn-off switching edges at the maximum drain current of the application. This may occur at start-up or at maximum load step. Alternatively, a double-pulse or multi-pulse test can be performed in the actual layout, up to >120% of the expected peak current of the application. See Figure 8 for an example. Verify that the ringing on the VDS waveform at the edges are damped. 9

10 Choke current Half-bridge output voltage (low-side VDS) ZOOM of above Choke current Half-bridge output voltage (low-side VDS) ZOOM of above Figure 8. Switching waveforms showing underdamped (without drain bead) and damped (with drain bead) VDS; test was performed with a multi-pulse test fixture 5 Conclusion Sustained oscillation can occur in switching applications using Transphorm high speed GaN devices which must be prevented for safe operation. By inserting a gate ferrite bead, a drain ferrite bead, and/or an RC snubber with recommended values, Transphorm GaN FETs can operate in a hard-switching bridge up to their full-rated current even with a less-than-ideal PCB layout. 10