I/O M odels for the MAX3882

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1 MAX3882 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim s High Frequency/Fiber Communication ICs utilize input and output (I/O) circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS) formats to transfer data into and out of an IC. These models are based on simplified circuit expressions that may include replacement of active circuit elements with ideal controlled voltage and current sources. As such, simulation with macromodels should be treated as typical performance and not relied upon as final proof-ofdesign. Use of macromodel descriptions is not a substitute for worst-case design analysis, nor for testing real circuits over temperature, supply, and other operating limits. The output format is provided as ASCII text netlists suitable for generic SPICE. This format is compatible with most versions of SPICE such as PSPICE and HSPICE. Additional information is found in HFAN 6.1 Input/Output Models for Maxim Fiber Components. To extract the circuit netlists using the Adobe Acrobat Reader follow these instructions. Select the "Text Select Tool" by clicking the left mouse button on this icon of the menu bar (a capital T with a small dashed box to the lower right). Highlight the desired netlist text with the cursor. Use the copy command from the edit menu to capture the selected lines. Then paste the selected lines into a text file editor and save the file with an extension compatible with the simulator. Revision A1, July 29, 2004

2 VCC I/O M odels for the MAX3882 OUTDRV R1 C1 R2 R3 Q5 Q6 VIN+ Q1 Q2 I1 R5 R6 C3 C4 OUT+ R7 C2 Q3 Q4 Q7 Q8 R2 VIN- OUT- I2 I3 I4 PAD and ESD STRUCTU RES Output Buffer Circuit MAX3882 Figure 1. Output m odel for signals PD0 to PD3 of the MAX3882. INDRV VCC R1 RL1 CL1 VIN+ IN+ Q1 I1 R2 RL2 CL2 IN- Q2 VIN- PAD and ESD STRUCTURES I2 Input Buffer for Circuit MAX3882 Figure 2. Input m odel for signals SDI and SLBI of the MAX3882.

3 Notes: The schematics on the previous page represent the output and input stage of the Maxim MAX Gbps/2.67Gbps 1:4 Demultiplexer. The output circuit shown is for the signal outputs (PD0+ to PD3+, PD0- to PD3-) and the input circuit is shown with the signal inputs (SDI+, SBLI+, SDI-, SLBI-)). However the models are given in generic SPICE, which only accepts node names as numbers. As discussed in the application note the output signals are described as (2001, 2002) and the input signals are described as (2101, 2102). These models are only valid at 25C. The bias currents for the input and output circuitry are modeled by ideal current sources. This model is not compensated for variations in VCC, so VCC equal to 3.3V should be used. ESD and PAD structures are modeled. The Output Stage: The output stage of the MAX3882 is shown as the sub-circuit OUTDRV. The OUTDRV Sub-circuit: The driver sub-circuit is a simplified version of the output stage used by the MAX3882 Demultiplexer. The output waveform is configured to be at a differential voltage of 325mV peak to peak. The offset output voltage has been set to 1.2V. The output waveform can have a frequency of 311Mhz or 333.3Mhz. You can change the frequency by changing the settings in the output netlist. The netlist is given in SPICE 2G6 format in Appendix A. The Input Stage: The input stage of the MAX3882 for the signals SDI and SLBI are shown as the sub-circuit INDRV. The INDRV Sub-circuit: The input structure of the MAX3882 is connected to an emitter follower configuration. The single ended input voltage is currently set to 2.9V. The differential input voltage is set to 400mV. The driving voltage source should be set to 0V differential at t=0. This ensures that the two AC coupling capacitors are not charged to different voltages initially (this is the way the circuit operates in steady-state operation). This was achieved by using a piecewise linear source as the driver. See Appendix B for the input netlist. Text File Format: This model is shipped in pdf format. Models and netlists can be copied to text format in the Acrobat Reader by holding the left mouse button on the Text Select Tool. Then the user can select what netlist and/or subcircuit with the mouse. Then use the copy command from the edit menu to capture the selected lines. These lines can then be pasted into the user s text file.

4 Appendix A: Output Netlist * 3882 Output Model.OPT ACCT NOMOD LIMPTS=10000.TEMP 25.OP.TRAN 2P 10n * Voltage Source VCC * Load Resistance R XOUTDRV OUTDRV.SUBCKT OUTDRV * For 622bps (311MHz): * VINP 1 0 PULSE ( m 2000m 0.04n 0.075n 0.075n 1.52n n) * VINN 3 0 PULSE (2000m m 0.04n 0.075n 0.075n 1.52n n) * For 667bps (333.5MHz) VINP 1 0 PULSE ( m 2000m 0.04n 0.075n 0.075n 1.42n n) VINN 3 0 PULSE (2000m m 0.04n 0.075n 0.075n 1.42n n) R R C p C p R R R R R R C f C f XQ N102M024

5 XQ N102M024 XQ N102M024 XQ N102M024 XQ N102M024 XQ N102M024 XQ N402V052 XQ N402V052 XQ N402V052 XQ N402V052 XQ N402V052 XQ N402V052 I mA I uA I uA I mA XD DE0172 XD DE0172 XD DE0172 XD DE0172 XP PADESD100 XP PADESD100.ENDS OUTDRV.SUBCKT N102M CP1SUB F RP1SUB K CTRENCH F RFIELDEPI K RREVERT G CBL F RSUB K CWAFER F CP1EPI F CP1P F RBX TC=2.271M RCX TC=2.717M, N RCI TC=2.717M, N REX QN TX.MODEL TX NPN( IS=2.558E-018 XTI=3 EG=1.120 BF=380 BR=12 XTB=0 VAF=66

6 + VAR=2.500 NF=1.018 NR=1.020 NE=2 NC=1.560 IKF=5.628M IKR= U + ISE=1.279E-018 ISC=0 RB= RBM= IRB= U CJE=6.016F + MJE=463M VJE=1.100 FC=990M CJC=3.276F MJC=350M VJC=1 TF=1.320P TR=5N + XTF=2 VTF=1.200 ITF=20.787M PTF=5 KF= N AF=2.150 ).ENDS N102M024.SUBCKT N402V CP1SUB F RP1SUB K CTRENCH F RFIELDEPI RREVERT G CBL F RSUB K CWAFER F CP1EPI F CP1P F RBX TC=1.853M RCX TC=2.518M,1.196U RCI TC=2.518M,1.196U REX QN TX.MODEL TX NPN( IS=2.188E-017 XTI=3 EG=1.120 BF=380 BR=12 XTB=0 VAF=66 + VAR=2.500 NF=1.018 NR=1.020 NE=2 NC=1.560 IKF=48.140M IKR=1.368M + ISE=1.094E-017 ISC=4.923E-030 RB=5.396 RBM=4.047 IRB=4.923M + CJE=51.239F MJE=463M VJE=1.100 FC=990M CJC=25.334F MJC=350M VJC=1 + TF=1.320P TR=5N XTF=2 VTF=1.200 ITF= M PTF=5 KF=47.251N + AF=2.150 ).ENDS N402V052.SUBCKT DE CTRENCH F RFIELDEPI RREVERT G CBL F RSUB K CWAFER F CP1EPI F DD 1 4 DCB RS TC=4.361M,4.344U.MODEL DCB D( IS=1.514E-018 N=1.050 CJO=41.280F VJ=800M M=500M ).ENDS DE0172

7 .SUBCKT PADESD XP1 2 5 PAD4SQ3P7 XQ DE0900 XQ DE0900.ENDS PADESD100.SUBCKT DE CTRENCH F RFIELDEPI RREVERT G CBL F RSUB K CWAFER F CP1EPI F DD 1 4 DCB RS TC=4.277M,4.217U.MODEL DCB D( IS=7.920E-018 N=1.050 CJO=216F VJ=800M M=500M ).ENDS DE0900.SUBCKT PAD4SQ3P7 1 3 CPAD F REPI TC=4.800M,5U CTRENCH F CBL P RX G RS K CWAFER F.ENDS PAD4SQ3P7.PROBE.END

8 Appendix B: Input Netlist * 3880 Input Model.OPT ACCT NOMOD LIMPTS=10000.TEMP 25.OP.TRAN 2P 2n VCC * Add input source here. * The source should connect to node 2101 (VINP) * and 2102 (VINN). * For 2.488Gbps (1.244GHz) * VINP 50 0 PULSE ( n 70p 70p 340p 803.9p) * VINN 60 0 PULSE ( n 70p 70p 340p 803.9p) * For 2.67Gbps (1.338GHz) VINP 50 0 PULSE ( n 70p 70p 300p 747.4p) VINN 60 0 PULSE ( n 70p 70p 300p 747.4p) RL RL CL p CL p XINPKG INPKG XINDRV INDRV.SUBCKT INDRV R R XQ h11m02 XQ h11m02 I mA I mA

9 XP PADESD100 XP PADESD100.ENDS INDRV ***********************************************.SUBCKT INPKG RP M RP M LP N LP N CP F CP F CP F.ENDS INPKG.SUBCKT H11M CP1EPI E-016 CP1P F CTRENCH F RBX TC=2.588M RCX TC=3.250M,2.039U RCI TC=3.250M,2.039U REX TC=44.406U RSUB K QP TXP OFF QN TX.MODEL TX NPN( IS=1.920E-018 XTI=3 EG=1.140 BF=265 BR=20 XTB=450M VAF=29 + VAR=3.500 NF=1.010 NR=1.020 NE=1.650 NC=1.560 IKF=6.878M IKR=126U + ISE=9.083E-022 ISC=1.168E-030 RB= RBM= IRB=1.168M + CJE=6.452F MJE=490M VJE=940M FC=990M CJC=1.729F MJC=470M VJC=850M + TF=3.651P TR=19N XTF=1 VTF=1K ITF=3.568M PTF=5 KF=1.500F AF=1 ).MODEL TXP PNP( IS=1.680E-019 CJE=1.729F MJE=470M VJE=850M CJC=3.870F + MJC=400M VJC=650M BF=10K BR= U TF=1N FC=900M ).ENDS H11M02.SUBCKT PADESD XP1 2 5 PAD4SQ3P7 XQ DE0900

10 XQ DE0900.ENDS PADESD100.SUBCKT DE CTRENCH F RFIELDEPI RREVERT G CBL F RSUB K CWAFER F CP1EPI F DD 1 4 DCB RS TC=4.277M,4.217U.MODEL DCB D( IS=7.920E-018 N=1.050 CJO=216F VJ=800M M=500M ).ENDS DE0900.SUBCKT PAD4SQ3P7 1 3 CPAD F REPI TC=4.800M,5U CTRENCH F CBL P RX G RS K CWAFER F.ENDS PAD4SQ3P7.PROBE.END

I/O Models for the MAX3880

I/O Models for the MAX3880 MAX3880 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim s High Frequency/Fiber Communication ICs utilize input and output (I/O) circuits