Simulation Guide. The notes in this document are intended to give guidance to those using the demonstration files provided for

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1 Simulation Guide The notes in this document are intended to give guidance to those using the demonstration files provided for Electronics: A Systems Approach 2nd Edition by Neil Storey. Demonstration files are provided in two formats:.sch files for use with the MicroSim Schematics package and.net netlist files for use with other simulation software. These notes assume the use of the MicroSim Schematics and PSpice simulation tools. For information on how to obtain a free evaluation copy of this simulation software see the Preface of the book. The files were generated using Evaluation Version 7.1 of PSpice but should work with later versions (although some of the configuration operations may be slightly different. The MicroSim tools are designed for use on PCs using the Windows, Windows95 or Windows NT operating systems, and the notes below assume the use of one of these operating systems. However, Mac users should be able to download the compressed demonstration files and to decompress them (for example using Stuffit) for use with other simulation packages. Installing the demonstration files: 1. Down load the compressed file Storey.zip The file can be obtained from the Addison-Wesley web site at: This site provides a search facility that allows you to locate information on a range of texts. Perform a search based on the title (or author) of the book and then follow the appropriate hyperlink to the web page associated with the book. Here you will find an entry under Supplements and samples which has a link to a location where you can download the compressed file. Download Storey.zip into a temporary file, it has a size of about 242 Kbytes. 2. Uncompress Storey.zip To uncompress the file you will need a program such as WinZip. If you do not have a copy of this program an evaluation version can be obtained, free of charge, on the internet at: If you have WInZip installed on your machine, then double clicking Storey.zip in Windows Explorer or File Manager should activate the decompression program automatically. When WinZip is run it will display a list of the files contained within the compressed file. Select Extract to decompress the files. The program will then ask for a destination directory. If you wish to install the demonstration files on only one machine then specify an appropriate directory name on a hard disk (e.g. C:\Storey). If you wish to distribute the demonstration files to a range of machines it may be more convenient to extract the files to a floppy disk (normally A: or B:). The files can then be copied from the floppy disk into a suitably named directory on each target machine. In any event you should make a note of the name of the directory used to store the demonstation files. When extraction of the files is complete the specified directory will contain:all the required demonstration files; two library files for use with the MicroSim Schematics package; README.doc Copyright Addison Wesley Longman Limited,

2 (this document in Word for Windows format); README.pdf (this document in Adobe Acrobat format) and README.txt (a text only version of this document for people without access to either Word for Windows or an Adobe Acrobat reader). When extraction is complete you may delete Storey.zip from the temporary directory if you wish. 3. Configuring MicroSim Schematics Before using MicroSim Schematics with the demonstration files you should install two custom library files Storey.lib and Storey.slb. To do this you will need to know the location of the directory used by the package to store its library files. The location of this directory can be found as follows: Run the Schematics package and from the Options menu select Editor Configuration. The directory containing the library files is displayed in a box labelled Library Path. Make a note of this directory and exit from Schematics. Use Windows Explorer or File Manager to copy the two files Storey.lib and Storey.slb from the directory containing the demonstration files to the directory used by Schematics to store its library files (as located above). Re-enter Schematics and select the Library and include files entry in the Analysis menu. In the File Name box enter Storey.lib and click the Add Library* button. Storey.lib* should now appear in the Library Files box. Click OK to close this window and then select Editor Configuration from the Options menu. Click the Library Settings button to bring up the Library Settings window. In the Library Name box enter Storey.slb and click Add*. Storey.slb should now appear in the list of library files. Click OK to close this window, and OK again to close the Editor Configuration window. The custom libraries are now configured and you can start working with the demonstration files now, or exit from Schematics and return later. 4. Loading the demonstration files To load a demonstration file from within Schematics click on the Open entry in the File menu. This will bring up the Open dialogue box which will allow you to specify the file you require from the directory where you stored the demonstration files. Using this document: You may wish to print out this document to that you can refer to it while you are working through the exercises. This document may be copied and distributed freely, provided that it is copied in its entirety without modification and that it is not used for commercial gain. In the early exercises, the various stages of editing the schematic, setting up the appropriate simulation and displaying the results (using Probe if appropriate) are described in some detail (although it is not the purpose of this document to teach the use of PSpice). In later exercises it is assumed that the reader will have gained a basic understanding of how to configure the package and less detailed information is given. In most cases when a demonstration file is loaded the settings of the various components and the required analysis will be already configured. If this is the case, then simply clicking on the Simulate icon (or selecting Simulate from the Analysis menu) will automatically generate the required simulation. However, when a simulation is performed the package saves the current settings of the various components and details of the required analysis. Therefore, if you experiment with settings or component values (as you will wish to do) you will loose the original values and settings. For this reason, the notes below give the settings of the various voltage sources and the parameters of the necessary analysis, so that these may be reproduced later if required. Since the Schematics package tends to overwrite the demonstration files as you experiment, you may wish to keep a backup copy of the demonstration files so that you can retrieve the original versions. This can be done by simply copying all the files to a backup directory. Copyright Addison Wesley Longman Limited,

3 FILE1: A resistor network This is a demonstration file for Computer Simulation Exercise 1.1. After loading the file into the Schematics editor, run the analysis by clicking the Simulate icon or by selecting Simulate from the Analysis menu. The voltage across R6 will be indicated by the 'Viewpoint'. FILE3A: Loading effects This is a demonstration file for Computer Simulation Exercises 3.1 and 3.2. Exercise 3.1 After loading the file into the Schematics editor, run the analysis. The voltage across the load resistor will be indicated by the 'Viewpoint'. Exercise 3.2 Load the demonstration file and then add a PARAM part using the parts browser, or by selecting 'Get New Part' from the 'Draw' menu. The PARAM part can be placed anywhere away from the components of the circuit. When placed it produces an underlined label "PARAMETERS". On the circuit diagram double click the text '50' that accompanies the load resistor. This will bring up a box that allows you to change the resistor value RL. Replace the value 50 with the string {RL_value} including the curly brackets and click 'OK'. Double click the PARAMETERS label with the left mouse button. This will bring up a configuration box for the PARAM part. Select NAME1 and enter the value RL_value (do not type curly brackets around this label). Click 'Save Attr'. Next select VALUE1, set its value to 50 and again click 'Set Attr'. Now click 'OK'. The parameter 'RL_value' will now appear on the circuit diagram below the PARAMETERS label. Bring up the 'Analysis Setup' box by clicking 'Setup' from the 'Analysis' menu. Click 'DC Sweep' and setup the necessary parameters, these are: 'Swept Var. Type' to 'Global Parameter'; 'Name' to 'RL_value' (again no curly brackets); 'Sweep Type' to 'Linear'; 'Start Value' to 1; 'End Value' to 100 and 'Increment' to 1. When you have entered these values click 'OK'. Make sure the 'Enabled' box is set against 'DC Sweep' and then click 'Close' to close the Analysis Setup box. You are now ready to run the analysis. Click the 'Simulate' icon (or select Simulate from the 'Analysis' menu). If probe is set to run automatically after simulation a probe window should now appear. (If not, run probe from the Analysis menu). Click 'Add' on the 'Trace' menu and type an expression for the output power in the 'Trace Expression' box and click 'OK'. A suitable expression is: V(Vo)* V(Vo)/ RL_value. This should result in a trace showing the variation of output power with RL, as the latter is swept from 1 to 100 ohms. Use the cursor controls to investigate this trace and determine the value of RL that corresponds to the maximum output power, and the value of this maximum value. Compare these values with those given in the text. Change Ro and repeat the exercise. FILE3B: A capacitively coupled network This is a demonstration file for Computer Simulation Exercises 3.3. Load the file into the Schematics editor and then change the values for C and R to your chosen values. Calculate (by hand) the value of the expected break frequency. Bring up the 'Analysis Setup' box by clicking on 'Setup' from the 'Analysis' menu. Click on 'AC Sweep' and select a Decade sweep with 101 Pts/Decade. Then enter Start and End Frequencies that are a couple of decades either side of your expected break frequency. Click 'OK' to close the AC Sweep setup box, check that the 'Enabled' box next to 'AC Sweep' is selected and click 'Close' to close the 'Analysis Setup' box. You are now ready to run the analysis. Click the 'Simulate' icon or select 'Simulate' from the 'Analysis' menu. If Probe is set to run automatically a Probe window should now appear. If not, you may run Probe from the Analysis menu. Copyright Addison Wesley Longman Limited,

4 In Probe click on Trace, and then Add and enter an appropriate expression in the 'Trace Expression' box, then click 'OK'. To see the variation of the output voltage with frequency you could simply display the output voltage V(Vo). However, probably more useful is to display the gain in dbs. To do this enter DB(V(Vo)/V(Vi)) in the 'Trace Expression' box. From the resultant curve you may measure the cut-off frequency (using the cursor) which is the point where the gain has dropped by 3 db. You can also confirm that the rate of fall of gain is as you expect. For the next part of the exercise close the Probe window and edit the circuit to add a source resistor. Calculate the effect of this modification on the circuit and repeat the simulation (changing the frequency range if appropriate). Compare your results with those predicated by your analysis. FILE3C: The effects of stray capacitance This is a demonstration file for Computer Simulation Exercise 3.4. After loading the file into the Schematics editor, change the component values to your sample values and calculate (by hand) the expected cut-off frequency. Now set up the simulation as described above for FILE3B, and again compare your results with those predicted by your calculations. FILE4A: A feedback circuit This is a demonstration file for Computer Simulation Exercise 4.1. Load the file and select appropriate values for the forward and reverse gain blocks (the values can be changed by double clicking on the gain value on the circuit schematic). Run the simulation (by clicking the 'Simulate' icon or by selecting 'Simulate' from the analysis menu) and observe the output voltage displayed by the 'Viewpoint' on the schematic. Compare the simulated gain with that predicted by calculation. FILE4B: A differential amplifier (subtractor) This is a demonstration file for Example 4.6. Load the file and investigate the behaviour of the circuit with a range of input voltages (V1 and V2), and for different values of the resistors. A good initial setup would set V1 to produce a 1kHz signal with an amplitude of 5mV, and V2 to produce a 5kHz signal with an amplitude of 1mV. Then set the simulator to perform a transient analysis with a final time of 2ms and a step size of 20us (to setup the analysis click on 'Setup' on the 'Analysis' menu, then select 'Transient' and enter the appropriate values in the 'Print Step' and 'Final Timer' boxes). The circuit includes 'Markers' so probe will automatically display the input and output waveforms when the simulation is run. FILE4C: An inverting summing amplifier (adder) This is a demonstration file for Example 4.7. Load the file and investigate the behaviour of the circuit with a range of input voltages (V1 and V2), and for different values of the resistors. A good initial setup would set V1 to produce a 1kHz signal with an amplitude of 5mV, and V2 to produce a 5kHz signal with an amplitude of 1mV. Then set the simulator to perform a transient analysis with a final time of 2ms and a step size of 20us (to setup the analysis click on 'Setup' on the 'Analysis' menu, then select 'Transient' and enter the appropriate values in the 'Print Step' and 'Final Timer' boxes). The circuit includes 'Markers' so probe will automatically display the input and output waveforms when the simulation is run. FILE4D: A unity gain buffer amplifier This is a demonstration file for Example 4.8. Load the file and investigate the behaviour of the circuit with a range of input voltages (V1). A good initial setup would set V1 to produce a 1kHz signal with an amplitude of 5mV. Set the simulator to perform a transient analysis with a final time of 2ms and a step size of 20us (to setup the analysis click on 'Setup' on the 'Analysis' menu, then select 'Transient' and enter the appropriate values in the 'Print Step' and 'Final Timer' boxes). The circuit includes 'Markers' so probe will automatically display the input and output waveforms when the simulation is run. Copyright Addison Wesley Longman Limited,

5 FILE4E: A current to voltage converter This is a demonstration file for Example 4.9. Load the file and investigate the behaviour of the circuit for different values of the input current and the resistor R. A suitable initial setup might be to set the current generator to give a current of 5mA at 1kHz, and to setup the analysis to perform a transient analysis with a step size of 20us and final time of 2ms. Since the circuit has 'Markers' the input current and output voltage should be displayed automatically when the simulation is complete. Unfortunately, because of the difference in magnitude of these two quantities it will be necessary to add a second Plot and to display the input current on one graph and the output voltage on another. FILE4F: An integrator This is a demonstration file for Example Load the file and set up the voltage source to produce a 1V signal at 1kHz. You will notice that the circuit includes a resistor in series with the capacitor. This additional component is to reduce the DC gain of the circuit to prevent it from saturating as a result of any input offset or bias current. The presence of the resistor has little effect on the integrating properties of the circuit. The circuit may be used with a range of either analogue or digital waveforms. Since at this point in the text we have concentrated on analogue circuits the demonstration file uses a sinusoidal input voltage. Set up the analysis to perform a transient analysis (for the above values, a step size of 20ns and a final time of 2ms would be appropriate). Run the simulation and you will observe the affect of integrating a sinewave. Note the phase shift produced. Experiment with different component values and input signals. FILE4G: A differentiator This is a demonstration file for Example You will notice, upon loading the file, that a resistor (Rs) has been added in series with the capacitor. This resistor reduces the gain of the circuit at high frequencies and therefore reduces the amplification of high frequency noise and improves stability. When you have looked at the characteristics of this circuit you might care to remove this resistor and note the effect. As in the last circuit we are using a sinusoidal input and you should set up the voltage source to appropriate values. Suitable settings would be an amplitude of 1V and a frequency of 1kHz. Set up the analysis to perform a transient analysis (for the above values, a step size of 20ns and a final time of 2ms would be appropriate). Run the analysis and observe the results. Note the phase shift produced as a result of the differentiation. Look at the characteristics of this circuit for different component values. Note that for some combinations of components the circuit becomes unstable despite the presence of Rs. FILE4H: A non-inverting amplifier This is a demonstration file for Computer Simulation Exercise 4.2. Load the file and set the resistors to the value you have calculated to give a gain of 100 (note that the values in the demonstration file do NOT produce a gain of 100). Set up the voltage source to give an output with an amplitude of 1V and a frequency of 1kHz. Perform a transient analysis with an appropriate step size and final time. Confirm that the gain of the circuit is as you predicted. Repeat the above experiment with different ratios of resistor values and conform that the gain is as you expect. Try using ratios that should produce voltage gains that are comparable with the nominal gain of the 741. Also investigate the effect of keeping the ratio constant but using very large or very small resistor values. FILE4J: A non-inverting amplifier This is a demonstration file for Computer Simulation Exercise 4.3. Repeat the activities described for the last demonstration file for this inverting amplifier. Copyright Addison Wesley Longman Limited,

6 FILE4K: Gain versus frequency for an op-amp This is a demonstration file for Computer Simulation Exercise 4.4. This demonstration file contains the circuit of an inverting amplifier. Set up the voltage source to give an output of 100mV AC and setup an AC sweep from 10Hz to 10MHz in decades, with 101 points per decade. The component values in the demonstration file give a voltage gain of unity. Run the simulation with these components and use Probe to plot the frequency response of the circuit. A suitable 'Trace Expression' is DB(V(Vo)/V(Vi+)) - this is the gain in dbs. Use the cursor in Probe to measure the gain of the circuit and its cut-off frequency (where the gain falls by 3dB from its low frequency gain). Hence determine the circuits bandwidth and its gain-bandwidth product. Select values of R2 to give gains of 10, 100 and 1000 and plot the frequency responses as above. In each case calculate the bandwidth and the gain-bandwidth product and then compare your results with those predicted by Figure 4.8. FILE5A: Diode currents This is a demonstration file for Computer Simulation Exercise 5.1. The circuit consists of a general purpose diode (a 1N4002) in series with a variable voltage source. Setup the analysis to perform a 'DC Sweep' from 0 to 0.8V in 0.01V increments. Look at the behaviour of the device over different voltage ranges including both forward and reverse bias conditions. Estimate the reverse breakdown voltage of the device. FILE5B: A Zener diode circuit This is a demonstration file for Computer Simulation Exercise 5.2. After loading the circuit configure the analysis to perform a DC sweep 0 to 6V in 0.01V steps. When the simulation is run this will produce a graph that shows that negligible current flows in the reverse biased Zener diode until the applied voltage exceeds the breakdown voltage (4.7V in this case). Try modifying the circuit by varying the series resistor and investigate the effects of applying different voltage ranges (including negative voltages). Finally, investigate the effects of adding a load resistor across D1. A suitable value to start with might be 1k, but look at the effects of using smaller values. FILE5C: A half-wave rectifier This is a demonstration file for Computer Simulation Exercise 5.3. Load the file and configure the voltage source to produce a 5V AC output at 50 or 60 Hz. Set up the analysis to perform a transient analysis with a 'Print Step' of 200us and a 'Final Time' of 60ms. Run the analysis and observe the relationship between the applied voltage and that across the load. While in Probe add a second Plot to the display and plot the diode current I(D). This illustrates the relationship between the supply voltage and the supply current. You might like to investigate the effect of increasing or decreasing the applied voltage. Add a reservoir capacitor to your circuit. A suitable value might be 100uF. Again add a second plot and observe the supply current. Note that the addition of a reservoir capacitor tends to keep the output voltage more constant and that the supply current now takes the form of short bursts of current which recharge the capacitor. Use the cursor to measure the peak output voltage and the output ripple voltage (these values are used in Computer Simulation Exercise 5.4). Investigate the effects of varying the size of the reservoir capacitor and the load resistor. Note also the effect of varying the frequency of the voltage produced by the voltage source. FILE5D: A full-wave rectifier This is a demonstration file for Computer Simulation Exercise 5.4. Load the file and repeat the various tasks suggested for FILE5C above. Note that in this circuit we measure the supply voltage by making a differential measurement across the voltage source. This is necessary because of the positioning of the analogue ground on one terminal of the load resistor. Compare the peak and ripple voltages measured for this circuit with those obtained earlier for the half-wave circuit. Copyright Addison Wesley Longman Limited,

7 FILE5E: Signal clamping This is a demonstration file for Computer Simulation Exercise 5.5. The demonstration file contains a circuit equivalent to the first example given in Example 5.5. Set the voltage source to produce an output of 10V at a frequency of 50Hz or 60Hz and run the simulation. Set up a transient analysis with a 'Print Step' of 200us and a 'Final Time' of 40ms. Confirm that the waveforms produced are as you expect and then modify the circuit to look at the other circuit configurations. A suitable Zener diode is the D1N750. This has a breakdown voltage of 4.7V. FILE6A: An AC coupled DE MOSFET amplifier This is a demonstration file for Computer Simulation Exercise 6.1. Load the file and set up the voltage source to produce a 1kHz signal with an amplitude of 50mV. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and within Probe display two separate plots, one for the input voltage and one for the output voltage. Then use the cursor to measure the magnitude and phase of the voltage gain. Progressively increase the input voltage and look at the effects on the output waveform. FILE6B: An AC coupled JFET amplifier This is a demonstration file for Computer Simulation Exercise 6.2. Load the file and set up the voltage source to produce a 1kHz signal with an amplitude of 50mV. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and within Probe display two separate plots, one for the input voltage and one for the output voltage. Then use the cursor to measure the magnitude and phase of the voltage gain. Progressively increase the input voltage and look at the effects on the output waveform. FILE6C: A JFET differential amplifier This is a demonstration file for Computer Simulation Exercise 6.3. After loading the file set up the AC voltage source to produce a 1kHz signal of 50mV. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2 ms. Run the simulation and observe the output. Note that the two output waveforms are not perfectly symmetrical. This is because Rs does not represent a perfect constant current source. Experiment with different values for the input voltage and the DC voltage applied to the gate of J2. Also try connecting the same signal to both gates (replacing the constant voltage source VG with a resistor equal to RG). FILE6D: A FET constant current source This is a demonstration file for Computer Simulation Exercise 6.4. Running the simulation will result in the current through the load resistor being displayed by the IPROBE component. Increase RL from 100 to 200 ohms and repeat process. You will note that although the load resistance has been changed by 100% the current chances by only a fraction of a percent. Repeat this process using various values of RL up to 1k. You will note that the current changes by only a few percent for a factor of 10 increase in the resistance. The circuit therefore is acting as a constant current source. Now look at the effect of changing RL to 2k. Can you explain this effect? FILE6E: Precision voltage controlled current source This is a demonstration file for Computer Simulation Exercise 6.5. After loading the file, set up a DC sweep analysis with Vi as the swept variable, and with a sweep from 0 to 1V in 0.01V increments. When the simulation is performed this should result in a plot of the current in the load against the input voltage and you can inspect this to confirm that this relationship is as required. If you wish to study this circuit further you may disable the DC sweep and set particular voltages for Vi. You can then add Viewpoint and Iprobe components to the circuit to display the various voltages and currents. Copyright Addison Wesley Longman Limited,

8 FILE7A: A common-emitter amplifier This is a demonstration file for Computer Simulation Exercises 7.1, 7.2 and 7.3. NOTE: Before loading this demonstration file (or any of the following group of files) ensure that the custom libraries "storey.lib" and storey.slb have been loaded as described in the installation instructions at the beginning of this document. To check that this has been done go to the 'Analysis' menu and click the 'Library and Include Files' entry. This will bring up a window which, among other things, displays the current library files. The 'Library Files' box should contain "storey.lib" in addition to "nom.lib". Close this window and then open the Editor Configuration box from the Options menu and confirm that storey.slb is included in the list of libraries. If either of these library entries is missing then carry out the configuration instructions given at the beginning of this document. If you experience any difficulties in loading or simulating this file it is likely that these libraries have not been correctly configured. In this event you should reconfigure them as described earlier. Exercise 7.1 When you have ascertained that the custom library has been correctly installed load the demonstration file and run the simulation. This will display the quiescent base and collector voltages for the circuit. Experiment with different resistor values and make sure that you understand the circuit's operation. Exercise 7.2 Replace the link from C to ground with an AC voltages source (VSIN) and use transient analysis to determine the small signal voltage gain. Apply a sinusoidal signal of 10mV at 1kHz and perform a transient analysis with a 'Print Step' of 20 us and a 'Final Time' of 2ms. The small signal input and output resistances may then be found using the technique described in the text. Exercise 7.3 Use the technique described above to measure the quiescent output voltage and the small signal voltage gain of the circuit for transistors of different current gains. The custom library contains parts: NPN80, NPN100, NPN150, etc. where the numeric part of the name gives the current gain. FILE7B: Quiescent conditions of a bipolar feedback amplifier This is a demonstration file for Computer Simulation Exercise 7.4. Load the circuit and run the simulation. This will indicate the quiescent voltages on the base and collector of the transistor. Add Iprobe components to the circuit to look at the currents and investigate the effect of replacing the transistor with one of higher gain. FILE7C: AC characteristics of a bipolar feedback amplifier This is a demonstration file for Computer Simulation Exercise 7.5. Load the circuit and set up the voltage source to produce a 50mV output at 1kHz. Set up a transient analysis with a 'Print Step' of 2us and a 'Final Time' of 2ms. Run the simulation and use Probe to look at both the input and the output waveforms (you may find it easier to use two separate plots to achieve this). Measure the small signal voltage gain of this arrangement. Now measure the small signal input and output resistances of this circuit using the same approach as used for FILE7A (you will need an estimate of input resistance when you come to look at FILE7D). Replace the transistor with a higher gain type (e.g. an NPN300) and compare your results. FILE7D: The effects of coupling capacitors This is a demonstration file for Computer Simulation Exercise 7.6. Having measured the input resistance of the circuit of FILE7C, calculate the low-frequency cut-off produced by a 1uF coupling capacitor. Load the demonstration file and set the magnitude of the voltage source Vi to 50mV. Set up an AC sweep with 101 points per decade and upper and lower frequencies chosen to be about two Copyright Addison Wesley Longman Limited,

9 decades above and below your calculated value for the cut-off frequency. Run the simulation and in Probe display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi:+)). Measure the cut-off frequency using the cursor and compare this with your calculated value. FILE7E: A single-stage bipolar amplifier This is a demonstration file for Computer Simulation Exercise 7.7. Load the circuit and set up the input voltage source to be 1.25V at 1kHz. Set up a transient analysis with a 'Print Step' of 2us and a 'Final Time' of 2ms. Run the simulation and observe the Probe output. Measure the peak to peak output voltage and the voltage gain and compare these with the specification. Now replace the 'VSIN' voltage source used for Vi with a 'VSRC' component (also labelling this Vi). Set this to give a suitable amplitude (say 50mV) and then set up an AC sweep from 1 Hz to 10kHz in decades with 101 points per decade. Run the simulation and use Probe to display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi:+)). Measure the cut-off frequency using the cursor and compare this with the required and predicted values. FILE7F: Use of an emitter resistor This is a demonstration file for Computer Simulation Exercise 7.8. Load the file and configure the input voltage source (Vi) to give a 50mV AC signal. Next setup an AC sweep going from 10Hz to 1GHz in decades, with 101 points per decade. Run the analysis, and within Probe display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi:+)). You will note that the response obtained is not of the form shown in the text. Firstly, at low frequencies the gain is not constant as shown in Figure 7.22(c) but falls with decreasing frequency. The reason for this is that Figure 7.22(c) shows the response of a circuit without a coupling capacitor. Our circuit has a 2.2uF coupling capacitor, and we saw in the last exercise that this causes a reduction of gain at low frequencies. The second area where the response differs from that predicted in the text is at high frequencies. Here the gain appears to remain constant to frequencies above 1GHz. This is caused by the simple nature of the model used for the NPN150 transistor. The models used for the custom parts are rather simplistic in order to get a predictable current gain. In order to get a more realistic picture of the circuit's behaviour replace the NPN150 transistor with a Q2N2222 part and change the value of the coupling capacitor C from 2.2uF to 22uF. Now repeat the above analysis and compare the results with those given in the text. FILE7G: A two stage bipolar amplifier This is a demonstration file for Computer Simulation Exercise 7.9. Load the circuit and set up the voltage source to produce a 50mV output at 1kHz. Set up a transient analysis with a 'Print Step' of 2us and a 'Final Time' of 2ms. Run the simulation and use Probe to look at both the input and the output waveforms (you may find it easier to use two separate plots to achieve this). Measure the small signal voltage gain of the circuit and compare this with the values calculated in the text. The Viewpoints will indicate the quiescent voltages at various points in the circuit. Use these to look at the DC operation of the arrangement. You may also care to add one or more Iprobe components to look at quiescent currents. FILE7H: A push-pull output stage This is a demonstration file for Computer Simulation Exercise Load the file and set up the input current source to have a current offset (IOFF)of 1.5mA, a current amplitude (IAMPL) of 0.5mA and a frequency of 1kHz. Set up a transient analysis with a 'Print Step' of 2us and a 'Final Time' of 2ms. Run the simulation and observe the form of the output using Probe. You will observe that the output has a very noticeable amount of cross-over distortion. Display the FFT of this waveform (by clicking the FFT icon or by selecting 'Fourier' from the 'Trace' menu) and use the cursor to determine the frequency of the various components. You will note that while most of the signal power is in the fundamental (1kHz) there are also several other frequencies present. Note the frequencies of these components. Copyright Addison Wesley Longman Limited,

10 In order to perform the second part of Computer Simulation Exercise 7.10 you may modify this circuit or load FILE7J. If you decide to modify this circuit you should add two diodes as in Figure 7.38(b) of the text, and adjust the offset current of the current generator to return the quiescent output voltage to zero. You may find it helpful to add a Viewpoint to the output voltage. FILE7J: An improved push-pull output stage This is a demonstration file for Computer Simulation Exercise Having loaded the file repeat the activities described above for FILE7H but decrease the offset current of the current generator to 1.18mA to allow for the presence of the diodes. You should find that the output waveform now has considerably less distortion and that the FFT shows that most of the harmonic distortion has been removed. FILE7K: A phase splitter This is a demonstration file for Computer Simulation Exercise Having loaded the file set up the voltage source to produce a signal of 1V at 1kHz. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and use Probe to compare the two output signals. Note that the quiescent output voltages of the two outputs are not the same. Now add load resistors of 1k between each output and ground. Repeat the simulation and again compare the outputs. It is clear that the output resistances of the two outputs are not the same. FILE8A: A third order low-pass filter This is a demonstration file for Computer Simulation Exercise 8.1. After loading the file set the voltage source to an amplitude of 50mV. Edit the three resistors and the three capacitors to the values you have calculated to give a cut-off frequency of 1kHz for each stage. Set up an AC sweep from 10Hz to 100kHz in decades with 101 points per decade. Run the simulation and use Probe to display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi)). Compare the response with your predictions. FILE8B: A low-pass filter This is a demonstration file for Computer Simulation Exercise 8.2. After loading the file set the voltage source to an amplitude of 50mV. Set up an AC sweep from 10Hz to 10kHz in decades with 101 points per decade. Run the simulation and use probe to display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi)). Note the general form of the response and its cut-off frequency and rate of fall of gain. FILE8C: A high-pass filter This is a demonstration file for Computer Simulation Exercise 8.2. After loading the file set the voltage source to an amplitude of 50mV. Set up an AC sweep from 10Hz to 10kHz in decades with 101 points per decade. Run the simulation and use probe to display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi)). Note the general form of the response and its cut-off frequency and rate of fall of gain. FILE8D: A band-pass filter This is a demonstration file for Computer Simulation Exercise 8.2. After loading the file set the voltage source to an amplitude of 50mV. Set up an AC sweep from 10Hz to 100kHz in decades with 101 points per decade. Run the simulation and use probe to display the voltage gain in dbs. A suitable 'Trace Expression' would be DB(V(Vo)/V(Vi)). Note the general form of the response and its cut-off frequency and rate of fall of gain. Copyright Addison Wesley Longman Limited,

11 FILE8E: A class A amplifier This is a demonstration file for Figure After loading the file set the voltage source to produce a 1kHz sinewave with an amplitude of 1V. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and use Probe to display the input voltage and the collector current (on separate plots). Note that the transistor conducts throughout the complete cycle of the input waveform. FILE8F: A class B amplifier This is a demonstration file for Figure After loading the file set the voltage source to give an offset voltage of 14.3V (to provide the correct bias to the two diodes), a voltage amplitude of 5V and a frequency of 1kHz. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and use Probe to display the two collector currents. Note that each transistor conducts for approximately half of each cycle of the input waveform. You will notice that the collector resistor has not been included in the demonstration circuit. This resistor serves no function other than to reduce the power consumption in the transistors and so is omitted. FILE8G: A class AB amplifier This is a demonstration file for Figure This file can be used in exactly the same way as FILE8F, except that the offset voltage of the voltage source should be reduced to about 14.0V because of the additional diode. You will notice that the current does not follow the idealised waveform given in the text. Because the voltage between the two bases is greater than that needed to turn the two transistors on, both devices conduct continuously. FILE8H: A class C amplifier This is a demonstration file for Figure Load the file and set up the voltage source to produce a 0.8V sinewave with a frequency of 1kHz. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and use Probe to display the collector current. You will see that the device conducts for less than half of the input cycle. FILE8J: A simple push-pull arrangement This is a demonstration file for Figure Load the file and set up the voltage source to give a sinewave of 5V amplitude and a frequency of 1kHz. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and observe the form of the output using Probe. You will observe that the output has a considerable amount of cross-over distortion. You can display the FFT of this waveform by clicking the FFT icon or by selecting 'Fourier' from the 'Trace' menu. FILE8K: An improved push-pull arrangement This is a demonstration file for Figure Load the file and set up the voltage source to give a sinewave of 5V amplitude and a frequency of 1kHz. Set up a transient analysis with a 'Print Step' of 20us and a 'Final Time' of 2ms. Run the simulation and observe the form of the output using Probe. You will observe that the output has considerably less cross-over distortion than the circuit of FILE8J. Again, you can display the FFT of this waveform by clicking the FFT icon or by selecting 'Fourier' from the 'Trace' menu. FILE9A: A logic circuit This is a demonstration file for Computer Simulation Exercise 9.1. The circuit uses a rather unusual method of displaying the output that allows the user to see directly the output produced by a particular input combination. Load the file and run the simulation to see the output corresponding to the set input. Then modify the inputs and confirm that the outputs are as you expect. You may use this approach to look at other logic functions if you wish. Copyright Addison Wesley Longman Limited,

12 FILE9B: Equivalence of logic circuits This is a demonstration file for Computer Simulation Exercise 9.2. The circuit contains the two implementations of the logic function fed from the same input terminals. If the two implementations are indeed equivalent then the two outputs (D1 and D2) should be the same for all combinations of the inputs A, B and C. Experiment with the circuit and see if this is the case. FILE10A: An S-R latch This is a demonstration file for Figure The input 'STIM1' components connected to R and S have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 15us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. Edit the voltage input waveforms and confirm that you understand the functioning of this circuit. FILE10B: A gated S-R latch This is a demonstration file for Figure The input 'STIM1' components connected to S, R and Enable have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 15us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. You will see that although the text assumes that the Q output of the latch is initially at 0, the simulation shows that the output is actually undefined until the enable output becomes active and either S or R is activated. FILE10C: A gated D latch This is a demonstration file for Figure The input 'STIM1' components connected to D and Enable have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 13us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. You will see that although the text assumes that the Q output of the latch is initially at 0, the simulation shows that the output is actually undefined until the enable output becomes active. FILE10D: A negative edge-triggered J-K flip-flop This is a demonstration file for Figure The input 'STIM1' components connected to J, K and CLK have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 15us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. You will see that although the text assumes that the Q output of the latch is initially at 0, the simulation shows that the output is actually undefined until the first active clock transition. FILE10E: A J-K flip-flop with active low PRESET and CLEAR This is a demonstration file for Figure The input 'STIM1' components connected to J, K and CLK have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 16us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. You will see that although the text assumes that the Q output of the latch is initially at 0, the simulation shows that the output is actually undefined until the first active clock transition. FILE10F: A J-K master/slave flip-flop This is a demonstration file for Figure The input 'STIM1' components connected to J, K and CLK have been programmed to reproduce the sample waveforms given in Figure Set up a transient analysis with a 'Final Time' of 17us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the input and output waveforms as in the text. You will see that Copyright Addison Wesley Longman Limited,

13 although the text assumes that the Q output of the latch is initially at 0, the simulation shows that the output is actually undefined until the first active clock transition. FILE10G: A simple ripple counter This is a demonstration file for Figure and Computer Simulation Exercise The input 'DigClock' components connected to CLK has been programmed to reproduce a 1MHz clock with an equal mark to space ratio. Set up a transient analysis with a 'Final Time' of 17us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the waveforms shown in Figure of the text. FILE10H: A decade ripple counter This is a demonstration file for Figure and Computer Simulation Exercise The input 'DigClock' components connected to CLK has been programmed to reproduce a 1MHz clock with an equal mark to space ratio. Set up a transient analysis with a 'Final Time' of 22.3us and a 'Print Step' of 100ns and run the simulation. This should result in Probe displaying the waveforms shown in Figure of the text. FILE11A: A logical inverter This is a demonstration file for Computer Simulation Exercise The 'STIM1' component has been programmed to produce a 250ns pulse. Set up a transient analysis with a 'Print Step' of 1ns and a 'Final Time' of 1us, and run the simulation. Use Probe to display on separate plots the input voltage V(Vi), the collector current IC(Q1) and the output voltage V(Vo). Compare your results with those given in Figure 11.5 and hence determine the turn-on and turn-off times for this arrangement. Increase the value of the base resistor to 10k and repeat the procedure, comparing your results with those obtained before. FILE11B: An RTL NOR gate This is a demonstration file for Figure The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11C: A diode logic AND gate This is a demonstration file for Figure 11.9(a). The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11D: A diode logic OR gate This is a demonstration file for Figure 11.9(b). The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. Copyright Addison Wesley Longman Limited,

14 FILE11E: A DTL NAND gate This is a demonstration file for Figure The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11F: A CMOS inverter This is a demonstration file for Figure The 'STIM1' component has been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce two separate plots showing the input voltage V(A) and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11G: A CMOS NAND gate This is a demonstration file for Figure 11.18(a). The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11H: A CMOS NOR gate This is a demonstration file for Figure 11.18(b). The 'STIM1' components have been configured to produce an irregular train of pulses to illustrate the operation of the gate. Set up a transient analysis with a 'Print Step' of 100ns and a 'Final Time' of 100us, and run the analysis. Use Probe to produce three separate plots showing the input voltages V(A) and V(B), and the output voltage V(Vo). Confirm that the circuit has the correct characteristics. FILE11J: A simple Schmitt trigger This is a demonstration file for Figure In order to appreciate the operation of this circuit we need to look at its transfer function. PSpice allows us to plot transfer functions directly, although in this case we are interested in two different transfer functions: that of the circuit when the input voltage is increasing (going more positive) and that of the circuit when the output is decreasing (going more negative). In order to observe these two distinct transfer functions we will display them separately. First set up a DC sweep for Vi with a start value of -15V and an end value of +15V, in increments of 0.1V. Next go to the 'Transfer Function' box in the 'Analysis Setup' box, and set the output variable to be V(Vo) and the input source to be Vi. Now run the simulation and observe the transfer function displayed by Probe. This shows that as the input voltage increases from -15V the output remains constant at about +15 volts until the input reaches +5V when the output changes abruptly to -15V. Thus the threshold voltage for increasing voltages is +5V. Now return to the DC sweep setup box and reverse the direction of the sweep by setting the start value to +15V and the end value to -15V. Now repeat the simulation and again observe the transfer function using Probe. You will now see that as the voltage drops from 15V the output remains constant at about -15V until the input reaches -5V when the output changes to +15V. Thus the threshold voltage for decreasing voltages is -5V. If you imagine these two waveforms superimposed on each other (with arrows showing the direction of change) we would have a graph similar to Figure (with the polarity of the output inverted). The reason for the change of polarity of Vo is that we are using an inverting amplifier. Copyright Addison Wesley Longman Limited,

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