Registers. CS152 Computer Architecture and Engineering Lecture 3

Transcription

1 CS52 Computer rchitecture and Engineering Lecture 3 Logic Design, Technology, and Delay January 28, 24 John Kubiatowicz (wwwcsberkeleyedu/~kubitron) lecture slides: Review:MIPS R3 Set rchitecture Register Set general -bit registers Register zero ($R) always zero Hi/Lo for multiplication/division Categories Load/Store Computational - teger/floating point Jump and ranch Memory Management Special 3 Formats: all bits wide OP OP OP R - R3 PC HI LO rs rt rd sa funct rs rt immediate jump target Registers Lec The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman does not distinguish between the conceptualization and the artifact -- Separation comes about because of complexity -- The concept is captured in one or more representation languages VERILOG, Schematics, etc -- This process IS design Design egins With Requirements -- Functional Capabilities: what it will do Design Process (cont) Design Finishes s ssembly -- Design understood in terms of components and how they have been assembled -- Top Down decomposition of complex functions (behaviors) into more primitive functions path CPU LU Regs Shifter Nand Gate -- bottom-up composition of primitive building blocks into more complex assemblies Control Design is a "creative process," not a simple method -- Performance Characteristics: Speed, Power, rea, Cost, Lec33 Lec34

2 Design Refinement formal System Requirement itial Specification refinement increasing level of detail termediate Specification Final rchitectural Description termediate Specification of Implementation Logic Components Final ternal Specification Physical Implementation Lec35 Lec36 Elements of the design zoo Wires: Carry signals from one point to another Single bit (no size label) or multi-bit bus (size label) Combinational Logic: Like function evaluation goes in, Results come out after some propagation delay Combinational Logic Flip-Flops: Storage Elements fter a clock edge, input copied to output Otherwise, the flip-flop holds its value lso: a Latch is a storage element that is level triggered D Q D[8] Q[8] 8 8 Lec37 asic Combinational Elements+DeMorgan Equivalence Wire = NND Gate = = + DeMorgan s Theorem verter = NOR Gate = + = Lec38

3 General C/L Cell Delay Model Combinational Logic Cell Cout ternal Delay Combinational Cell (symbol) is fully specified by: functional (input -> output) behavior - truth-table, logic equation, VHDL put load factor of each input Delay Va -> delay per unit load Propagation delay from each input to each output for each transition - T HL (, o) = Fixed ternal Delay + Load-dependent-delay x load Ccritical Cout Storage Element s Timing Model D Q Setup Hold D Don t Care Don t Care Clock-to-Q Q Unknown Setup Time: put must be stable EFORE trigger clock edge Hold Time: put must REMIN stable after trigger clock edge Clock-to-Q time: put cannot change instantaneously at the trigger clock edge Similar to delay in logic gates, two components: - ternal Clock-to-Q - Load dependent Clock-to-Q Linear model composes Lec39 Lec3 Clocking Methodology Critical Path & Cycle Time Combination Logic ll storage elements are clocked by the same clock edge The combination logic blocks: puts are updated at each clock tick ll outputs MUST be stable before the next clock tick Critical path: the slowest path between any two storage devices Cycle time is a function of the critical path must be greater than: Clock-to-Q + Longest Path through Combination Logic + Setup Lec3 Lec

4 Clock Skew s Effect on Cycle Time How to void Hold Time Violation? 2 Clock Skew Combination Logic The worst case scenario for cycle time consideration: The input register sees CLK The output register sees CLK2 2 Cycle Time - Clock Skew CLK-to-Q + Longest Delay + Setup Cycle Time CLK-to-Q + Longest Delay + Setup + Clock Skew Hold time requirement: put to register must NOT change immediately after the clock tick This is usually easy to meet in the edge trigger clocking scheme Hold time of most FFs is <= ns CLK-to-Q + Shortest Delay Path must be greater than Hold Time Lec33 Lec34 Clock Skew s Effect on Hold Time dministrative Matters 2 2 Clock Skew Combination Logic The worst case scenario for hold time consideration: The input register sees CLK2 The output register sees CLK fast FF2 output must not change input to FF for same clock edge (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time Lec35 Sections start tomorrow! 2: 4:, 4: 6: in 37 Etcheverry Want announcements directly via ? Look at information page to sign up for cs52-announce mailing list Prerequisite quiz will be Monday 2/2 during class: Review Sunday (2/), 7:3 9: pm here (36 Soda) Review Chapters -4, 7-72, p, p, of COD, Second Edition Turn in survey form (with picture!) [Can t get into class without one!] Homework # also due Monday 2/2 at beginning of lecture! No homework quiz this time (Prereq quiz may contain homework material, since this is supposed to be review) Lab Due Wednesday 2/4 Lec36

5 Finite State Machines: System state is explicit in representation Transitions between states represented as arrows with inputs on arcs put may be either part of state or on arcs Mod 3 Machine 6 Mod 3 put (MS first) 2 2 lpha/ Delta/ 2 eta/ Lec37 Implementation as Combinational logic + Latch Combinational Logic FlipFlop Mealey Machine Moore Machine / lpha/ / / / / Delta/ 2 eta/ / put State old State new Div Lec38 Example: Simplification of logic C S = = S = = 2 State 2 flops Comb Logic 3 S S C S S ( S ) ( ) ( ) C + S C + S C + ( S C) ( S C) + ( S C) ( S ) ( ) ( ) C + S C + S C + ( S C) ( S C) + ( S C) + ( S ) Lec39 C Karnaugh Map for easier simplification S S C S S State 2 flops Next State Comb Logic S s ( S C) + ( S C) S = s ( S C) + ( S C) + ( S ) = S Lec

6 One-Hot Encoding Review: The loop of control (is there a statemachine?) C State 4 flops Comb Logic One Flip-flop per state Only one state bit = at a time Much faster combinational logic Tradeoff: Size Speed 2 S = S = S = 2 S = 3 3 ( S ) ( ) C + S3 C ( S ) ( ) C + S C ( S2 C) + ( S C) ( S + ( S C) 3 2 Lec Fetch Decode Operand Fetch Execute Result Store Format or Encoding how is it decoded? Location of operands and result where other than memory? how many explicit operands? how are memory operands located? which can or cannot be in memory? type and Size Operations what are supported Successor instruction Next jumps, conditions, branches fetch-decode-execute is implicit! Lec2 Designing a machine that executes MIPS Next ddress Ideal Memory ddress PC Rd 5 Rs 5 Rw Ra Rt 5 Rb -bit Registers Control Control Signals LU path Conditions ddress Ideal Memory If you don t fully remember this, it is ok! (Don t need for prereq quiz) Lec3 peek: Single Cycle path Rs, Rt, Rd and Imed6 hardwired from Fetch Unit Combinational logic for decode and lookup busw Rd Rt RegDst Mux Rs Rt RegWr imm6 Rw Ra Rb -bit Registers 6 npc_sel bus Extender bus /28/4 ExtOp UC Spring 24 Mux LUSrc Fetch Unit LUctr LU <3:> Rt Zero <2:25> Rs <6:2> WrEn dr Memory Rd MemWr <:5> <:5> Imm6 Mux MemtoReg Lec4

7 peek: PL Implementation of the Main Control op<5> op<5> op<5> op<5> op<5> op<5> <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite LUSrc RegDst MemtoReg MemWrite ranch Jump ExtOp LUop<2> LUop<> LUop<> Lec5 peek: n bstract View of the Critical Path (Load) Register file and ideal memory: Next ddress The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - ddress valid => put valid after access time Ideal Memory ddress PC Rd 5 Rs 5 Rt 5 Rw Ra Rb -bit Registers Imm 6 Critical Path (Load Operation) = PC s -to-q + Memory s ccess Time + Register File s ccess Time + LU to Perform a -bit dd + Memory ccess Time + Setup Time for Register File Write + Clock Skew LU ddress Ideal Memory Lec6 Worst Case Timing (Load s) Ultimately: It s all about communication -to-q PC Old Value New Value Memory ccess Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic LUctr Old Value New Value ExtOp Old Value New Value LUSrc Old Value New Value Proc Caches Memory usses Pentium III Chipset adapters MemtoReg Old Value New Value Register Write Occurs RegWr Old Value New Value Register File ccess Time bus Old Value New Value Delay through Extender & Mux bus Old Value New Value LU Delay ddress Old Value New Value Memory ccess Time busw Old Value CS52 New/ Kubiatowicz Lec7 I/O Devices: Controllers Disks Displays Keyboards Networks ll have interfaces & organizations New Pentium Chip: 3 cycle pipeline Pipeline stages for communication? I would bet it s true! Lec8

8 Delay Model: CMOS Lec9 Review: General C/L Cell Delay Model Combinational Logic Cell Combinational Cell (symbol) is fully specified by: functional (input -> output) behavior - truth-table, logic equation, VHDL load factor of each input Cout critical propagation delay from each input to each output for each transition - T HL (, o) = Fixed ternal Delay + Load-dependent-delay x load Linear model composes ternal Delay Delay Va -> delay per unit load Ccritical Cout Lec33 asic Technology: CMOS CMOS: Complementary Metal Oxide Semiconductor NMOS (N-Type Metal Oxide Semiconductor) transistors PMOS (P-Type Metal Oxide Semiconductor) transistors = 5V asic Components: CMOS verter Symbol Circuit PMOS NMOS NMOS Transistor pply a HIGH () to its gate turns the transistor into a conductor pply a LOW (GND) to its gate shuts off the conduction path PMOS Transistor pply a HIGH () to its gate shuts off the conduction path pply a LOW (GND) to its gate turns the transistor into a conductor GND = v = 5V GND = v Lec33 verter Operation Charge Open Vin Open Discharge Lec3

9 asic Components: CMOS Logic Gates asic Components: CMOS Logic Gates = NND Gate = + NOR Gate C D 4-input NND Gate C D More puts More asymmetric Edges Times! Lec333 Lec334 Ideal versus Reality Fluid Timing Model When input ->, output -> but NOT instantly put goes -> : output voltage goes from (5v) to v When input ->, output -> but NOT instantly put goes -> : output voltage goes from v to (5v) Voltage does not like to change instantaneously => Voltage => GND Vin Time Lec335 Level (V) = Reservoir SW Tank (Cout) Tank Level () SW2 Water Electrical Charge Tank Capacity Capacitance (C) Water Level Voltage Water Flow Charge Flowing (Current) Size of Pipes Strength of Transistors (G) Time to fill up the tank proportional to C / G Sea Level (GND) ottomless Sea SW SW2 Cout Lec336

10 Series Connection Vin Voltage /2 G Vin V d G2 V d2 Vin G V C GND Time Total Propagation Delay = Sum of individual delays = d + d2 Capacitance C has two components: Capacitance of the wire connecting the two gates put capacitance of the second inverter G2 Cout Lec337 Calculating ggregate Delays Vin V Sum delays along serial paths Delay (Vin -> V2)! = Delay (Vin -> V3) V2 V3 Delay (Vin -> V2) = Delay (Vin -> V) + Delay (V -> V2) Delay (Vin -> V3) = Delay (Vin -> V) + Delay (V -> V3) Critical Path = The longest among the N parallel paths C = Wire C + Cin of Gate 2 + Cin of Gate 3 Vin G V C G2 G3 V2 V3 Lec338 Characterize a Gate put capacitance for each input For each input-to-output path: For each output transition type (H->L, L->H, H->Z, L->Z etc) - ternal delay (ns) - Load dependent delay (ns / ff) Example: 2-input NND Gate For and : put Load (IL) = 6 ff For either -> or -> : Tlh = 5ns Tlhf = 2ns / ff Thl = ns Thlf = 2ns / ff 5ns Delay -> : Low -> High Slope = 2ns / ff Cout Lec339 Specific Example: 2 to MU Wire S Gate Gate 2 put Load (IL) Wire Wire 2, : IL (NND) = 6 ff Gate 3 Y = ( and!s) or ( and S) S: IL (INV) + IL (NND) = 5 ff + 6 ff = ff Load Dependent Delay (LDD): Same as Gate 3 TYlhf = 2 ns / ff TYhlf = 2 ns / ff TYlhf = 2 ns / ff TYhlf = 2 ns / ff TSYlhf = 2 ns / ff TSYlhf = 2 ns / ff 2 x Mux S Y Lec34

11 2 to MU: ternal Delay Calculation 2 to MU: ternal Delay Calculation (continue) Wire Gate Wire Gate 3 Y = ( and!s) or ( and S) Wire Gate Wire Gate 3 Y = ( and!s) or ( and S) Gate 2 Wire 2 Gate 2 Wire 2 S S ternal Delay (ID): to Y: ID G + (Wire C + G3 put C) * LDD G + ID G3 to Y: ID G2 + (Wire 2 C + G3 put C) * LDD G2 + ID G3 S to Y (Worst Case): ID v + (Wire C + G put C) * LDD v + ternal Delay to Y We can approximate the effect of Wire C by: ssume Wire has the same C as all the gate C attached to it ternal Delay (ID): to Y: ID G + (Wire C + G3 put C) * LDD G + ID G3 to Y: ID G2 + (Wire 2 C + G3 put C) * LDD G2 + ID G3 S to Y (Worst Case): ID v + (Wire C + G put C) * LDD v + ternal Delay to Y Specific Example: TYlh = TPhl G + (2 * 6 ff) * TPhlf G + TPlh G3 = ns + 22 ff * 2 ns/ff + 5ns = 844 ns Lec34 Lec342 bstraction: 2 to MU KISS RULE: Keep It Simple, Stupid! Gate Gate 2 Gate 3 S put Load: = 6 ff, = 6 ff, S = ff Load Dependent Delay: TYlhf = 2 ns / ff TYhlf = 2 ns / ff TYlhf = 2 ns / ff TYhlf = 2 ns / ff TSYlhf = 2 ns / ff TSYlhf = 2 ns / f F ternal Delay: TYlh = TPhl G + (2 * 6 ff) * TPhlf G + TPlh G3 = ns + 22 ff * 2ns/fF + 5ns = 844ns Fun Exercises: TYhl, TYlh, TSYlh, TSYlh Y 2 x Mux S Y Lec343 Simple designs: Can be debugged easier Have lower capacitance on any one output (less fan-out) Have fewer gates in the critical path (complexity Less Power consumption Complex designs: More gates/capacitance (probably slower clock rate!) More functionality per cycle (may occasionally win out!) More Power More ugs! Which is better? etter evaluate carefully more gates) Lec344

12 FPG Overview asic idea: 2D array of combination logic blocks (CL) and flip-flops (FF) with a means for the user to configure both: the interconnection between the logic blocks, 2 the function of each block Emulation with FPGs Lec345 Simplified version of FPG internal architecture Lec346 Where are FPGs in the IC Zoo? Source: quest Programmable Logic Devices (PLDs) SPLDs (PLs) Standard Logic Gate rrays CPLDs Logic SIC Cell-ased ICs FPGs Full Custom ICs FPG Variations Families of FPG s differ in: physical means of implementing user programmability, arrangement of interconnection wires, and basic functionality of logic blocks Most significant difference is in the method for providing flexible blocks and connections: nti-fuse based (ex: ctel) + Non-volatile, relatively small - fixed (non-reprogrammable) (lmost used in 5 Lab: only -shot at getting it right!) cronyms SPLD = Simple Prog Logic Device PL = Prog rray of Logic CPLD = Complex PLD FPG = Field Prog Gate rray Common Resources Configurable Logic locks (CL) Memory Look-Up Table ND-OR planes Simple gates put / put locks (IO) idirectional, latches, inverters, pullup/pulldowns terconnect or Routing Local, internal feedback, and global (Standard logic is SSI or MSI buffers, gates) Lec348

13 User Programmability Idealized FPG Logic lock Latch-based (ilinx, ltera, ) latch Latches are used to: make or break cross-point connections in interconnect 2 define function of logic blocks 3 set user options: - within the logic blocks - in the input/output blocks - global reset/clock INPUTS Logic lock 4-LUT FF latch set by configuration bit-stream OUTPUT + reconfigurable - volatile - relatively large die size - Note: Today 9% die is interconnect, % is gates Configuration bit stream loaded under user control: ll latches are strung together in a shift chain Programming => creating bit stream 4-input Look Up Table (4-LUT) implements combinational logic functions Register 4-input "look up table" optionally stores output of LUT Latch determines whether read reg or LUT Lec349 Lec35 4-LUT Implementation 6 latch latch latch latch INPUTS 6 x mux OUTPUT Latches programmed as part of configuration bit-stream n-bit LUT is actually implemented as a 2 n x memory: inputs choose one of 2 n memory locations memory locations (latches) are normally loaded with values from user s configuration bit stream puts to mux control are the CL (Configurable Logic lock) inputs Result is a general purpose logic gate n-lut can implement any function of n inputs! Lec35 LUT as general logic gate n n-lut as a direct implementation of a function truth-table Each latch location holds value of function corresponding to one input combination Example: 2-lut INPUTS ND OR Implements any function of 2 inputs How many functions of n inputs? Example: 4-lut INPUTS F(,,,) F(,,,) F(,,,) F(,,,) store in st latch store in 2nd latch Lec352

14 Why FPGs? ( / 5) y the early 98 s most of logic circuits in typical systems were absorbed by a handful of standard large scale integrated circuits (LSI ICs) Microprocessors, bus/io controllers, system timers, Every system still needed random small glue logic ICs to help connect the large ICs: generating global control signals (for resets etc) data formatting (serial to parallel, multiplexing, etc) Systems had a few LSI components and lots of small low density SSI (small scale IC) and MSI (medium scale IC) components Why FPGs? (2 / 5) Custom ICs sometimes designed to replace glue logic: reduced complexity/manufacturing cost, improved performance ut custom ICs expensive to develop, and delay introduction of product ( time to market ) because of increased design time Note: need to worry about two kinds of costs: cost of development, Non-Recurring Engineering (NRE), fixed 2 cost of manufacture per unit, variable Usually tradeoff between NRE cost and manufacturing costs Printed Circuit (PC) board with many small SSI and MSI ICs and a few LSI ICs Total Cost NRE NRE Lec353 Few Medium Many /28/4 UC Units Spring manufactured 24 Lec354 Why FPGs? (3 / 5) Why FPGs? (4 / 5) Therefore custom IC approach was only viable for products with very high volume (where NRE could be amortized), and not sensitive in time to market (TTM) FPGs introduced as alternative to custom ICs for implementing glue logic: improved PC board density vs discrete SSI/MSI components (within around x of custom ICs) computer aided design (CD) tools meant circuits could be implemented quickly (no physical layout process, no mask making, no IC manufacturing), relative to pplication Specific ICs (SICs) (3-6 months for these steps for custom IC) - lowers NREs (Non Recurring Engineering) - shortens TTM (Time To Market) ecause of Moore s law the density (gates/area) of FPGs continued to grow through the 8 s and 9 s to the point where major data processing functions can be implemented on a single FPG FPGs continue to compete with custom ICs for special processing functions (and glue logic) but now try to compete with microprocessors in dedicated and embedded applications Performance advantage over microprocessors because circuits can be customized for the task at hand Microprocessors must provide special functions in software (many cycles) MICRO: Highest NRE, SW: fastest TTM SIC: Highest performance, worst TTM FPG: Highest cost per chip (unit cost) Lec355 Lec356

15 Why FPGs? (5 / 5) s Moore s Law continues, FPGs work for more applications as both can do more logic in chip and faster Can easily be patched vs SICs Perfect for courses: Can change design repeatedly Low TTM yet reasonable speed With Moore s Law, now can do full CS 52 project easily inside FPG Lec357 Summary Design = translating specification into physical components Combinational, Sequential (FlipFlops), Wires Timing is important Critical path: maximum time between clock edges Clocking Methodology and Timing Considerations Simplest clocking methodology - ll storage elements use the SME clock edge Cycle Time CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time lgebraic Simplification Karnaugh Maps Speed Size tradeoffs! (Many to be shown Performance and Technology Trends Keep the design simple (KISS rule) to take advantage of the latest technology CMOS inverter and CMOS logic gates Delay Modeling and Gate Characterization Delay = ternal Delay + (Load Dependent Delay x put Load) FPGs: programmable logic Lec358