You are Here! Processor Design Process. Agenda. Agenda 10/25/12. CS 61C: Great Ideas in Computer Architecture Single Cycle MIPS CPU Part II

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/26/2 CS 6C: Great Ideas in Computer Architecture Single Cycle MIPS CPU Part II /25/2 ructors: Krste Asanovic, Randy H. Katz hcp://inst.eecs.berkeley.

g., 5 pipelined uctons Parallel > data item @ one Tme e.g., Add of pairs of words Hardware descriptons All gates @ one Tme Programming Languages You are Here!

Computer (Cache) Core FuncTonal Unit(s) A +B A +B A 2 +B 2 A 3 +B 3 Today Levels of RepresentaTon/ InterpretaTon High Level Language Program (e.g., C) Compiler Assembly Language Program (e.

e., data or uctons! Logic Circuit DescripCon /25/2 (Circuit SchemaCc Diagrams) Fall 22 - - Lecture #26 3 Processor Design Process Five steps to design a processor:.

Analyze implementaton of each ucton to determine sehng of control points that effects the register transfer. 5.

1 /26/2 CS 6C: Great Ideas in Computer Architecture Single Cycle MIPS CPU Part II /25/2 ructors: Krste Asanovic, Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs6c/fa2 Fall Lecture #26 Parallel Requests Assigned to computer e.g., Search Katz Parallel Threads Assigned to core e.g., Lookup, Ads Soware Parallel ructons > one Tme e.g., 5 pipelined uctons Parallel > data one Tme e.g., Add of pairs of words Hardware descriptons All one Tme Programming Languages You are Here! Harness Parallelism & Achieve High Performance Hardware Warehouse Scale Computer Core Input/Output ructon Unit(s) Cache Core Smart Phone Logic Gates /25/2 Fall Lecture #26 2 Computer (Cache) Core FuncTonal Unit(s) A +B A +B A 2 +B 2 A 3 +B 3 Today Levels of RepresentaTon/ InterpretaTon High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g., MIPS) Machine Interpretaon Assembler Machine Language Program (MIPS) Hardware Architecture DescripCon (e.g., block diagrams) Architecture Implementaon temp v[k]; v[k] v[k+]; v[k+] temp; lw $t, ($2) lw $t, ($2) sw $t, ($2) sw $t, ($2) Anything can be represented as a number, i.e., data or uctons! Logic Circuit DescripCon /25/2 (Circuit SchemaCc Diagrams) Fall Lecture #26 3 Processor Design Process Five steps to design a processor:. Analyze ucton set à Processor datapath requirements Control 2. Select set of datapath components & establish path clock methodology 3. Assemble datapath meetng the requirements. Analyze implementaton of each ucton to determine sehng of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic EquaTons Design Circuits /25/2 Fall Lecture #26 Input Output path Control path Control /25/2 Fall Lecture #26 5 /25/2 Fall Lecture #26 6

2 /26/2 ADDU and SUBU addu rd,rs,rt subu rd,rs,rt OR Immediate: ori rt,rs,imm6 LOAD and 3 STORE Word lw rt,rs,imm6 sw rt,rs,imm6 3 BRANCH: beq rs,rt,imm6 The MIPS- lite Subset op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits bits 5 bits 5 bits 6 bits bits 5 bits 5 bits 6 bits bits 5 bits 5 bits 6 bits /25/2 Fall Lecture #26 7 Register Transfer Language (RTL) RTL gives the meaning of the uctons {op, rs, rt, rd, shamt, funct} MEM[ ]! {op, rs, rt, Imm6} MEM[ ]! All start by ing the ucton Register Transfers! ADDU R[rd] R[rs] + R[rt]; +! SUBU R[rd] R[rs] R[rt]; +! ORI R[rt] R[rs] zero_et(imm6); +! LOAD R[rt] MEM[ R[rs] + sign_et(imm6)]; +! STORE MEM[ R[rs] + sign_et(imm6) ] R[rt]; +! BEQ if ( R[rs] R[rt] ) then + + (sign_et(imm6) ) else +! /25/2 Fall Lecture #26 8 RTL: The Add ructon op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[] Fetch the ucton from memory R[rd] R[rs] + R[rt] The actual operaton + Calculate the net ucton s address ructon Fetch Unit at the Beginning of Add Fetch the ucton from ructon memory: ructon MEM[] same for all uctons Et n_sel Mu Address ructon<3:> /26/2 Spring Lecture #26 9 imm6 /26/2 Spring Lecture #26 Single Cycle path during Add op rs rt rd shamt funct R[rd] R[rs] + R[rt] RegDst rd n_sel+ rt RegWr rs rt imm6 6 EtOp Rs Imm6 zero ctradd MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /26/2 Spring Lecture #26 ructon Fetch Unit at End of Add + Same for all uctons ecept: Branch and Jump Et imm6 n_sel+ Mu Address /26/2 Spring Lecture #26 2 2

3 /26/2 Single Cycle path during Or Immediate R[rt] R[rs] OR ZeroEt[Imm6] RegDst RegWr Rs n_sel imm6 6 EtOp Rs Imm6 zero ctr MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 3 Student RouleCe Single Cycle path during Or Immediate 3 26 R[rt] R[rs] OR ZeroEt[Imm6] RegDst RegWr Rs n_sel+ imm6 6 EtOpzero 2 6 Rs Imm6 zero ctror MemtoReg /25/2 Fall Lecture #26 Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> Single Cycle path during Load R[rt] {R[rs] + SignEt[imm6]} RegDst RegWr Rs n_sel imm6 6 EtOp Rs Imm6 zero ctr MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> /25/2 Fall Lecture #26 5 <:5> Student RouleCe Single Cycle path during Load R[rt] {R[rs] + SignEt[imm6]} RegDst RegWr Rs n_sel+ imm6 6 EtOpsign Rs Imm6 zero ctradd MemtoReg Src ruction<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 6 Single Cycle path during Store {R[rs] + SignEt[imm6]} R[rt] RegDst RegWr Rs n_sel imm6 6 EtOp Rs Imm6 zero ctr MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 7 Student RouleCe Single Cycle path during Store {R[rs] + SignEt[imm6]} R[rt] RegDst RegWr Rs n_sel+ imm6 6 EtOpsign Rs Imm6 zero ctradd MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 8 3

/26/2 Single Cycle path during Branch 3 26 2 6 if (R[rs] - R[rt] ) then Zero ; else Zero RegDst RegWr Rs n_sel imm6 6 EtOp Rs Imm6 zero ctr MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr

MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall 22 - - Lecture #26 2 ructon Fetch Unit at the End of Branch 3 26 2 6 if (Zero ) then + + SignEt[imm6]* ; else + n_sel

MUX Fall 22 - - Lecture #26 Q: What logic gate?

4 /26/2 Single Cycle path during Branch if (R[rs] - R[rt] ) then Zero ; else Zero RegDst RegWr Rs n_sel imm6 6 EtOp Rs Imm6 zero ctr MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 9 Single Cycle path during Branch if (R[rs] - R[rt] ) then Zero ; else Zero RegDst RegWr Rs n_selbr imm6 6 EtOp Rs Imm6 zero ctrsub MemtoReg Src ructon<3:> <2:25> In <6:2> MemWr <:5> <:5> /25/2 Fall Lecture #26 2 ructon Fetch Unit at the End of Branch if (Zero ) then + + SignEt[imm6]* ; else + n_sel Zero imm6 Et MUX n_sel ctrl Mu Adr ructon<3:> What is encoding of n_sel? Direct MUX select? Branch inst. / not branch Let s pick 2nd opton n_sel zero? MUX Fall Lecture #26 Q: What logic gate? /25/2 2 Summary: path s Control Signals EtOp: zero, sign src: regb; immed ctr: ADD, SUB, OR Et Address n_sel Mu RegDst RegWr Rs imm6 6 EtOp MemWr: write memory MemtoReg: ; Mem RegDst: rt ; rd RegWr: write register ctr MemtoReg MemWr /25/2 Fall Lecture #26 22 imm6 Src In CS6c in the News path Control /25/2 Fall Lecture #26 23 /26/2 Fall Lecture #26 2

5 /26/2 path Control /26/2 Fall Lecture #26 25 /25/2 Fall Lecture #26 26 Given path: RTL à Control Adr ructon<3:> <26:3> <:5> Op Fun <2:25> <6:2> <:5> <:5> Imm6 n_sel RegWr RegDst EtOp Src ctr Rs Control DATA PATH MemWr MemtoReg inst Summary of the Control Signals (/2)!Register Transfer! add!r[rd] R[rs] + R[rt]; +!!srcregb, ctr ADD, RegDstrd, RegWr, n_sel +!! sub!r[rd] R[rs] R[rt]; +!!srcregb, ctr SUB, RegDstrd, RegWr, n_sel +! ori!r[rt] R[rs] + zero_et(imm6); +!!srcim, Etop Z, ctr OR, RegDstrt,RegWr, n_sel +! lw!r[rt] MEM[ R[rs] + sign_et(imm6)]; +!!srcim, Etop sn, ctr ADD, MemtoReg, RegDstrt, RegWr,!n_sel +! sw!mem[ R[rs] + sign_et(imm6)] R[rs]; +!!srcim, Etop sn, ctr ADD, MemWr, n_sel +! beq!if (R[rs] R[rt]) then + sign_et(imm6)]!else +!!n_sel br, ctr SUB! /25/2 Fall Lecture #26 27 /25/2 Fall Lecture #26 28 Summary of the Control Signals (2/2) See func We Don t Care :- ) Appendi A op add sub ori lw sw beq RegDst Src MemtoReg RegWrite MemWrite nsel Jump EtOp ctr<2:> Add Subtract Or Add Add Subtract R- type op rs rt rd shamt funct add, sub I- type ori, lw, sw, beq /25/2 Fall Lecture #26 29 Boolean Epressions for Controller RegDst add + sub Src ori + lw + sw MemtoReg lw RegWrite add + sub + ori + lw MemWrite sw nsel beq Jump jump EtOp lw + sw ctr[] sub + beq (assume ctr is ADD, : SUB, : OR) ctr[] or! Where:! rtype ~op 5 ~op ~op 3 ~op 2 ~op ~op, ori ~op 5 ~op op 3 op 2 ~op op lw op 5 ~op ~op 3 ~op 2 op op sw op 5 ~op op 3 ~op 2 op op beq ~op 5 ~op ~op 3 op 2 ~op ~op jump ~op 5 ~op ~op 3 ~op 2 op ~op! How do we implement this in gates? add rtype func 5 ~func ~func 3 ~func 2 ~func ~func sub rtype func 5 ~func ~func 3 ~func 2 func ~func! /25/2 Fall Lecture #26 3 5

/26/2 Controller ImplementaTon AND Control in Logisim opcode func AND logic add sub ori lw sw beq OR logic RegDst Src MemtoReg RegWrite MemWrite nsel EtOp ctr[] ctr[] /25/2 Fall 22 - - Lecture #26 3

6 /26/2 Controller ImplementaTon AND Control in Logisim opcode func AND logic add sub ori lw sw beq OR logic RegDst Src MemtoReg RegWrite MemWrite nsel EtOp ctr[] ctr[] /25/2 Fall Lecture #26 3 /25/2 Fall Lecture #26 OR Control Logic in Logisim /25/2 Fall Lecture #26 33 Single Cycle Performance Assume Tme for actons are ps for register read or write; 2ps for other events Clock rate is? r r Register read op /25/2 Fall Lecture #26 access Register write Total time lw 2ps ps 2ps 2ps ps 8ps sw 2ps ps 2ps 2ps 7ps R-format 2ps ps 2ps ps 6ps beq 2ps ps 2ps 5ps What can we do to improve clock rate? Will this improve performance as well? Want increased clock rate to mean faster programs 3 Student RouleCe? And in Conclusion, Single- Cycle Processor Five steps to design a processor:. Analyze ucton set à Processor datapath requirements Control 2. Select set of datapath components & establish path clock methodology 3. Assemble datapath meetng the requirements. Analyze implementaton of each ucton to determine sehng of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic EquaTons Design Circuits /25/2 Fall Lecture #26 35 Input Output 6

EECS150 - Digital Design Lecture 2 - Synchronous Digital Systems Review Part 1. Outline

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