EECS 470 Lecture 4. Pipelining & Hazards II. Winter Prof. Ronald Dreslinski h8p://
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1 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar EECS 4 ecture 4 Pipelining & Hazards II Winter 29 GS STTION Prof. Ronald Dreslinski h8p:// Slides developed in part by Profs. ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar, and Wenisch of Carnegie ellon niversity, Purdue niversity, niversity of ichigan, niversity of Pennsylvania, and niversity of Wisconsin. EECS 4 ecture 4 Slide
2 nnouncements Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Programming assignment #2 due Tuesday /29 Electronic hand-in by :59pm HW # 2 released, Due Thursday / EECS 4 ecture 4 Slide 2
3 Readings Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar For Thursday /9: H & P Chapter C.5-C.,.-.,. EECS 4 ecture 4 Slide
4 Sample Code (Simple) Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Run the following code on a pipelined path: add 2 ; reg = reg reg 2 nand ; reg 6 = reg 4 & reg 5 lw ; reg 4 = em[reg22] add ; reg 5 = reg 2 reg 5 sw ; em[reg] =reg EECS 4 ecture Slide 4
5 Wenisch et al. 2 instruction reg regb R val valb offset target eq? result valb ory result m dest Bits -2 Bits 6-8 Bits dest op / E dest op E/ em dest op em/ 5
6 Wenisch et al. 2 Initial State noop Bits -2 Bits 6-8 Bits R noop / E noop E/ em ory noop em/ dest 6
7 Wenisch et al. 2 add 2 Fetch: add 2 Time: add 2 Bits -2 Bits 6-8 Bits R noop / E noop E/ em ory noop em/ dest
8 Wenisch et al. 2 nand add 2 Fetch: nand Time: 2 2 nand Bits -2 Bits 6-8 Bits R add / E noop E/ em ory noop em/ dest 8
9 Wenisch et al. 2 lw nand add 2 Fetch: lw Time: lw Bits -2 Bits 6-8 Bits R nand / E add E/ em ory noop em/ dest 9
10 Wenisch et al. 2 add lw nand add 2 Fetch: add Time: 4 4 add Bits -2 Bits 6-8 Bits R lw / E nand E/ em 45 ory 45 add em/ dest
11 Wenisch et al. 2 sw add lw nand add Fetch: sw Time: 5 5 sw 2 5 Bits -2 Bits 6-8 Bits R add / E lw E/ em - 6 ory - 6 nand 45 em/ dest
12 Wenisch et al. 2 sw add lw nand No more instructions Time: 6 Bits -2 Bits 6-8 Bits R sw / E add E/ em 29 4 ory lw - 6 em/ dest 2
13 Wenisch et al. 2 sw add lw No more instructions Time: Bits -2 Bits 6-8 Bits R / E sw E/ em 6 5 ory 6 5 add 99 4 em/ dest
14 Wenisch et al. 2 sw add R ory 55 6 dest No more instructions Time: 8 Bits -2 Bits 6-8 Bits / E E/ em sw 5 em/ 4
15 Wenisch et al. 2 sw R ory dest No more instructions Bits -2 Bits 6-8 Bits Time: 9 / E E/ em em/ 5
16 Outline: Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar nderstanding the Execution Core. s 5-stage pipeline (review) 2. Implemen]ng pipeline interlocks (review). Scoreboard scheduling (CDC 66) 4. Tomasulo s OoO scheduling algorithm (IB 6) 5. Precise interrupts with a Reorder Buffer (P6) 6. odern OoO (IPS K, Netburst) EECS 4 ecture 4 Slide 6
17 Time graphs Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Time: add fetch decode execute ory writeback nand fetch decode execute ory writeback lw fetch decode execute ory writeback add fetch decode execute ory writeback sw fetch decode execute ory writeback EECS 4 ecture 4 Slide
18 Balancing Pipeline Stages Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar IF T IF = 6 units Without pipelining T cyc T IF T T E T E T = E T = 2 units T E = 9 units Pipelined T cyc max{t IF,T,T E,T E,T } = 9 E T E = 5 units Speedup= / 9 EECS 4 T = 9 units Can we do be*er in terms of either performance or efficiency? ecture 4 Slide 8
19 Balancing Pipeline Stages Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Two ethods for Stage Quan]za]on: erging of mul]ple stages Further subdividing a stage Recent Trends: Deeper pipelines (more and more stages) Pipeline depth growing more slowly since Pen]um 4. ul]ple pipelines (subpipelines) Pipelined ory/cache accesses (tricky) EECS 4 ecture 4 Slide 9
20 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar The Cost of Deeper Pipelines ruc]on pipelines are not ideal i.e. ruc:ons in different stages can have dependencies Suppose add 2 nand 4 5 RW!! add nand t t t 2 t t 4 F t D t E t 2 t W t 4 t 5 t 5 F F D D E E Stall W E W F F D D E Stall D W E EECS 4 ecture 4 Slide 2
21 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Types of Dependencies and Hazards Dependence (Both ory and register) True dependence (RW) ruc:on must wait for all required input operands n]-dependence (WR) ater write must not clobber a s:ll-pending earlier read Output dependence (WW) Earlier write must not clobber already-completed later write Control Dependence (aka Procedural Dependence) Condi]onal branches may change instruc]on sequence ruc]ons aker cond. branch depend on outcome (more exact defini:on later) EECS 4 ecture 4 Slide 2
22 Terminology Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Pipeline Hazards: Poten]al viola]ons of program dependences ust ensure program dependences are not violated Hazard Resolu]on: Sta]c ethod: Performed at compiled ]me in sokware Dynamic ethod: Performed at run ]me using hardware Pipeline Interlock: Hardware mechanisms for dynamic hazard resolu]on ust detect and enforce dependences at run ]me EECS 4 ecture 4 Slide 22
23 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Necessary Conditions for Hazards j:r k _ Reg Write j:r k _ Reg Write j:_ r k stage Reg Read Hazard Distance stage Y i:r k _ Reg Write i:_ r k Reg Read i:r k _ Reg Write WW Hazard WR Hazard RW Hazard EECS 4 dist(i,j) dist(,y)?? Hazard!! dist(i,j) > dist(,y)?? Safe ecture 4 Slide 2
24 Handling Hazards Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar voidance (sta]c) ake sure there are no hazards in the code Detect and Stall (dynamic) Stall un]l earlier instruc]ons finish Detect and Forward (dynamic) Get correct value from elsewhere in pipeline EECS 4 ecture 4 Slide 24
25 Handling Hazards: voidance Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Programmer/compiler must know implementa]on details Insert nops between dependent instruc]ons add 2 nop nop nand 4 5 write in cycle 5 read in cycle 6 EECS 4 ecture 4 Slide 25
26 Problems with voidance Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Binary compatability New implementa]ons may require more nops Code size Higher instruc]on cache footprint onger binary load ]mes Worse in machines that execute mul]ple instruc]ons / cycle Intel Itanium 25-4% of instruc]ons are nops Slower execu]on CPI=, but many instruc]ons are nops EECS 4 ecture 4 Slide 26
27 Handling Hazards: Detect & Stall Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Detec]on Compare reg & regb with DestReg of preceding insn. bit comparators Stall Do not advance pipeline register for Fetch/Decode Pass nop to Execute EECS 4 ecture 4 Slide 2
28 Wenisch et al. 26 Fetch Decode Execute emory instruction reg regb R val valb offset target eq? result valb ory result m dest Bits -2 Bits 6-8 Bits dest op dest op dest op / E E/ em em/ 28
29 Wenisch et al. 26 Fetch Decode Execute emory instruction reg regb R val valb offset target eq? result valb ory result m dest dest dest dest op op op / E E/ em em/ 29
30 Wenisch et al. 26 End of Cycle add 2 reg regb R 4 val valb offset target eq? result valb ory result m op op op / E E/ em em/
31 Wenisch et al. 26 End of Cycle 2 nand 4 5 reg regb R 4 4 target eq? result valb ory result m add op op / E E/ em em/
32 Wenisch et al. 26 First half of cycle Hazard detection nand 4 5 reg regb R 4 4 target eq? result valb ory result m add op op / E E/ em em/ 2
33 Wenisch et al. 26 Hazard detected compare compare compare compare reg regb REG file / E
34 Wenisch et al. 26 Hazard detected compare reg regb 4
35 Wenisch et al. 26 First half of cycle en en 2 nand 4 5 Hazard reg regb R 4 4 target eq? result ory result m valb add / E E/ em em/ 5
36 Wenisch et al. 26 End of cycle 2 nand 4 5 reg regb R 4 2 ory result m noop add / E E/ em em/ 6
37 Wenisch et al. 26 First half of cycle 4 en en 2 nand 4 5 Hazard reg regb R 4 2 ory result m noop add / E E/ em em/
38 Wenisch et al. 26 End of cycle 4 2 nand 4 5 reg regb R 4 ory 2 noop noop add / E E/ em em/ 8
39 Wenisch et al. 26 First half of cycle 5 2 nand 4 5 No Hazard reg regb R 4 ory 2 noop noop add / E E/ em em/ 9
40 Wenisch et al. 26 End of cycle 5 add 5 reg regb R ory nand noop noop / E E/ em em/ 4
41 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Problems with Detect & Stall CPI increases on every hazard re these stalls necessary? Not always! The new value for is in the E/em register Reroute the result to the nand Called forwarding or bypassing EECS 4 ecture 4 Slide 4
42 Handling Hazards: Detect & Forward Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Detec]on Same as detect and stall, but each possible hazard requires different forwarding paths Forward dd paths for all possible sources dd mux in front of to select source bypassing logic oken a cri]cal path in wide-issue machines # paths grows quadra]cally with machine width EECS 4 ecture 4 Slide 42
43 Wenisch et al. 26 First half of cycle 2 nand 4 5 Hazard reg regb R ory add fwd fwd fwd / E E/ em em/ 4
44 Wenisch et al. 26 End of cycle add 6 5 reg regb R ory nand add H / E E/ em em/ 44
45 Wenisch et al. 26 First half of cycle 4 add 6 New Hazard 5 reg regb R ory nand add H / E E/ em em/ 45
46 Wenisch et al. 26 End of cycle 4 4 lw 6 reg regb 5 R ory 2 add nand add H2 / E H E/ em em/ 46
47 Wenisch et al. 26 First half of cycle 5 4 lw 6 No Hazard reg regb 5 R ory 2 add nand add H2 / E H E/ em em/ 4
48 Wenisch et al. 26 End of cycle 5 5 sw reg regb 5 R ory -2 lw add nand / E H2 E/ em H em/ 48
49 Wenisch et al. 26 First half of cycle 6 en en 5 sw Hazard 6 reg regb 6 5 R ory -2 lw add nand / E H2 E/ em H em/ 49
50 Wenisch et al. 26 End of cycle 6 5 sw reg regb 6 R ory 22 noop lw add / E E/ em H2 em/ 5
51 Wenisch et al. 26 First half of cycle 5 sw Hazard 6 reg regb 6 R ory 22 noop lw add / E E/ em H2 em/ 5
52 Wenisch et al. 26 End of cycle reg regb 6 R ory 99 sw noop lw H / E E/ em em/ 52
53 Wenisch et al. 26 First half of cycle 8 reg regb 6 R ory 99 sw noop lw H / E E/ em em/ 5
54 Wenisch et al. 26 End of cycle 8 reg regb R ory sw noop / E H E/ em em/ 54
55 oad Delay Slot (IPS ) Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar i: j: k: t t t 2 t t 4 t 5 F D E W F D E W F D E W h: R k -- i: R k E[ - ] j: -- R k k: -- R k - The effect of a delayed oad is not visible to the instructions in its delay slots. Which (R k ) do we really mean? EECS 4 ecture 4 Slide 55
56 Control Hazards Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar beq sub 4 5 beq sub t t t 2 t t 4 t 5 F D E W F D E W squash EECS 4 ecture 4 Slide 56
57 Handling Control Hazards Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar voidance (sta]c) No branches? Convert branches to predica]on Control dependence becomes dependence Detect and Stall (dynamic) Stop fetch un]l branch resolves Speculate and squash (dynamic) Keep going past branch, throw away instruc]ons if wrong EECS 4 ecture 4 Slide 5
58 voidance: if-conversion Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar if (a == b) { x; y = n / d; } sub t a, b jnz t, 2 add x x, # div y n, d sub t a, b add(t) x x, # div(t) y n, d sub t a, b add t2 x, # div t n, d cmov(t) x t2 cmov(t) y t EECS 4 ecture 4 Slide 58
59 Handling Control Hazards: Detect & Stall Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Detec]on In decode, check if opcode is branch or jump Stall Hold next instruc]on in Fetch Pass noop to Decode EECS 4 ecture 4 Slide 59
60 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Problems with Detect & Stall CPI increases on every branch re these stalls necessary? Not always! Branch is only taken half the ]me ssume branch is NOT taken Keep fetching, treat branch as noop If wrong, make sure bad instruc]ons don t complete EECS 4 ecture 4 Slide 6
61 Handling Control Hazards: Speculate & Squash Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Speculate ssume branch is not taken Squash Overwrite opcodes in Fetch, Decode, Execute with noop Pass target to Fetch EECS 4 ecture 4 Slide 6
62 62 Wenisch et al. 26 REG file ory / E E/ em em/ sign ext Control equal beq sub add nand add sub beq beq noop noop noop
63 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Problems with Speculate & Squash lways assumes branch is not taken Can we do bewer? Yes. Predict branch direc]on and target! Why possible? Program behavior repeats. ore on branch predic]on to come... EECS 4 ecture 4 Slide 6
64 Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar Branch Delay Slot (IPS, SPRC) branch: next: target: t t t 2 t t 4 t 5 F D E W F Squash F D E W - ruction in delay slot executes even on taken branch branch: delay: target: F D E W F D E W F D E W i: beq, 2, tgt j: add, 4, 5 What can we put here? EECS 4 ecture 4 Slide 64
65 Pipeline Hazard Checklist Wenisch Portions ustin, Brehob, Falsafi, Hill, Hoe, ipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar emory Dependences Output Dependence (WW) n] Dependence (WR) True Dependence (RW) Register Dependences Output Dependence (WW) n] Dependence (WR) True Dependence (RW) Control Dependences EECS 4 ecture 4 Slide 65
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