CMSC 611: Advanced Computer Architecture

Transcription

1 CMSC 611: Advanced Compute Achitectue Pipelining Some mateial adapted fom Mohamed Younis, UMBC CMSC 611 Sp 2003 couse slides Some mateial adapted fom Hennessy & Patteson / 2003 Elsevie Science

2 Pipeline Hazads Cases that affect instuction execution semantics and thus need to be detected and coected Hazads types Stuctual hazad: attempt to use a esouce two diffeent ways at same time Single memoy fo instuction and data Data hazad: attempt to use item befoe it is eady Instuction depends on esult of pio instuction still in the pipeline Contol hazad: attempt to make a decision befoe condition is evaluated banch instuctions Hazads can always be esolved by waiting

3 Detecting and Resolving Stuctual Hazad Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t. O d e Load Inst 1 Inst 2 Stall Inst 3 Bubble Bubble Bubble Bubble Bubble

4 Stalls & Pipeline Pefomance Aveage instuction time unpipelined Pipelining Speedup = Aveage instuction time pipelined CPI unpipelined = CPI pipelined " Clock cycle unpipelined Clock cycle pipelined Ideal CPI pipelined = 1 CPI pipelined = Ideal CPI+ Pipeline stall cycles pe instuction = 1+ Pipeline stall cycles pe instuction CPI unpipelined Clock cycle unpipelined Speedup = " 1 + Pipeline stall cycles pe instuction Clock cycle pipelined Assuming all pipeline stages ae balanced Speedup = Pipeline depth 1 + Pipeline stall cycles pe instuction

5 Time (clock cycles) Data Hazads IF ID/RF EX MEM WB I n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11

6 Thee Geneic Data Hazads Read Afte Wite (RAW) Inst J ties to ead opeand befoe Inst I wites it I: add 1,2,3 J: sub 4,1,3 Caused by a Data Dependence (in compile nomenclatue). This hazad esults fom an actual need fo communication.

7 Thee Geneic Data Hazads Wite Afte Read (WAR) Inst J wites opeand befoe Inst I eads it I: sub 4,1,3 J: add 1,2,3 K: mul 6,1,7 Called an anti-dependence in compiles. This esults fom euse of the name 1. Can t happen in MIPS 5 stage pipeline because: All instuctions take 5 stages, and Reads ae always in stage 2, and Wites ae always in stage 5

8 Thee Geneic Data Hazads Wite Afte Wite (WAW) Inst J wites opeand befoe Inst I wites it. I: mul 1,4,3 J: add 1,2,3 K: sub 6,1,7 Called an output dependence in compiles This also esults fom the euse of name 1. Can t happen in MIPS 5 stage pipeline: All instuctions take 5 stages, and Wites ae always in stage 5 Do see WAR and WAW in moe complicated pipes

9 Fowading to Avoid Data Hazad Time (clock cycles) I n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11

10 HW Change fo Fowading NextPC istes ID/EX mux mux EX/MEM Data Memoy MEM/WR Immediate mux

11 Data Hazad Even with Fowading Time (clock cycles) I n s t. lw 1, 0(2) sub 4,1,6 O d e and 6,1,7 o 8,1,9

12 Resolving Load Hazads Adding hadwae? How? Whee? Detection? Compilation techniques? What is the cost of load delays?

13 Resolving the Load Data Hazad Time (clock cycles) I n s t. O d e lw 1, 0(2) sub 4,1,6 and 6,1,7 Bubble Bubble o 8,1,9 Bubble How is this diffeent fom the instuction issue stall?

14 Softwae Scheduling to Avoid Load Hazads Ty poducing fast code fo a = b + c; d = e f; assuming a, b, c, d,e, and f in memoy. Slow code: LW Rb,b Fast code: LW Rb,b LW Rc,c LW Rc,c LW Re,e ADD Ra,Rb,Rc ADD Ra,Rb,Rc SW a,ra LW Rf,f LW Re,e SW a,ra LW Rf,f SUB Rd,Re,Rf SW d,rd SUB Rd,Re,Rf SW d,rd

15 Instuction Set Connection What is exposed about this oganizational hazad in the instuction set? k cycle delay? bad, CPI is not pat of ISA k instuction slot delay load should not be followed by use of the value in the next k instuctions Nothing, but code can educe un-time delays MIPS did the tansfomation in the assemble