Precision, Dual-Channel, JFET Input, Rail-to-Rail Instrumentation Amplifier AD8224

Transcription

1 Precision, Dual-Channel, JFET Input, Rail-to-Rail Instrumentation Amplifier FEATURES Two channels in a small 4 mm 4 mm LFCSP Low input currents pa maximum input bias current (B Grade).6 pa maximum input offset current (B Grade) High CMRR db CMRR (minimum), G = (B Grade) 9 db CMRR (minimum) to khz, G = (B Grade) Excellent ac specifications and low power.5 MHz bandwidth (G = ) 4 nv/ Hz input noise ( khz) Slew rate: 2 V/μs 75 μa quiescent current per amplifier Versatility Rail-to-rail output Input voltage range to below negative supply rail 4 kv ESD protection 4.5 V to 36 V single supply ±2.25 V to ±8 V dual supply Gain set with single resistor (G = to ) APPLICATIONS Medical instrumentation Precision data acquisition Transducer interfaces Differential drives for high resolution input ADCs Remote sensors GENERAL DESCRIPTION The is the first single-supply, JFET input instrumentation amplifier available in the space-saving 6-lead, 4 mm 4 mm LFCSP. It requires the same board area as a typical single instrumentation amplifier yet doubles the channel density and offers a lower cost per channel without compromising performance. Designed to meet the needs of high performance, portable instrumentation, the has a minimum common-mode rejection ratio (CMRR) of 86 db at dc and a minimum CMRR of 8 db at khz for G =. Maximum input bias current is pa and typically remains below 3 pa over the entire industrial temperature range. Despite the JFET inputs, the typically has a noise corner of only Hz. With the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. FUNCTIONAL BLOCK DIAGRAM IN R G 2 R G 3 +IN 4 +V S OUT OUT V S REF REF2 Figure. 2 IN2 R G2 R G2 9 +IN2 Table. In Amps and Difference Amplifiers by Category High Perform Low Cost High Voltage Mil Grade Low Power Digital Gain AD822 AD8553 AD628 AD62 AD627 AD823 AD822 AD623 AD629 AD62 AD825 AD8222 AD524 AD825 AD526 AD8555 AD624 AD8556 AD8557 Rail-to-rail output. Designed to alleviate this problem, the can operate on a ±8 V dual supply, as well as on a single +5 V supply. The device s rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need for higher voltage, dual supplies. The draws 75 μa of quiescent current per amplifier, making it ideal for battery powered devices. In addition, the can be configured as a single-channel, differential output, instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input ADCs. For a single-channel version, use the AD822. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 9 Thermal Resistance... 9 ESD Caution... 9 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Theory of Operation... 2 Gain Selection... 2 Layout... 2 Solder Wash Input Bias Current Return Path Input Protection RF Interference Common-Mode Input Voltage Range Applications Information Driving an ADC Differential Output Driving a Differential Input ADC Driving Cabling Outline Dimensions Ordering Guide Reference Terminal... 2 REVISION HISTORY 4/7 Rev. to Rev. A Changes to Features, General Description, and Figure... Changes to Table Changes to Table 3 and Table Changes to Table Changes to Table 6 and Table Changes to Figure Changes to Figure 3... Inserted Figure 4, Figure 5, and Figure 6; Renumbered Sequentially... Changes to Figure 7... Changes to Figure 2 and Figure Changes to Figure Changes to Theory of Operation and Figure Changes to Ordering Guide /7 Revision : Initial Version Rev. A Page 2 of 28

3 SPECIFICATIONS VS+ = +5 V, VS = 5 V, VREF = V, TA = 25 C, G =, RL = 2 kω, unless otherwise noted. Table 2 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 62. Table 2. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration 2, VS = ±5 V A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 6 Hz with VCM = ± V kω Source Imbalance G = db G = 94 db G = 94 db G = 94 db CMRR at khz VCM = ± V G = 74 8 db G = 84 9 db G = 84 9 db G = 84 9 db NOISE RTI noise = (eni 2 + (eno/g) 2 ) Voltage Noise, khz Input Voltage Noise, eni VIN+, VIN = V nv/ Hz Output Voltage Noise, eno VIN+, VIN = V 9 9 nv/ Hz RTI,. Hz to Hz G = 5 5 μv p-p G =.8.8 μv p-p Current Noise f = khz fa/ Hz VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G) Input Offset, VOSI 3 75 μv Average TC T = 4 C to +85 C 5 μv/ C Output Offset, VOSO 2 8 μv Average TC T = 4 C to +85 C 5 μv/ C Offset RTI vs. Supply (PSR) VS = ±5 V to ±5 V G = db G = 96 db G = 96 db G = 96 db INPUT CURRENT (PER CHANNEL) Input Bias Current 25 pa Over Temperature 3 T = 4 C to +85 C 3 3 pa Input Offset Current 2.6 pa Over Temperature 3 T = 4 C to +85 C 5 5 pa REFERENCE INPUT RIN 4 4 kω IIN VIN+, VIN = V 7 7 μa Voltage Range VS +VS VS +VS V Gain to Output ±. ±. V/V Rev. A Page 3 of 28

4 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit GAIN G = + (49.4 kω/rg) Gain Range V/V Gain Error VOUT = ± V G =.6.4 % G =.3.2 % G =.3.2 % G =.3.2 % Gain Nonlinearity VOUT = V to + V G = RL = kω ppm G = RL = kω 5 5 ppm G = RL = kω ppm G = RL = kω 5 5 ppm G = RL = 2 kω ppm G = RL = 2 kω ppm G = RL = 2 kω ppm G= RL = 2 kω ppm Gain vs. Temperature G = ppm/ C G > 5 5 ppm/ C INPUT Impedance (Pin to Ground) GΩ pf Input Operating Voltage Range 5 VS = ±2.25 V to ±8 V VS. +VS 2 VS. +VS 2 V for dual supplies Over Temperature T = 4 C to +85 C VS. +VS 2. VS. +VS 2. V OUTPUT Output Swing RL = 2 kω V Over Temperature T = 4 C to +85 C V Output Swing RL = kω V Over Temperature T = 4 C to +85 C V Short-Circuit Current 5 5 ma POWER SUPPLY (PER AMPLIFIER) Operating Range ± ±8 ± ±8 V Quiescent Current μa Over Temperature T = 4 C to +85 C μa TEMPERATURE RANGE For Specified Performance C Operational C When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. 2 Refers to the differential configuration shown in Figure Refer to Figure 4 and Figure 5 for the relationship between input current and temperature. 4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 The can operate up to a diode drop below the negative supply; however, the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. 7 The is characterized from 4 C to +25 C. See the Typical Performance Characteristics section for expected operation in this temperature range. Rev. A Page 4 of 28

5 VS+ = +5 V, VS = 5 V, VREF = V, TA = 25 C, G =, RL = 2 kω, unless otherwise noted. Table 3 displays the specifications for the dynamic performance of each individual instrumentation amplifier. Table 3. Dynamic Performance of Each Individual Amplifier Single-Ended Output Configuration, VS = ±5 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth 3 db G = 5 5 khz G = 8 8 khz G = 2 2 khz G = 4 4 khz Settling Time.% ΔVO = ± V step G = 5 5 μs G = μs G = μs G = μs Settling Time.% ΔVO = ± V step G = 6 6 μs G = μs G = μs G = μs Slew Rate G = to 2 2 V/μs When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. VS+ = +5 V, VS = 5 V, VREF = V, TA = 25 C, G =, RL = 2 kω, unless otherwise noted. Table 4 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 62. Table 4. Dynamic Performance of Both Amplifiers Differential Output Configuration 2, VS = ±5 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth 3 db G = 5 5 khz G = 8 8 khz G = 2 2 khz G = 4 4 khz Settling Time.% ΔVO = ± V step G = 5 5 μs G = μs G = μs G = μs Settling Time.% ΔVO = ± V step G = 6 6 μs G = μs G = μs G = μs Slew Rate G = to 2 2 V/μs When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. 2 Refers to the differential configuration shown in Figure 62. Rev. A Page 5 of 28

6 VS + = 5 V, VS = V, VREF = 2.5 V, TA = 25 C, G =, RL = 2 kω, unless otherwise noted. Table 5 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 62. Table 5. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration 2, VS =+5 V A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 6 Hz with VCM = to 2.5 V kω Source Imbalance G = db G = 94 db G = 94 db G = 94 db CMRR at khz G = 74 8 db G = 84 9 db G = 84 9 db G = 84 9 db NOISE RTI noise = (eni 2 + (eno/g) 2 ) Voltage Noise, khz VS = ±2.5 V Input Voltage Noise, eni VIN+, VIN = V, VREF = V nv/ Hz Output Voltage Noise, eno VIN+, VIN = V, VREF = V 9 9 nv/ Hz RTI,. Hz to Hz G = 5 5 μv p-p G =.8.8 μv p-p Current Noise f = khz fa/ Hz VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G) Input Offset, VOSI 3 25 μv Average TC T = 4 C to +85 C 5 μv/ C Output Offset, VOSO 2 8 μv Average TC T = 4 C to +85 C 5 μv/ C Offset RTI vs. Supply (PSR) G = db G = 96 db G = 96 db G = 96 db INPUT CURRENT (PER CHANNEL) Input Bias Current 25 pa Over Temperature 3 T = 4 C to +85 C 3 3 pa Input Offset Current 2.6 pa Over Temperature 3 T = 4 C to +85 C 5 5 pa REFERENCE INPUT RIN 4 4 kω IIN VIN+, VIN = V 7 7 μa Voltage Range VS +VS VS +VS V Gain to Output ±. ±. V/V Rev. A Page 6 of 28

7 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit GAIN G = + (49.4 kω/rg) Gain Range V/V Gain Error G = VOUT =.3 V to 2.9 V.6.4 % G = VOUT =.3 V to 3.8 V.3.2 % G = VOUT =.3 V to 3.8 V.3.2 % G = VOUT =.3 V to 3.8 V.3.2 % Nonlinearity VOUT =.3 V to 2.9 V for G = VOUT =.3 V to 3.8 V for G > G = RL = kω ppm G = RL = kω ppm G = RL = kω ppm G = RL = kω ppm G = RL = 2 kω ppm G = RL = 2 kω ppm G = RL = 2 kω ppm G = RL = 2 kω ppm Gain vs. Temperature G = ppm/ C G > 5 5 ppm/ C INPUT Impedance (Pin to Ground) GΩ pf Input Voltage Range 5. +VS 2. +VS 2 V Over Temperature T = 4 C to +85 C. +VS 2.. +VS 2. V OUTPUT Output Swing RL = 2 kω V Over Temperature T = 4 C to +85 C V Output Swing RL = kω V Over Temperature T = 4 C to +85 C V Short-Circuit Current 5 5 ma POWER SUPPLY (PER AMPLIFIER) Operating Range V Quiescent Current μa Over Temperature T = 4 C to +85 C μa TEMPERATURE RANGE For Specified Performance C Operational C When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. 2 Refers to the differential configuration shown in Figure Refer to Figure 4 and Figure 5 for the relationship between input current and temperature. 4 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 The can operate up to a diode drop below the negative supply, but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 The is characterized from 4 C to +25 C. See the Typical Performance Characteristics section for expected operation in that temperature range. Rev. A Page 7 of 28

8 VS + = 5 V, VS = V, VREF = 2.5 V, TA = 25 C, G =, RL = 2 kω, unless otherwise noted. Table 6 displays the specifications for the dynamic performance of each individual instrumentation amplifier. Table 6. Dynamic Performance of Each Individual Amplifier Single-Ended Output Configuration, VS = +5 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth 3 db G = 5 5 khz G = 8 8 khz G = 2 2 khz G = 4 4 khz Settling Time.% G = ΔVO = 3 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step 6 6 μs Settling Time.% G = ΔVO = 3 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs Slew Rate G = to 2 2 V/μs When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. VS + = 5 V, VS = V, VREF = 2.5 V, TA = 25 C, G =, RL = 2 kω unless otherwise noted. Table 7 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 62. Table 7. Dynamic Performance of Both Amplifiers Differential Output Configuration 2, VS = +5 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth 3 db G = 5 5 khz G = 8 8 khz G = 2 2 khz G = 4 4 khz Settling Time.% G = ΔVO = 3 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step 6 6 μs Settling Time.% G = ΔVO = 3 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs G = ΔVO = 4 V step μs Slew Rate G = to 2 2 V/μs When the output sinks more than 4 ma, use a 47 pf capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as kω. 2 Refers to the differential configuration shown in Figure 62. Rev. A Page 8 of 28

9 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Supply Voltage ±8 V Power Dissipation See Figure 2 Output Short-Circuit Current Indefinite Input Voltage (Common Mode) ±VS Differential Input Voltage ±VS Storage Temperature Range 65 C to +3 C Operating Temperature Range 2 4 C to +25 C Lead Temperature (Soldering, sec) 3 C Junction Temperature 3 C Package Glass Transition Temperature 3 C ESD (Human Body Model) 4 kv ESD (Charge Device Model) kv ESD (Machine Model).4 kv Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Assumes the load is referenced to midsupply. 2 Temperature for specified performance is 4 C to +85 C. For performance to 25 C, see the Typical Performance Characteristics section. THERMAL RESISTANCE Table 9. Thermal Pad θja Unit Soldered to Board 48 C/W Not Soldered to Board 86 C/W The θja values in Table 9 assume a 4-layer JEDEC standard board. If the thermal pad is soldered to the board, it is also assumed it is connected to a plane. θjc at the exposed pad is 4.4 C/W. Maximum Power Dissipation The maximum safe power dissipation for the is limited by the associated rise in junction temperature (TJ) on the die. At approximately 3 C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 3 C for an extended period can result in a loss of functionality. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP on a 4-layer JEDEC standard board. 4. MAXIMUM POWER DISSIPATION (W) θ JA = 86 C/W WHEN THERMAL PAD IS NOT SOLDERED TO BOARD θ JA = 48 C/W WHEN THERMAL PAD IS SOLDERED TO BOARD AMBIENT TEMPERATURE ( C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. A Page 9 of 28

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V S OUT OUT2 IN R G 2 R G 3 +IN 4 PIN INDICATOR TOP VIEW 2 IN2 R G2 R G2 9 +IN2 +V S 5 REF 6 REF2 7 8 Figure 3. Pin Configuration Table. Pin Function Descriptions Pin Number Mnemonic Description IN Negative Input Instrumentation Amplifier (In-Amp) 2 RG Gain Resistor In-Amp 3 RG Gain Resistor In-Amp 4 +IN Positive Input In-Amp 5 +VS Positive Supply 6 REF Reference Adjust In-Amp 7 REF2 Reference Adjust In-Amp 2 8 VS Negative Supply 9 +IN2 Positive Input In-Amp 2 RG2 Gain Resistor In-Amp 2 RG2 Gain Resistor In-Amp 2 2 IN2 Negative Input In-Amp 2 3 VS Negative Supply 4 OUT2 Output In-Amp 2 5 OUT Output In-Amp 6 +VS Positive Supply Rev. A Page of 28

11 TYPICAL PERFORMANCE CHARACTERISTICS 25 C, VS = ±5 V, RL = kω, unless otherwise noted. 4 NUMBER OF UNITS VOLTAGE NOISE RTI (nv/ Hz) GAIN = BANDWIDTH ROLL-OFF GAIN = GAIN = GAIN = /GAIN = GAIN = BANDWIDTH ROLL-OFF CMRR (µv/v) k k k FREQUENCY (Hz) Figure 4. Typical Distribution of CMRR (G = ) Figure 7. Voltage Spectral Density vs. Frequency 4 35 NUMBER OF UNITS X (X) V OSI (µv) µV/DIV X (X) s/div Figure 5. Typical Distribution of Input Offset Voltage Figure 8.. Hz to Hz RTI Voltage Noise (G = ) 4 NUMBER OF UNITS 3 2 X (X) V OSO (µv) µv/div X (X) s/div Figure 6. Typical Distribution of Output Offset Voltage Figure 9.. Hz to Hz RTI Voltage Noise (G = ) Rev. A Page of 28

12 DELTA V OSI (µv) INPUT BIAS CURRENT (pa) INPUT OFFSET CURRENT ±5 5.V 5.V INPUT OFFSET CURRENT ±5 INPUT BIAS CURRENT ±5 INPUT BIAS CURRENT ± INPUT OFFSET CURRENT (pa).5. TIME (s) Figure. Change in Input Offset Voltage vs. Warmup Time COMMON-MODE VOLTAGE (V) Figure 3. Input Bias Current and Input Offset Current vs. Common-Mode Voltage GAIN = n PSRR (db) GAIN = GAIN = GAIN = BANDWIDTH LIMITED INPUT BIAS CURRENT (A) n p p p I BIAS I OS 3.p k k k M FREQUENCY (Hz) Figure. Positive PSRR vs. Frequency, RTI TEMPERATURE ( C) Figure 4. Input Bias Current and Offset Current vs. Temperature, VS = ±5 V, VREF = V n PSRR (db) GAIN = GAIN = GAIN = CURRENT (A) n p p p I BIAS I OS 3 GAIN =.p k k k M FREQUENCY (Hz) Figure 2. Negative PSRR vs. Frequency, RTI TEMPERATURE ( C) Figure 5. Input Bias Current and Offset Current vs. Temperature, VS = 5 V, VREF = 2.5 V Rev. A Page 2 of 28

13 6 7 4 GAIN = 6 5 GAIN = CMRR (db) 2 8 GAIN = GAIN = GAIN = BANDWIDTH LIMITED GAIN (db) GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure 6. CMRR vs. Frequency k k k M M FREQUENCY (Hz) Figure 9. Gain vs. Frequency GAIN = CMRR (db) 2 8 GAIN = GAIN = GAIN = BANDWIDTH LIMITED X NONLINEARITY (ppm/div) R LOAD = kω R LOAD = 2kΩ 6 4 FREQUENCY (Hz) Figure 7. CMRR vs. Frequency, kω Source Imbalance V S = ±5V OUTPUT VOLTAGE (V) Figure 2. Gain Nonlinearity, G = CMRR (µv/v) X NONLINEARITY (ppm/div) R LOAD = kω R LOAD = 2kΩ TEMPERATURE ( C) Figure 8. Change in CMRR vs. Temperature, G = V S = ±5V OUTPUT VOLTAGE (V) Figure 2. Gain Nonlinearity, G = Rev. A Page 3 of 28

14 4 X NONLINEARITY (2ppm/DIV) V S = ±5V R LOAD = kω OUTPUT VOLTAGE (V) R LOAD = 2kΩ Figure 22. Gain Nonlinearity, G = INPUT COMMON-MODE VOLTAGE (V) V, +.7V +.V, +.5V +3V +5V SINGLE SUPPLY, V REF = +2.5V.3V OUTPUT VOLTAGE (V) +4.9V, +.7V +4.9V, +.5V Figure 25. Input Common-Mode Voltage Range vs. Output Voltage, G =, VS = 5 V, VREF = 2.5 V X NONLINEARITY (ppm/div) R LOAD = 2kΩ R LOAD = kω V S = ±5V OUTPUT VOLTAGE (V) Figure 23. Gain Nonlinearity, G = INPUT COMMON-MODE VOLTAGE (V) ±5V SUPPLIES 4.9V, +5.4V 4.9V, +.4V 4.9V, 4.V 4.8V, 9V +3V +3V ±5V SUPPLIES 5.3V 5.3V OUTPUT VOLTAGE (V) +4.9V, +5.4V +4.9V, +.5V +4.9V, 4.V +4.9V, 9V Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G =, VREF = V INPUT COMMON-MODE VOLTAGE (V) ±5V SUPPLIES 4.8V, +5.5V 4.8V, +.6V 4.8V, 3.3V 4.8V, 8.3V +3V +3V ±5V SUPPLIES 5.3V 5.3V OUTPUT VOLTAGE (V) +4.9V, +5.5V +4.95V, +.6V +4.95V, 3.3V +4.9V, 8.3V Figure 24. Input Common-Mode Voltage Range vs. Output Voltage, G =, VREF = V INPUT COMMON-MODE VOLTAGE (V) V, +.7V +.V,.5V +3V +5V SINGLE SUPPLY, V REF = +2.5V.3V OUTPUT VOLTAGE (V) +4.9V, +.7V +4.9V,.5V Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G =, VS = 5 V, VREF = 2.5 V Rev. A Page 4 of 28

15 V S + 5 INPUT VOLTAGE LIMIT (V) 2 + V S 4 C +25 C +25 C +85 C NOTES. THE CAN OPERATE UP TO A V BE BELOW THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. 4 C +25 C +85 C +25 C OUTPUT VOLTAGE SWING (V) C +25 C +25 C 4 C +85 C +25 C +25 C +85 C SUPPLY VOLTAGE (V) Figure 28. Input Voltage Limit vs. Supply Voltage, G =, VREF = V k k R LOAD (Ω) Figure 3. Output Voltage Swing vs. Load Resistance, VS = ±5 V, VREF = V V S + 5 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES C +25 C +25 C +85 C +25 C +85 C +25 C 4 C OUTPUT VOLTAGE SWING (V) C +25 C +25 C 4 C +25 C +25 C +85 C +85 C V S DUAL SUPPLY VOLTAGE (±V) Figure 29. Output Voltage Swing vs. Dual Supply Voltage, RLOAD = 2 kω, G =, VREF = V V S k k R LOAD (Ω) Figure 32. Output Voltage Swing vs. Load Resistance, VS = 5 V, VREF = 2.5 V V S OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES C +85 C +25 C 4 C +25 C +85 C +25 C 4 C OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES C 4 C +85 C +25 C +25 C +85 C +25 C +.2 V S DUAL SUPPLY VOLTAGE (±V) Figure 3. Output Voltage Swing vs. Dual Supply Voltage, RLOAD = kω, G =, VREF = V C V S I OUT (ma) Figure 33. Output Voltage Swing vs. Output Current, VS = ±5 V, VREF = V Rev. A Page 5 of 28

16 V S + 35 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES C +85 C +25 C +25 C +85 C +25 C 4 C OUTPUT VOLTAGE SWING (V p-p) GAIN =,, GAIN = V S I OUT (ma) Figure 34. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V k k k M M FREQUENCY (Hz) Figure 37. Output Voltage Swing vs. Large Signal Frequency Response NO LOAD 47pF pf 5V/DIV X (X) 2mV/DIV 5µs/DIV X (X) Figure 35. Small Signal Pulse Response for Various Capacitive Loads, VS = ±5 V, VREF = V NO LOAD 47pF pf X (X) X (X).2%/DIV 5µs TO.% 6µs TO.% 2µs/DIV X (X) Figure 38. Large Signal Pulse Response and Settle Time, G =, RLOAD = kω, VS = ±5 V, VREF = V V/DIV X (X).2%/DIV 4.3μs TO.% 4.6μs TO.% 2mV/DIV 5µs/DIV X (X) Figure 36. Small Signal Pulse Response for Various Capacitive Loads, VS = 5 V, VREF = 2.5 V µs/DIV X (X) Figure 39. Large Signal Pulse Response and Settle Time, G =, RLOAD = kω, VS = ±5 V, VREF = V Rev. A Page 6 of 28

17 5V/DIV X (X).2%/DIV 8.μs TO.% 9.6μs TO.% X (X) 2µs/DIV Figure 4. Large Signal Pulse Response and Settle Time, G =, RLOAD = kω, VS = ±5 V, VREF = V V/DIV X (X).2%/DIV 58μs TO.% 74μs TO.% X (X) 2µs/DIV Figure 4. Large Signal Pulse Response and Settle Time, G =, RLOAD = kω, VS = ±5 V, VREF = V X X 2mV/DIV X 4µs/DIV Figure 43. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = ±5 V, VREF = V X 2mV/DIV X 4µs/DIV Figure 44. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = ±5 V, VREF = V X 2mV/DIV 2mV/DIV X Figure 42. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = ±5 V, VREF = V 4µs/DIV X 4µs/DIV Figure 45. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = ±5 V, VREF = V Rev. A Page 7 of 28

18 X X 2mV/DIV 2mV/DIV X Figure 46. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = 5 V, VREF = 2.5 V 4µs/DIV X 4µs/DIV Figure 49. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = 5 V, VREF = 2.5 V X 2mV/DIV SETTLING TIME (µs) 5 SETTLED TO.% SETTLED TO.% X 4µs/DIV Figure 47. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = 5 V, VREF = 2.5 V OUTPUT VOLTAGE STEP SIZE (V) Figure 5. Settling Time vs. Output Voltage Step Size, (G = ) ±5 V, VREF = V X 2mV/DIV SETTLING TIME (µs) SETTLED TO.% SETTLED TO.% X 4µs/DIV Figure 48. Small Signal Pulse Response, G =, RLOAD = 2 kω, CLOAD = pf, VS = 5 V, VREF = 2.5 V GAIN (V/V) Figure 5. Settling Time vs. Gain for a V Step, VS = ±5 V, VREF = V Rev. A Page 8 of 28

19 CHANNEL SEPARATION (db) SOURCE V OUT = 2V p-p THERMAL CROSSTALK VARIES WITH LOAD GAIN = GAIN = SOURCE V OUT SMALLER TO AVOID SLEW RATE LIMIT CMR OUT (db) LIMITED BY MEASUREMENT SYSTEM CMR OUT = 2 log V DIFF_OUT V CM_OUT 4 k k k M FREQUENCY (Hz) Figure 52. Channel Separation vs. Frequency, RLOAD = 2 kω, Source Channel at G = k k k M FREQUENCY (Hz) Figure 54. Differential Output Configuration: Common-Mode Output (CMROUT) vs. Frequency GAIN = 4 GAIN (db) 2 GAIN = GAIN = GAIN = 2 4 k k k M M FREQUENCY (Hz) Figure 53. Differential Output Configuration: Gain vs. Frequency Rev. A Page 9 of 28

20 THEORY OF OPERATION +V S +V S +V S +V S NODE A R G NODE B 2kΩ R 24.7kΩ R2 24.7kΩ 2kΩ 2kΩ NODE F A3 +V S OUTPUT +V S +V S NODE C NODE D NODE E +V S +IN J Q C C2 Q2 J2 IN 2kΩ REF V PINCH A A2 V PINCH I VB I Figure 55. Simplified Schematic The is a JFET input, monolithic instrumentation amplifier based on the classic three op amp topology (see Figure 55). Input Transistor J and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A and A2 to change accordingly. The input signal creates a current through RG that flows in R and R2 such that the outputs of A and A2 provide the correct, gained signal. Topologically, J, A, and R and J2, A2, and R2 can be viewed as precision current feedback amplifiers with a gain bandwidth of.5 MHz. The common-mode voltage and amplified differential signal from A and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 2 kω laser trimmed resistors that result in an in-amp with a gain error of less than.4%. New trim techniques were developed to ensure that the CMRR exceeds 86 db (G = ). Using JFET transistors, the offers an extremely high input impedance, extremely low bias currents of pa maximum, low offset current of.6 pa maximum, and no input bias current noise. In addition, input offset is less than 75 μv and drift is less than 5 μv/ C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result, and the output can undergo phase reversal. Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of, driving the amplifier with V on ±5 V constitutes overdriving the inputs because the amplifier cannot output V. The has none of these problems; its input bias current is limited to less than μa, and the output does not phase reverse under overdrive fault conditions. The has extremely low load induced nonlinearity. All amplifiers that comprise the have rail-to-rail output capability for enhanced dynamic range. The input of the can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual ±2.25 V to ±8 V. The transfer function of the is 49.4 kω G = + R G Users can easily and accurately set the gain using a single, standard resistor. Because the input amplifiers employ a current feedback architecture, the gain bandwidth product increases with gain, resulting in a system that does not experience as much bandwidth loss as voltage feedback architectures at higher gains. GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the. This is calculated by referring to Table or by using the following gain equation R G 49.4 kω = G Rev. A Page 2 of 28

21 Table. Gains Achieved Using % Resistors % Standard Table Value of RG (Ω) Calculated Gain 49.9 k k k k k The defaults to G = when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum. REFERENCE TERMINAL The output voltage of the is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin or the REF2 pin to level-shift the output so that the can drive a single-supply ADC. Pin REFx is protected with ESD diodes and should not exceed either +VS or VS by more than.5 V. For best performance, source impedance to the REF terminal should be kept below Ω. As shown in Figure 55, the reference terminal, REF, is at one end of a 2 kω resistor. Additional impedance at the REF terminal adds to this 2 kω resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by ( 2 kω + R ) 2 4 kω + R REF REF Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT CORRECT CORRECT LAYOUT The is a high precision device. To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. The pinout is arranged in a logical manner to aid in this task. Package Considerations The is available in a 6-lead, 4 mm 4 mm LFCSP. Blindly copying the footprint from another 4 mm 4 mm LFCSP part is not recommended because it may not have the same thermal pad size and leads. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. Space between the leads and thermal pad should be kept as wide as possible for the best bias current performance. To maintain the ultralow bias current performance, the thermal pad area can be reduced to extend the gap between the leads and the pad. Thermal Pad The 4 mm 4 mm LFCSP comes with a thermal pad. This pad is connected internally to +VS. The pad can either be left unconnected or connected to the positive supply rail. To preserve maximum pin compatibility with other dual instrumentation amplifiers, such as the AD8222, leave the pad unconnected. This can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Because the dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the thermal pad to the positive supply rail. For the best heat dissipation performance, the positive supply rail should be a plane in the board. See the Thermal Resistance section for more information. Common-Mode Rejection over Frequency The has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. V REF V REF V REF + + OP277 Figure 56. Driving the Reference Pin Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. Reference Errors introduced at the reference terminal feed directly to the output. Take care to tie the REFx pins to the appropriate local ground. Rev. A Page 2 of 28

22 Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The has two positive supply pins (Pin 5 and Pin 6) and two negative supply pins (Pin 8 and Pin 3). While the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. The should be decoupled with. μf bypass capacitors, one for each supply. Place the positive supply decoupling capacitor near Pin 6, and the negative supply decoupling capacitor near Pin 8. Each supply should also be decoupled with a μf tantalum capacitor. The tantalum capacitor can be placed further away from the and can generally be shared by other precision integrated circuits. Figure 57 shows an example layout..µf SOLDER WASH The solder process can leave flux and other contaminants on the board. When these contaminants are between the leads and thermal pad, they can create leakage paths that are larger than the bias currents. A thorough washing process removes these contaminants and restores the device s excellent bias current performance. INPUT BIAS CURRENT RETURN PATH The input bias current of the must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created, as shown in Figure 58. INPUT PROTECTION All terminals of the are protected against ESD. ESD protection is guaranteed to 4 kv (human body model). In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the safely handles a continuous 6 ma current at room temperature. R G R G For applications where the encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV99Ls, FJHs, or SP72s, should be used. INCORRECT CORRECT 3 +V S +V S REF REF.µF TRANSFORMER TRANSFORMER Figure 57. Example Layout C +V S C +V S C REF f HIGH-PASS = 2πRC C R REF R CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 58. Creating an IBIAS Path Rev. A Page 22 of 28

23 RF INTERFERENCE RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The by its nature has a 5 pf gate capacitance (CG) at its inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 59). The relationship between external, matched series resistors and the internal gate capacitance is expressed as FilterFreqDIFF = 2 πrc FilterFreq CM R R = 2 πrc +IN IN G G +5V.µF µf C G C G REF.µF µf V OUT 5V Figure 59. RFI Filtering Without External Capacitors Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than times CC. This sets the differential filter frequency lower than the common-mode frequency. R 4.2kΩ R 4.2kΩ C C C D C C nf nf nf.µf +IN IN +5V REF µf.µf µf 5V Figure 6. RFI Suppression + V OUT COMMON-MODE INPUT VOLTAGE RANGE The 3-op amp architecture of the applies gain and then removes the common-mode voltage. Therefore, internal nodes in the experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 24 through Figure 27 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass RC network can be placed at the input of the instrumentation amplifier (see Figure 6). The filter limits the input signal bandwidth according to the following relationship: FilterFreqDIFF = 2πR(2 CD + CC + C ) FilterFreq CM = 2πR( CC + C G ) G Rev. A Page 23 of 28

24 APPLICATIONS INFORMATION DRIVING AN ADC An instrumentation amplifier is often used in front of an ADC to provide CMRR and additional conditioning such as a voltage level shift and gain (see Figure 6). In this example, a 2.7 nf capacitor and a 5 Ω resistor create an antialiasing filter for the AD7685. The 2.7 nf capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the ADC. The 5 Ω series resistor reduces the burden of the 2.7 nf load from the amplifier. However, large source impedance in front of the ADC can degrade the total harmonic distortion (THD). For applications where THD performance is critical, the series resistor needs to be small. At worst, a small series resistor can load the, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the AD865 should be used after the to drive the ADC. ±5mV µf +.7kΩ.µF +IN IN +5V REF +2.5V 5Ω 2.7nF AD7685 ADR435 Figure 6. Driving an ADC in a Low Frequency Application DIFFERENTIAL OUTPUT The differential configuration of the has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to MHz. +5V 4.7µF The circuit configuration, outlined in Table 4 and Table 7, refers to the configuration shown in Figure 62 only. The circuit includes an RC filter that maintains the stability of the loop. The transfer function for the differential output is VDIFF_OUT = V+OUT V OUT = (V+IN V IN) G where: 49.4 kω G = + RG IN R G IN + + 2kΩ 33pF +OUT +IN2 REF2 OUT Figure 62. Differential Circuit Schematic Setting the Common-Mode Voltage The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is VCM_OUT = (V+OUT + V OUT)/2 = (V+IN2 + VREF2)/2 +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the positive supply rail. REF2 must be driven with a low impedance but can go 3 mv beyond the supply rails. A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a commonmode output voltage of half the ADC reference voltage. 2-Channel Differential Output Using a Dual Op Amp Another differential output topology is shown in Figure 63. Instead of a second in-amp, ½ of a dual OP277 op amp creates the inverted output. Because the OP277 comes in an MSOP, this configuration allows the creation of a dual-channel, precision differential output in-amp with little board area. Errors from the op amp are common to both outputs and are, thus, common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they are likely to be rejected by the next device in the signal chain. +IN IN REF 4.99kΩ V REF +OUT kΩ + OP277 OUT Figure 63. Differential Output Using Op Amp Rev. A Page 24 of 28

25 +2V µf +.µf +5V +IN IN kω kω pf NPO 5% pf pf NPO 5% +OUT (DIFF OUT) OUT +IN2 REF2 +5V REF 86Ω 86Ω 2.7nF 2.7nF IN+ IN +2V VDD AD7688 GND µf X5R.µF REF µf +.µf 2V.µF V IN VOUT ADR435 GND.µF +5V REF Figure 64. Driving a Differential ADC DRIVING A DIFFERENTIAL INPUT ADC The can be configured in differential output mode to drive a differential ADC. Figure 64 illustrates several of the concepts. First Antialiasing Filter The kω resistor, pf capacitor, and pf capacitors in front of the in-amp form a 76 khz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. The pf capacitors protect against commonmode RFI signals. Note that they are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the CMRR of the system high over frequency. Second Antialiasing Filter An 86 Ω resistor and a 2.7 nf capacitor are located between each output and ADC input. These components create a 73 khz low-pass filter for another stage of antialiasing protection. These four elements also isolate the ADC from loading the. The 86 Ω resistor shields the from the switched capacitor input of the ADC, which looks like a timevarying load. The 2.7 nf capacitor provides a charge to the switched capacitor front end of the ADC. If the application requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. However, other converters have less robust inputs and may need the added protection. Reference The ADR435 supplies a reference voltage to both the ADC and the. Because REF2 on the is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC. DRIVING CABLING All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the output response. To reduce peaking, use a resistor between the and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 5 Ω. The operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. (DIFF OUT) The 86 Ω resistors can also protect an ADC from overvoltages. Because the runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR converter, such as the AD7688. Its input can handle a 3 ma overdrive, which is much higher than the short-circuit limit of the. (SINGLE OUT) Figure 65. Driving a Cable Rev. A Page 25 of 28

26 OUTLINE DIMENSIONS 4. BSC SQ MAX.3 PIN INDICATOR PIN INDICATOR SEATING PLANE TOP VIEW 3.75 BSC SQ 2 MAX.8 MAX.65 TYP BSC.95 BCS BOTTOM VIEW.5 MAX.2 NOM COPLANARITY.2 REF.8 COMPLIANT TO JEDEC STANDARDS MO-22-VGGC. Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm 4 mm Body, Very Thin Quad (CP-6-3) Dimensions are shown in millimeters EXPOSED PAD SQ MIN 36-A ORDERING GUIDE Model Temperature Range Product Description Package Option ACPZ-R7 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 ACPZ-RL 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 ACPZ-WP 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 BCPZ-R7 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 BCPZ-RL 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 BCPZ-WP 4 C to +85 C 6-Lead LFCSP_VQ CP-6-3 -EVALZ Evaluation Board Z = RoHS Compliant Part. Rev. A Page 26 of 28

27 NOTES Rev. A Page 27 of 28

28 NOTES 27 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /7(A) Rev. A Page 28 of 28