Medium voltage electrical system research using DSP-based real-time simulator

Transcription

1 Computer Applicatios i Electrical Egieerig Vol Medium voltage electrical system research usig DSP-based real-time simulator Maciej Fajfer Uiversity of Techology ad Life Scieces i Bydgoszcz Bydgoszcz, ul. Ks. Kordeckiego 20, Maciej.Fajfer@utp.edu.pl The paper presets the results of a simulatio of operatig coditios of a two-sectioed medium-voltage power lie, with the use of a simulator based o a multi-core sigal processor. It is a kid of type of a real-time digital simulator of electrical system. Steady states ad trasiets were aalyzed, as well as the switchig operatio of the load with zero iitial coditios. The trasiet states of this electrical system was also aalyzed durig oe ad multi phase short-circuit. The oscillograms of steady ad trasiet ode system voltages ad currets registered durig simulator work were preseted. The obtaied results were compared to the oes received via Matlab simulatio package. The estimated maximum errors of the simulator i steady ad trasitio states were preseted. The method of simulatio, which is used i the implemetatio of discreet mathematical models of the complex electrical systems i real-time simulators, was applied. The mai advatage of the simulator is the ability of its cooperatio with real devices (e.g. regulators). KEYWORDS: simulator workig i real-time, DSP processor, simulatio of electrical system Itroductio For may years we could observe cotiuous developmet of microprocessor ad computer techology. It allows for the evolutio of the techiques ad tools used for simulatio i the field of electrical egieerig. Due to the decreasig cost of computer techologies ad the icrease i computig power of processors, it is possible to create a variety of computer systems workig as digital simulators of electrical systems. The developmet of real time simulators ad the ability to work with real devices (eg. regulators) is still a valid issue. I [1, 2] a persoal computer with multi-core processor ad graphics processors was used. By cotrast, [3, 4] focuse o DSP-based simulators. The study ivolved a sample of a electrical system. The article describes the use of a simulator for the aalysis of trasiet states occurrig i the electrical system, cosistig of a equivalet geerator (MV switchgear i a 110/15 kv trasformer statio) two-sectioed MV trasmissio lie ad receptio. This makes it possible to aalyze the pheomea occurrig radomly. A example of this could be the trasiet short circuits, of which detectio ad aalysis i a real power system is difficult. I additio, the estimated maximum errors of the simulator i steady ad trasiet states were preseted.

2 2. Real time simulatio of electrical systems Referrig to the IEEE [5] stadard, it is possible to provide a defiitio of a simulator operatig i real time (SOiRT). It is a digital platform i which calculatios are performed simultaeously with the exterally occurrig process, i order to cotrol, supervise ad timely respod to evets occurrig i this process [5, 6]. Schematic diagram of the SOiRT simulator is show i Figure 1. Fig. 1. Schematic diagram of the SOiRT simulator [1] The mai elemet of the simulator is the processor, which is the computig ad cotrollig uit. As i ay computer system, here you ca also distiguish the program ad data memory. The flow of sigals from the exteral process to the simulator ad vice versa is provided by the meas of aalog-to-digital (A/D) ad digital-to-aalog (D/A) coverters. The sesors ad actuators are placed i the exteral process. The exteral process described i the article, rus i a real techical object (eg. a regulator of a reactive power compesatio system). It allows to verify the accuracy of the algorithm implemeted i the regulator (respose to the processes occurrig i the electrical system) or to aalyze the operatig coditios of the electrical system, particularly the trasitioal processes, takig ito accout the characteristics of a real regulator (coected to the simulator). 3. Sigal processor based simulator A simplified block diagram of a simulator based o the digital sigal processor is show i Figure 2. The simulator has bee developed o the base of the TMDSEVM6678L developmet module made by Texas Istrumets. The mai elemet of this module is a eight-core TMS320C6678 DSP processor. I additio, the module cotais JTAG iterface of XDS100 type, ad umerous memory chips. Here it 335

3 is possible to distiguish 512 MB of DDR3 RAM exteral dyamic memory ad FLASH memory [7]. The computatioal power of a sigle core is 20 GFLOPS at a core clock frequecy of 1.25 GHz. The give computatioal power is achieved by performig up to eight istructios i parallel. It is possible because sigle core of the C66XX processor icludes several ALU computatioal uits. This allows you to perform parts of the calculatio parallelly i a sigle core. I additio, the processor supports 32-bit fixed ad floatig-poit calculatios (sigle precisio) ad 64-bit floatig-poit calculatios (double precisio). The parallel computig is supported here, icludig the classical support of the shared memory ad hardware sychroizatio mechaisms [8]. Fig. 2. Simplified block diagram of the simulator [3] The commuicatio with exteral devices was implemeted with the use of a SPI hardware iterface (Serial Peripheral Iterface). This iterface ca work with a maximum clock frequecy of 66 MHz ad the data frame legth i the rage from two to sixtee bits [9]. The choice of peripherals was made via the CS1 ad CS2 lie. The aalog outputs use a 16-bit, 8-chael Digital/Aalog D/A DAC8718 type coverter. Symmetrical power supply, referece voltage of 2.5 V ad a amplificatio of 6 was used. This allows to obtai chages i the output voltage ragig from -7.5 V to 7.5 V. The maximum operatig frequecy of the D/A SPI iterface is 50 MHz [10]. I order to simplify the hardware part of the system the two-way commuicatio was abadoed. The D/A coverter allows to eter the selected sigals ito the real object workig with the simulator. I cotrast, aalog iputs were created through a 16-bit, six-chael aalog/digital (A/D) ADS8558 type coverter. The ADS8556 cotai six successive approximatio register (SAR) based aalog-to-digital coverters (A/D) with true bipolar iputs. Each chael cotais a sample-ad-hold circuit that allows 336

4 simultaeous high-speed multi-chael sigal acquisitio. The additioal cotrol lies are essetial here. RESET sigal sets the coverter to the iitial state, while the lie CONVST begis the process of samplig ad covertig the aalog iput sigal. BUSY lie ca geerate a iterrupt to iform the processor about the ed of the coversio [11]. This system cofiguratio is adapted to the stadard rage of iput voltages from -10 V to +10 V. I order to esure galvaic isolatio a ISO7240M system was used betwee the processor ad audio A/D ad D/A coverters. ISO7240M system is a quadruple optical isolator, which ca operate at a maximum bitrate of 150 Mb/s [12]. 4. Mathematical model of the aalyzed system The aalyzed electrical system cosists of a equivalet geerator (MV switchgear i a 110/15 kv trasformer statio) - structural elemet ES1, twosectioed MV power trasmissio lie - structural elemets ES2 - ES6 ad the MV cocetrated MV receptio - structural elemet ES7. The power lie model is the classical model of type π, with RL logitudial braches ad C trasverse braches. I developed model serially with capacitors usig for represetig capacitace to groud ad capacitaces betwee phase wires was iserted i series coected resistors ad iductors. Preseted mathematical model is based o multipole method which is oe of the may kow methods of modellig of electric circuits. I this method electric circuit is aalyzed as structural elemets (SE) coected each other. O Figure 3 was preseted iteral structurals of multipoles usig for created model of aalyzed circuit. Fig. 3. Iteral structurals of multipoles usig for created model of power lie I this case structural elemets are represet by six-termial etwork (multipole). It is possible to specify iteral structural types of ERL, RL ad RLC depedig o elemets cotaied i followig braches. Model without LC elemets was used. This kid of model is uderstood as a resistace model with currets sources. It is created by approximatio differetial equatios which describe capacitace ad iductace by selected 337

5 algorithm of umerical itegratio. I their research, the author used the trapezoidal umerical itegratio algorithm [1]. I Figure 4 a equivalet schematic diagram of aalyzed circuit with followig structural elemet was explaied. 338 Fig. 4. Equivalet schematic diagram of aalyzed circuit This circuit cosists of seve three-phased structural elemets (SE1 SE7). The elemet is preseted i the form of a multipole, for which the vector of potetial exteral odes ca be explaied v T v1se k v2 v3 v4 v5 v6, (1) where: v 1, v 2, v 3, v 4, v 5, v 6 potetial of exteral odes k-th structural elemet,

6 as well as vector of exteral braches currets of elemet i T i1se k i2 i3 i4 i5 i6, (2) where: i 1, i 2, i 3, i 4, i 5, i 6 currets of exteral braches k-th SE. Mathematical model of elemet has to be realized i a way that allows to create the exteral vector equatio as follows [1] ise k ASE kv B 0, (3) where: A square matrix with size 6 6; B 6-elemet colum matrix. Elemets of matrices A ad B used i (3) are defied by parameters ad physical quatities iside elemet. Termials of idividual structural elemets SE are coected i eleve odes of electric circuit. Potetial of oe of these ode equals zero. Therefore for remaiig te exteral odes a vector of potetial of electric circuit ca be created v T S v1s v2s v3s v4s v5s v6s v7s v8s v9s v10s, (4) where: v 1S, v 2S, v 3S, v 4S, v 5S, v 6S, v 7S, v 8S, v 9S, v 10S idepedet potetial odes of circuit. Coectio betwee potetial of exteral odes SE ad potetial odes of circuit ca be described usig a matrix traspose i relatio to the icidece matrix P k k-th elemet [1] T v Pk v. (5) S Matrix P k usig i (5) is costat for idividual elemet. Number of rows is equal to umbers of idepedet odes of electric circuit. Whereas umber of colums is equal to umbers of braches idividual SE. It meas i aalyzed example size of matrices P k is After usig Kirchhoff's curret law for all idepedet odes of circuit followig equatio ca be created 7 Pk i 0. (6) k1 After determiig curret values of exteral braches of multipoles usig (3) ad substitutio this values to (6) as well as usig (5) odal equatio of circuit ca be created [1] where: A S v S B S 0, (7) 7 T A P A P, (8) S k1 7 k1 k k B P k B. (9) S I case whe elemet is six-termial etwork (multipole) matrix A is gettig by [1] 339

7 340 M. Fajfer / Medium voltage electrical system research usig DSP-based... a a A, (10) a a where: 0 0 a 0 0, (11) 0 0 where: ζ umber of idividual SE braches (i this case ζ = 1, 2, 3). I this case matrix B is as follow [1] b B, (12) b where: b, (13) where: ζ umber of idividual SE braches (i this case ζ = 1, 2, 3). Physical quatities α ζ ad β ζ deped o iteral structurals ad physical parameters of idividual. Equatios that are ecessary for calculatig α ζ, β ζ as well as physical quatities iside structurals elemets SE are combied below with iteral structurals. Elemet type of ERL (SE1) [1]: e t E si 2πft, (14) m 1 R L, (15) 1 e t 1 ul t L i t 1 t L i t i t u t, (16) ul 1 1 L, (17) where: ξ =0,5h; h software itegratio step; ζ A, B, or C for followig phase of ; t +1 ext momet of time; t actual momet of time; E mζ amplitude of voltage source; f frequecy; φ ζ iitial phase; Elemet type of RLC (SE2, SE4, SE6) [1]: R L C 1 1 u C t ul t L C i t 1 k t 1 C i t 1 i t ucse k t 1 t L i t i t u t, (18), (19) SE k u u C SE, (20) L 1 1 L. (21)

8 Elemet type of RL (SE3, SE5, SE7) [1]: u L 1 R 1 L 1 ul t LSE k i t i t i t u t, (22), (23) t L 1 1 L. (24) The developed mathematical model of example electric circuit was implemeted i digital simulator of electric circuit which was described briefly i poit Aalyzed electrical circuit simulatio algorithm I Figure 5 the author presets a mathematical modelig algorithm of aalyzed electric circuit with the use of a model described i poit 4, which was implemeted i hardware structure explaied i poit 3. Research was carried out with the use of sequetial computig based o oe core of the processor. A.1 block is used for iput data. It meas the memory is iitialized by values relatig to parameters ad physical quatities iside structural elemets. Block A.2 realizes calculatig values which are costat i the simulatio process. It is ecessary to distiguish differeces betwee calculatig time ad software itegratio step. First is the time of executig calculatig blocks from A.4 up to A.11. Secod is the itegratio step of differetial equatios of mathematical model of electric circuit, which obviously deped of summig calculatig time ad time cosumptio for commuicatig with D/A coverter. A.3 block is used for the cofiguratio of the processor ad peripheral devices. Clock rate of cores of the processor type TMS320C6678 is equal to 1 GHz. It is usig real time operatig DSP/BIOS from Texas Istrumets. The time variable t is icreasig i each iteratio by value of software itegratio step h. RTI module (Real Time Iterrupt) iside the structural of usig processor is resposible for the software itegratio step. This module was cofigured for call periodically iterrupt every time h (coditioal operatio W.1). There is a global variable set up i the subroutie of this iterrupt. It causes the start of calculatio iside mai loop of program. Afterwards blocks A.4 ad A.5 are realized usig equatios (5) ad (3). I computig block A.6 iteral physicals quatities of SE are determied, such as voltages o capacitors ad iductors based o equatios (17), (20), (21) ad (24). A.8 ad A.9 blocks are resposible for calculatig elemets of matrixes A S ad B S usig calculatio formulas (8) ad (9). Fial calculatig block is A.10 which is used for umerical solvig of liear equatio system (7). I articles [3, 4] the simplest method for solvig equatio (7) was used. It was factorizatio of mai matrix AS of liear equatio system for lower triagular matrix L ad upper triagular matrix U (LU factorizatio). This liear equatios systems (for matrices L 341

9 ad U) was afterwards solved by forward ad backward substitutio algorithms. Factorizatio was carried out with the use of Doolittle s algorithm [13]. 342 Fig. 5. Mathematical modelig algorithm of electric circuit [4]

10 I this article, aside from methods used previously, the Gauss-Seidel iteratio method was used. Iteratio methods for solvig liear equatio systems ca achieve high performace i case of sparse matrix for mai matrix of liear equatios. For such method it is required to execute N iteratio for improvig iitial solutio for oe iteratio of electric circuit. I preseted model matrix A S cosists of 100 elemets. This matrix ca be cosidered as sparse because oly 28 elemets are differet tha zero. I order to achieve high performace of iteratio methods it is ecessary special represetatio of matrix A S without zero elemets. I this case is usig coordiate format. It meas matrix A S is represet by three vectors I, J, V. Legth of this vectors is equal to umber of o zero elemets. Vector I cotais the rows umbers of ozero elemets, while the vector J colum umbers. The last of the vectors V cotais values of ozero elemets. Basic versio of coordiate format does ot require orgaized registratio. Because i every iteratio of the iterative method is required A S matrix multiplicatio by the vector of iitial solutio is better stored i V the ozero elemets of the followig rows. Such a multiplicatio algorithm makes iterative methods especially performace i the case of sparse matrices. It is achieve by to avoid multiplicatios by zero elemets. As a iitial solutio vector used odal voltages V S from the previous iteratio of the model. Therefore first iteratio uses as a iitial solutio vector V S filled with zeros. The calculatio is termiated after reachig a predetermied umber of iteratios. Due to icrease the time variable t i each iteratio by the value of the software itegratio step h it causes value of t ca theoretically reaches ifiity. It should be oted that the periodic sigals are geerated, so a coditioal operatio block W.2 ca determie whe a variable t exceeds period T of the sigals occurrig i the model. If it happes variable t is reset to zero. Calculatios are executig up to ed of the simulatio. It is schematically illustrated as W.3 block. It ca be associatio with expired time of simulatio defied i A.2 block. The last of blocks is A.11. It correspods for sedig sigals of istataeous values the specified sigals of model to the D/A coverter. Source code of a program was developed i C laguage ad compiled i Code Composer Studio 5.5 eviromet from Texas Istrumets. 6. Experimetal research I Table 6.1. was combied parameter of elemets of electric circuit (Fig. 4) which are usig i experimetal research. Value of itegratio step h is equal to 110 μs. This value of itegratio step was to chose for possibility workig model i real time. It is widely described i sectio 6.1. Whereas parameters of voltage sources iside the SE1 elemet was show i Table 6.2. This parameters to meet the coditios i three phase balaced etworks of medium voltage ad frequecy 50 Hz. 343

11 344 M. Fajfer / Medium voltage electrical system research usig DSP-based... Table 6.1. Parameters of structural elemets Structural elemet Typ R ζesk [Ω] L ζesk [mh] C ζesk [F] ES1 ERL 0,195 6,21 - ES2 RLC 0,01 1,00 36,5 ES3 RL 1,32 3,63 - ES4 RLC 0,01 1,00 72,0 ES5 RL 2,64 7,26 - ES6 RLC 0,01 1,00 36,5 ES7 RL Table 6.2. Parameters of voltage sources of elemet SE1 E mζes1 [V] f [Hz] φ AESk [rad] φ BESk [rad] φ CESk [rad] , Durig carry out research was aalyzed odal voltages of electric circuit ad currets of exteral braches of elemet SE7. This sigals was to put out to the eviromet of simulator by usig D/A coverters. Due to the acceptable output voltage rage of D/A coverter sigals represetig odal voltages was divided by 1700 before sedig procedure. Aalyzed currets was coverted to voltages sigals usig coefficiet equal to 0,017 Ω. Give coefficiets was calculated for achieve full scale of outputs voltages D/A coverter. Measuremets was carry out usig Rigol DS1104B oscilloscope Calculatio time for DSP processor Compariso calculatio times was carried out for LU factorizatio ad Gauss-Seidel methods for solvig liear equatio system (7). Floatig poit computig was made for sigle-precisio ad double-precisio floatig poit umber represetatio. Table 6.3 iclude combiatio of calculatio times for previously described cases. This times to pertai cosecutive te iteratios of the model. I case of Gauss-Seidel iteratio method costat umber of twelve iteratio improvig iitial solutio was usig. I the case of double-precisio computig is possible to obtai time for a iterative method lower by 13,545 μs tha time for the LU factorizatio method. However for sigle-precisio computig is to obtai time decrease time of computig by 5,729 μs. Whereas i the case of sigle-precisio computig is to obtai decrease time of calculatig by 5,729 μs. The differece betwee these values are causes by differet computatioal complexity of usig algorithms ad

12 more time for executig a double-precisio arithmetic operatios. Referrig to times combied i Table 6.3, times the data trasfer to the D/A coverter ad other delays existig i the DSP it is possible to achieve the previously specified software itegratio step amoutig to 110 μs. Time fluctuatios i followig iteratios are cases by workig of operatioal system DSP/BIOS. Table 6.3. Combiatio of the calculatig time Method s ame Calculatio time of idividual iteratio Mea calculatio time LU factorizatio double precisio computig Gauss-Seidel - double precisio computig LU factorizatio sigle precisio computig Gauss-Seidel - sigle precisio computig 78,474 64,983 67,818 62,046 78,511 64,618 67,817 61,612 78,021 65,059 67,408 62,046 78,427 65,014 67,405 61,612 78,424 64,613 67,820 62,055 78,424 65,316 67,409 62,043 78,422 65,004 68,174 62,031 78,794 65,030 67,406 62,043 78,848 65,030 67,772 61,617 78,388 64,613 67,409 62,042 78,473 64,928 67,644 61, Experimetal accuracy estimatio of simulatio results Accuracy estimatio of simulatio results was carried out for previously described methods for solvig liear equatios systems as well as sigleprecisio ad double-precisio computig. Furthermore was aalyzed accuracy computig for steady state ad trasitio sates. I case trasitio states was chose trasitio short circuit state. Oe phase short circuit i phase A of structural elemet SE7 as well as multiple phase short circuit was aalyzed. Sigals recordig was started after 500 ms from begiig simulatio. As well as after that time trasiet states was to produced. Trasiet mometary short circuit duratio was 40 ms. Whereas value of resistace i short-circuited brach was equal 2,00 Ω ad value of iductace 141 mh. Waveforms ad values of some variables was aalyzed. It was odal voltages of circuit V S1 V S9 ad currets of exteral braches of elemet SE7. Errors of all variables was obtaied as follows: a jb t aj t j max max A, (25) jb where: a jb (t) calculated istataeous value j-th variable of base results; a j (t) calculated istataeous value j-th variable; A jb vector of base values of j-th variable. 345

13 Istataeous values of base variables as well as istataeous values of model variables was calculated i Borlad Builder C++ eviromet with usig as digital platform PC computer. I the same eviromet was also calculated values of maximal errors based o (25). It uses the model implemetatio for DSP processor usig the portability of code i C. Carry out research by this method is possible due to the o of sigificat differeces i the results of calculatios for the PC ad the DSP. I the case of calculatig the istataeous values of variables software itegratio step was 110 μs. Justificatio for the selectio of this value is give i sectio 6.1. Whereas base variables were determied for 1 μs itegratio step, double-precisio calculatios ad LU factorizatio method for solvig a system of liear equatios (7). For comparative purposes have bee take ito accout at 110- th the value of the base variable. I Figure 6 maximal errors calculated base o (25) was show for steady state. Fig. 6. Maximal errors for model variables i steady state Afterwards o Figure 6 was show maximal errors for oe phase mometary short circuit. Whereas o Figure 7 was explaied maximal errors for trasiet multiple phase short circuit. 346 Fig. 7. Maximal errors for model variables i oe phase trasiet short circuit

14 Fig. 8. Maximal errors for model variables i multiple phase trasiet short circuit Calculatio errors obtaied for a iterative Gauss-Seidel ad LU factorizatio method are similar (Fig. 6, 7 ad 8). Usig double-precisio computig ca reduce sigificatly values of errors (Fig. 6, 7 ad 8). It relates i particular to the steady state (Fig. 6). Values of the error preset i the trasiet state are much larger tha i steady states. It is caused by larger chages the values of variables i the trasiet states betwee followig iteratios Steady state Figure 8 show some of the waveforms odal voltages (Fig. 9a) ad currets of exteral braches structural elemet SE7 (Fig. 9b) i steady state. Fig. 9. Waveforms i steady states, a) some of the odal voltages (3400V/div), b) currets of exteral braches of structural elemet SE7 (120A/div) Noticeable siusoidal sigals are show with phase shift each other of agle to poit i Table 6.2. Because simulated electric circuit is balaced (Tab. 6.1) that potetial v 10S reaches zero value. I order to verify the proper operatio of developed digital simulator of the electrical circuit, a suitable simulatio i Matlab was also carried out. This 347

15 simulatio was carried out with usig the same methods like i digital simulator based o the sigal processor. Figure 10 shows simulatio results from Matlab. Fig. 10. Waveforms of some odal voltages ad currets of exteral braches SE7 (Matlab simulatio) After comparig the experimetal results with results from simulator based o DSP it ca be cocluded that there are o sigificat differeces betwee the istataeous values i steady state. This proves the satisfactory adequacy of the simulatio usig a digital simulator developed for exemplary electric circuit Trasiet states I Figure 11 was preseted waveforms of currets of exteral braches SE7 elemet i to switch o load i programmed time. I this experimet first step was to switch o equivalet geerator modelig by SE7 elemet. Secod step was to switch o load SE7 after 500 ms from start of the simulatio. 348 Fig. 11. Curret waveforms of exteral braches SE7 i to switch o load state (120A/div)

16 Figure 12 shows some of the waveforms odal voltages (Fig. 12a) ad currets of exteral braches structural elemet SE7 (Fig. 12b) i oe phase mometary short circuit i programmed time. Short circuit is created i phase A of SE7 elemet after 500 ms from start of the simulatio. Trasiet mometary short circuit duratio was 40 ms. I that time value of resistace R ASE7 = 2,00 Ω, a iductace of L ASE7 = 141 mh. Fig. 12. Waveforms i oe phase trasitio short circuit, a) some of the odal voltages (3400V/div), b) Currets of exteral braches of structural elemet SE7 (120A/div) Due to o groudig of ode umber 10 there are chages currets i other phases SE7 elemet. Furthermore imbalace causes v 10S potetial reaches values greater tha zero durig the short circuit. The last cosidered trasiet state was multiple phase trasitio short circuit i programmed time. Short circuit is created i all phases of SE7 elemet after 500 ms from start of the simulatio (Fig. 13). Trasiet mometary short circuit duratio was 40 ms. I that time value of resistace equals 2,00 Ω, ad the iductace 141 mh i all braches of SE7 elemet. Fig. 13. Waveforms i multiple phase trasitio short circuit, a) some of the odal voltages (3400V/div), b) Currets of exteral braches of structural elemet SE7 (120A/div) I this case potetial v 10S is zero all the time. It is caused by balaced durig simulatio of trasiet short circuit. 349

17 I this case as well, i order to verify the results a simulatio i Matlab was carried out. I Figure 14 was preseted waveforms of currets of exteral braches SE7 elemet i to switch o load. Fig. 14. Waveforms of phase currets SE7 elemet durig to switch o load (Matlab simulatio) Figure 15 shows simulatio results i Matlab for oe phase trasitio short circuit. Fig. 15. Waveforms of some odal voltages ad currets of exteral braches SE7 i oe phase trasitio short circuit (Matlab simulatio) The last aalyzed issue of simulatio i Matlab was the case of multiple phase trasitio short circuit. The results of this simulatio was show o Figure 16. Also i the case of trasiet aalysis ca be cocluded that digital simulator developed a exemplary electric circuit is workig properly. 350

18 Fig. 16. Waveforms of some odal voltages ad currets of exteral braches SE7 i multiple phase trasitio short circuit (Matlab simulatio) 7. Coclusios The article presets the results of a simulatio of operatig states of a electric circuit based o a multi-core sigal processor TMS320C6678. Due to the real time simulatio, the created simulator ca cooperate with real devices such as regulators. This type of operatio is cofirmed by the give waveforms from oscilloscope. The possibility of a simulatio of a circuit i steady state as well as trasiet state was show. It is importat for the aalysis of electric circuits because registerig trasiet states i real circuit is difficult. I author s opiio, simulatio results created by Matlab are coicidetal eough with the results received from simulator based o a sigal processor. Moreover, maximal errors estimated for steady states ad trasiet states (Fig. 6, 7, ad 8) allow, i the author's opiio, to costitute satisfactory adequacy of the preseted model. This paper demostrates the possibility of decreasig the calculatio time with the use of Gauss-Seidel iteratio method for solvig liear equatio (7). It allowed to decrease the calculatio time i referece to the LU factorizatio method up to 17% (Table. 6.3). It is also importat that there is o sigificat icrease of the error calculatio i the case of the iterative method (Fig. 6, 7 ad 8). It was also show that the use of double precisio calculatio ca sigificatly reduce the calculatio error (Fig. 6, 7 ad 8), without sigificat icrease of the error calculatio (Tab. 6.3). Preseted results ecourage the author to carry out further research, especially i the field of parallel computig. Aother iterestig aspect metioed i the article, is the use of faster coverget iterative methods for solvig system of liear equatios (7). It could allow to receive bigger beefits from usig the iterative method. 351

19 Referece [1] Cieslik S., Obwodowe modele układów elektryczych w cyfrowych symulatorach pracujących w czasie rzeczywistym, Wydawictwo Politechiki Pozańskiej, [2] Cieslik S., GPU Implemetatio of the Electric Power System Model for Real- Time Simulatio of Electromagetic Trasiets, Proc. of the 2-d Iteratioal Coferece o Computer Sciece ad Electroics Egieerig, Atlatis Press, Paris, Frace, 2013, pp [3] Fajfer M.: Symulacja staów pracy układu elektryczego z wykorzystaiem symulatora opartego a procesorze sygałowym, Poza Uiversity of Techology Academic Joural, 2014, r 80, str [4] Fajfer M.: Kocepcja cyfrowego symulatora układów elektryczych pracującego w czasie rzeczywistym opartego a procesorach sygałowych, Ryek Eergii, 2014, Nr 5, str [5] Glossary of Software Egieerig Termiology, IEEE/ANSI Stadard 729, [6] Stadard Computer Dictioary, IEEE Std 610, [7] SPRUH58 - TMDSEVM6678L EVM Techical Referece Maual Versio 2.0, Revised March [8] SPRS691D - TMS320C6678 Multicore Fixed ad Floatig-Poit Digital Sigal Processor, April [9] SPRUGP2A - KeyStoe Architecture Serial Peripheral Iterface (SPI) User Guide, March [10] SBAS467A Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Iput DIGITAL-TO-ANALOG CONVERTER, May 2009 Revised December [11] SBAS404B - 16-, 14-, 12-Bit, Six-Chael, Simultaeous Samplig ANALOG- TO-DIGITAL CONVERTERS, October 2006 revised Jauary [12] SLLS868O ISO7240CF, ISO7240C, ISO7240M, ISO7241C, ISO7241M, ISO7242C, ISO7242M High speed quad digital isolators, September 2007 Revised November [13] Kicaid David, Cheey Ward, Aaliza umerycza w przekładzie i pod redakcją Stefaa Paszkowskiego, Wydawictwa Naukowo-Techicze, Warszawa