Embedded system for audio source localization based on beamforming

Transcription

1 Embedded system for audio source localizatio based o beamformig Petr Dostále, Ja Doliay ad Vladimír Vaše Abstract Paper presets desig of embedded audio source localizatio system with respect to compact dimesios, low power cosumptio ad easy implemetatio to applicatios such as telecoferecig, security ad robotics systems. It cosists of the three mai fuctioal parts: fixed geometry microphoe array with fiftee omidirectioal uits with geometrical cofiguratio adapted for beamformig at ceter frequecy of 75 Hz, sixtee chael preamplifier uit with built-i atialias filter ad evaluatio uit based o five 3bit microcotrollers Freescale MCF5AC8 where each cocurretly processes a part of the localizatio algorithm. Evaluatio uit is equipped with alphaumerical LCD display for visualizatio of the device state ad localizatio results i autoomous mode. For commuicatio with supervisio system is provided USB iterface allowig complete cofiguratio possibilities ad results trasferrig icludig diagostic data. Keywords acoustic source localizatio, beamformig, FFT, itelliget sesor, microphoe array, ColdFire V. B I. INTRODUCTION EGINNING of audio localizatio is dated to the year 88 whe the first device for this purpose was desiged. Its ivetor Professor Mayer used it for avigatio improvemet i fog. This istrumet was called by its author Mayer s topophoe. O the basis of his ivetio was costructed umber of similar devices but with questioable practical usage. The biggest iterest i audio locatio systems occurs i the period betwee World War ad World War. They were primarily used for detectio a localizatio of the aircraft egie soud. Measured data about aircraft positio was directly trasferred to air-defese artillery which ca aim at target before visual cotact. Costructios ad dimesios of these systems were very various but the basic cocept is based o Mayer s topophoe improved with ext two hors orieted This wor was supported by the Europea Regioal Developmet Fud uder the project CEBIA-Tech No. CZ..5/../3.89. This support is very gratefully acowledged. Petr Dostále is with the Departmet of Automatio ad Cotrol Egieerig, Tomas Bata Uiversity i Zli, Faculty of Applied Iformatics, ám. T. G. Masarya 5555, 7 Zlí, Czech Republic ( dostale@fai.utb.cz). Ja Doliay is with the Departmet of Automatio ad Cotrol Egieerig, Tomas Bata Uiversity i Zli, Faculty of Applied Iformatics, ám. T. G. Masarya 5555, 7 Zlí, Czech Republic ( doliay@fai.utb.cz). Vladimír Vaše is with the Departmet of Automatio ad Cotrol Egieerig, Tomas Bata Uiversity i Zli, Faculty of Applied Iformatics, ám. T. G. Masarya 5555, 7 Zlí, Czech Republic ( vase@fai.utb.cz).). i vertical plae. Due to state of electroics the miimally two people were required for soud aalysis origiated from hor system. Sice it was impossible to cotiuously elarge hor dimesios for better gai achievig, static dishes ad walls based o spherical reflectio surface was developed. These systems were able to detect aircrafts at loger distaces. After radio locator ivetio i 934 audio locatio devices were ot further developed i this area because they were completely replaced by RADAR systems with better detectio ad ragig properties [6]. Nowadays very dyamical developmet i electroics ad computer sciece eables applyig of the soud localizatio systems i areas where it was impossible due to techical ad ecoomical aspects several years ago. These areas iclude applicatios i security, telecoferecig, robotic systems ad other else where iformatio is coded i audio sigal source positio. This paper deals with desig of the compact audio source localizatio system cosistig of microphoe array with fiftee electret uits, multichael preamplifier with atialias filter ad evaluatio uit based o five 3bit microcotrollers. It also icludes software implemetatio of data acquisitio, digital filters ad soud source localizatio algorithm. Theoretical part describes mai priciple of delay ad sum type beamformer operatio ad its applicatio i soud source localizatio system. Next part proposes desig of the sesory system cosistig of microphoe array with fixed geometry ad preamplifiers with atialiasig filters for sigal coditioig to correct voltage levels before aalog-to-digital coversio process i microcotrollers. The follows chapter describig hardware architecture of the evaluatio system based o five 3bit Freescale ColdFire V MCF5AC8 microcotrollers where each performs cocurretly portio of the localizatio algorithm. Last part of the paper deals with software implemetatio of the evaluatio uit. II. BEAMFORMING PRINCIPLE Priciple of delay ad sum beamformer operatio is obvious from Fig.. Iput sigals from microphoe array x[] are delayed by time which depeds o sesory system geometrical cofiguratio ad soud source agle [], [5]. We ca cosider that sigals from microphoe uits i the array are same except time-shift. Maximum level of useful sigal after summig we obtai by settig of appropriate delay d a [m] to each audio chael. Issue 6, Volume 6, 367

2 Beamformer output y a [] steered to agle a ca be computed by equatio () where x m [] is iput sigal from microphoe m, d a is delay i samples itroduced to sigal path of microphoe m for beam directio a ad M is umber of microphoe uits. y a M [] = xm [ d a [ m ] m= For liear uiform microphoe array depicted i Fig. ad o assumptio that soud source is i much larger distace tha is each sesor spacig d S, time delay i each microphoe uit sigal for directio of soud wave arrival α ca be computed by equatio (), where is microphoe uit idex ad v is soud wave propagatio speed i air. Referece uit is microphoe with idex which has zero time shifts for all source agles. t siα ds = v ( ) Soud source localizatio usig delay ad sum beamformer is based o computatio of its output sigal level for each soud source azimuth agle. Root-mea-square value of the samples legth output sigal ad azimuth agle a ca be determied by equatio (3). V RMS [] a = ya [] = Maximum RMS value of beamformer output ad correspodig agle idicates soud source azimuth: a ( [] a ) α = argmax. (4) V RMS () () (3) rage which is fully determied by microphoe array geometry it is very importat to limit badwidth of the sigal eterig beamformer iputs. This ca be doe by isertig aalog bad-pass filters realized by operatioal amplifiers to the sigal path before aalog-to-digital coverter or by digital bad-pass filter which operates with digital sigal after A/D coverter. Advatage of the first approach is that there is o computatioal cost o evaluatio system. O the other had it is difficult to practical realize precisio higher orders filters which are required for this purpose. Secod method assumes that sigal badwidth is restricted by microphoe uits itself ad therefore there is o eed to apply atialias filter before A/D coverter if samplig frequecy is high eough. All filtratio tass are the processed digitally eablig to use filter which best fulfills our requiremets. I real audio processig system it is still better to use at least lower order atialias filter which ca smooth trasiets origiatig o log sigal path from microphoe uits to preamplifier. Filter cutoff frequecy should be selected as highest possible for proper beamformer operatio o the other had it must bad limit sigal to fulfill the Shao-Koteliov samplig theorem at used samplig frequecy. With respect to usage of fixed poit arithmetic i evaluatio system it is better to use fiite impulse respose (FIR) filter istead of ifiite impulse respose (IIR) filter by reaso of higher order IIR filter implemetatio is sesitive to roud-off errors durig computatios. FIR filters does ot have this limitatio so there is o problem with filter istability or bad results. But requiremets o the computatioal power are much higher due to processig time itesive covolutio of filter erel with filtered sigal. For our applicatio is suitable digital versio of Butterworth 8 th order low-pass ad high-pass filters combied to bad pass filter. Butterworth low-pass filter poles s ca be computed usig equatio (5), where ω c is cutoff agular frequecy, filter order ad pole idex i the rage of,, 3,, [8]. A. Sigal filterig Because of beamformer best wors i arrow frequecy s = e j π ( ) (5) x [] d a [] w [] Distat soud source x [] d a [] w [] x 3 [] d a [3] w 3 [] Σ y a [] Δd α x M [] d a [M] w M [] MIC α d S MIC Fig. Delay ad sum beamformer operatio. Fig. Soud wave impactig pair of sesors. Issue 6, Volume 6, 368

3 H Trasfer fuctio of the -th order low-pass filter the is: LP () s = = = s s s ωc, (6) where ω c is cutoff agular frequecy. Trasfer fuctio of high-pass filter is: H HP () s = = s = s s s ωc. (7) Discrete impulse resposes (filter erels) of the both filters we obtai after coversio of cotiuous-time models (6) ad (7) to discrete-time models i the form (8) followed by computatio of filters respose to uit impulse δ[]. H ( z) b z + b z b = (8) a z + a z a Bad-pass filter erel h BP [] is equal to the covolutio of the low-pass h LP [] ad high-pass h HP [] filter erels: h BP [] h [] h [] =. (9) LP HP Filter output y[] is equal to the covolutio of filter erel h BP [] with iput sigal x[] [7]: [] h [] x[] y = BP. () bit A/D Coldfire V USB iterface Microphoe array (up to 6 uits) 6 chael preamplifier uit bit A/D Coldfire V Coldfire V GPIO bit A/D Coldfire V Fig. 3 Localizatio system architecture. bit A/D Coldfire V Mai microcotroller LCD display Due to the fact that covolutio computatio for large N taes a lot of computer processig time, it is suitable to compute it i the frequecy domai i which processig time cosumig covolutio is replaced by multiplicatio of Fourier trasformed iput sigal x[] ad filter erel h BP [] [7]: [] F { F{ h [] } F{ x[] } y = BP. () III. LOCALIZATION SYSTEM HARDWARE ARCHITECTURE Hardware of the acoustic source localizatio system is obvious from Fig. 3. It cosists of microphoe array with fixed geometry cofiguratio, sixtee chaels preamplifier with built-i atialias filter ad evaluatio uit. A. Microphoe array For microphoe array geometry desig was created program equipmet worig i Matlab 6.5 eviromet which ca compute for give geometry both directioal ad steered directioal characteristic usig beamformig for demaded mai lobe agle. Usig this program was desiged array geometry optimized for audio source frequecies i the rage of Hz to Hz where is o the basis of simulatio results esured required shape of directioal characteristic ad satisfactory steered directioal characteristic over all demaded mai lobe agles without distict side lobes. Operatio with wider frequecy rage is possible but with egative effect o the directioal characteristic. Simulated characteristics for differet microphoe array cofiguratios are depicted i the Fig. 4. I the first colum is microphoe array cofiguratio, i the secod colum array directioal characteristic ad i the last steered directioal characteristic to agle 45 degrees usig beamformig. Practically realized is the last array at the bottom of the figure. Table I. Coordiates of microphoes i the array. Microphoe idex [-] X coordiate [mm] Y coordiate [mm] Issue 6, Volume 6, 369

4 Microphoe array geometry Normalized directioal characteristic 9 Normalized steered directioal characteristic y [m] gai [-] 8 gai [-] x [m] 4 7 agle [degrees] Hz Hz Hz 4 7 agle [degrees] Hz Hz Hz Microphoe array geometry Normalized directioal characteristic 9. Normalized steered directioal characteristic 9 5. y [m] 9 gai [-] 8 gai [-] x [m] agle [degrees] 3 Hz Hz Hz 4 7 agle [degrees] 3 Hz Hz Hz. 4 Microphoe array geometry 8 6 Normalized directioal characteristic 9 Normalized steered directioal characteristic 9 y [m] gai [-] 5. 8 gai [-] x [m] 4 7 agle [degrees] Hz Hz Hz 4 7 agle [degrees] Hz Hz Hz Microphoe array geometry Normalized directioal characteristic 9. Normalized steered directioal characteristic 9 5. y [m] gai [-] 8 gai [-] x [m] agle [degrees] 3 Hz Hz Hz 4 7 agle [degrees] 3 Hz Hz Hz Fig. 4 Simulated directioal characteristics of differet microphoe array geometrical cofiguratio. Issue 6, Volume 6, 37

5 Realized microphoe array cotais 5 omidirectioal electret microphoe uits MCE soldered o the prited circuit board (PCB) with dimesios of x mm. O the board is itegrated stabilized power supply with output voltage of 5 V which is eeded for operatio of microphoe uits. Output sigal from each microphoe is coected to doublerow coector where 4 pis are reserved for array supply voltage i the rage of 7.5 to 5 V, pis for groud ad 6 pis for audio sigal output. Because of preamplifier is ot itegrated i the microphoe array board it is suitable to coect amplifier with shortest possible ribbo cable to avoid iterferece leaage ad useful sigal losses. Schematic of the microphoe array is i the Fig. 5, photograph of completed array i the Fig. 6. B. Microphoe preamplifier Each microphoe cartridge of microphoe array is coected with preamplifier uits followed by d order active low-pass atialias filters based o rail-to-rail quad operatioal amplifiers TS94 (for oe audio chael is used half of the operators). Filter parts was desiged usig Bessel approximatio with cut-off frequecy of Hz ad gai of db i the passbad. This type of the filter was chose due to liear curve of the phase characteristic i the wide frequecy rage ad advatageous step respose with small overshot. O the other had its drawbac is smaller slope of the stop-bad part of the frequecy characteristic i compariso with Chebyshev or Butterworth approximatios. Parts values were desiged usig procedure published i [8]. Computatio of filter parts is based o trasfer fuctio of Salle-Key d order low-pass filter () where coefficiets a ad b are equal to (3) ad (4). A A() s = + a s + b s () [ C ( R + R ) + ( A ) R ] a = ω c (3) C ωc R RCC b = (4) Trasfer fuctio of the d order low-pass filter is: () A s A =, (5) + ω c[ C( R + R ) + ( A ) RC ] s + ω c R RCC s where ω c is a cutoff agular frequecy, A is gai of the filter i the passbad ad a ad b are filter coefficiets determiig its properties. After the formulatio of R from equatio (4) ad costitutig to (3) we obtai quadratic equatio: R ( C + C A C ) C C c arcc ωc + b = ω (6) Its solutio is equatio for computatio of R part value (8), R part value ca be computed by (7). R b = (7) RCCωc acc ωc + R = ( a C C ω ) 4C C ω b ( C + C A C ) c C C c ωc (8) I order to obtai o egative value uder square root i (8), capacitors values must fulfill (9). C 4b A + a A a C (9) a A Fig. 5 Microphoe array board schematic. Fig. 6 Photograph of the completed microphoe array board. Issue 6, Volume 6, 37

6 Bessel-type filter coefficiets for both filter stages are provided i the Table II. Table II. Bessel filter coefficiets [8]. Filter order Stage i a i b i Q i Practically the easiest way is to choose first capacitors C ad C maufactured usually i E6 series ad the compute resistor values. Exact resistor value ca be reached by coectig more resistors i parallel or i series. Schematic of the amplifier for oe audio chael is depicted i the Fig. 7. As ca be see preamplifier cosist of the two stages. First oe is o-ivertig amplifier IC A with gai of db which additioally represets low impedace sigal source for filter circuit. Secod operator IC B is a part of d order Bessel filter. Its output is directly coected to aalog-to-digital coverter of the evaluatio uit without couplig capacitor. C. Evaluatio uit Hardware of the evaluatio system is based o 3bit Freescale ColdFire V MCF5AC8 microcotrollers each providig computatioal power ear 5 DMIPS ad low power cosumptio. These microcotrollers have itegrated o the chip 8 KB of the flash memory, 3 KB of static RAM ad may peripherals such as bit aalog to digital coverter with up to 4 chaels, timer system, serial peripheral iterface (), serial commuicatio iterface (SCI), cotroller-area etwor (CAN) ad others []. Evaluatio uit structure is obvious from Fig.3. Aalog sigal from microphoe uits is amplified to voltage rage 5 V suitable for microcotrollers A/D coverter. Sixtee aalog chaels are the uiformly distributed betwee four microcotrollers which wor as slave devices of the master microcotroller. Slave devices fuctio is cotrolled by 8-bit bidirectioal bus DB-7 coected to rapid geeral purpose iput / output iterface (RGPIO) which is available o port F pis. About slave devices actual status is master device iformed by BUSY sigal which is active i logic high state. I this state master must wait for completio of previous operatio before ext commad will be issued. Data trasfers o parallel bus from slaves to master are sychroized by STROBE sigal idicatig valid data byte o the bus ready for trasfer. For high-speed data trasfers is utilized serial peripheral iterface () which is fully cotrolled by mai microcotroller i master mode. Operatio optios of the iterface are fully programmable so it is possible to program trasmit bit rate, serial cloc phase ad polarity, MSB first or LSB first shiftig ad other possibilities. Trasmitter ad receiver double bufferig elimiates possible character losses whe high bit rates are used. Maximum cloc frequecy i master mode is bus frequecy (f BUS ) divided by, i slave mode it is f BUS divided by 4. Serial peripheral commuicatio iterface operatio is obvious from Fig. 9. Master device, i our case microcotroller uit (), iitiates commuicatio by selectig slave device usig slave select sigal which is active i logic low level. The iterface shifts data from the iteral register to the MISO lie (Master Out Slave I) while o the SPSCK lie is geerated cloc sigal. At the same time master device receives data from the MISO (Master I Slave Out) lie. Slave select sigal is pulled high logic level whe commuicatio with slave device is doe. Commuicatio with supervisio system is provided by FT3BM USB. ad. compatible uiversal asychroous receiver / trasmitter (UART) itegrated circuit which is iteded for may applicatio areas such as: USB to RS3 coverters, smart card readers, bar code readers, USB hardware modems, USB istrumetatio ad may other applicatios. It is capable to commuicate at TTL levels with data trasfer rates up to 3 MBd. O the chip itegrated Bode Diagram Magitude (db) Phase (deg) Fig. 7 Microphoe array preamplifier schematic for oe chael Frequecy (rad/sec) Fig. 8 Filter Bode frequecy respose simulatio. Issue 6, Volume 6, 37

7 trasmit ad receive buffers with capacity of 8 B ad 384 B respectively eables high data throughput. IC operates from sigle power supply with voltage of 5 V. USB iput / output iterface is supplied from itegrated 3.3 V voltage regulator. Due to itegrated level coverter for UART I/O sigals it is possible to coect it with logic circuits operatig at 3.3 V or 5 V power supplies [3]. FT3BM is wired i maufacturer recommeded wirig for self powered applicatio with 5 V iput / output iterface. Cloc sigal is geerated exterally by crystal oscillator Q with frequecy of 6 MHz. Activity of serial iterface is idicated by two LEDs LD ad LD for receive ad trasmit mode separately. FT3BM UART sigals RxD (receive data) ad TxD (trasmit data) are crosscoected to pis TxD ad RxD of the mai microcotroller UART pis which is able to achieve commuicatio speed of up to.5 Mbits per secod at 5 MHz bus cloc. Serial iterface cotrol sigals RTS (request to sed), CTS (clear to sed), DTR (data termial ready), DSR (data set ready) except DCD (data carrier detect) ad RI (rig idicator) are coected to geeral purpose iput / output pis of the microcotroller eablig utilizatio of hardware flow cotrol i case of eed. Microcotroller s UART iterface supports full-duplex operatio utilizig stadard o-retur-to-zero (NRZ) format. Trasmitter ad receiver ca be eabled separately allowig lower power cosumptio. Their double bufferig eables high speed commuicatio without problems with received characters losses. Mai features of the UART iterface are []: Hardware parity geeratio ad checig Programmable 8-bit or 9-bit character legth Programmable baud rates Iterrupt-drive or polled operatio To the FT3BM is coected Kbit EEPROM memory 93C46 with 64 x 6b iteral orgaizatio. It is used for storage of USB vedor idetificatio (VID), device class defiitio for physical iterface devices (PID), serial umber ad product descriptio strigs. Memory ca operate at wide power supply voltages low voltage (.8 V to 5.5 V) or stadard voltage (.7 V to 5.5 V). Its coectio with UART IC is provided by 3-wire sychroous serial iterface operatig up-to MHz cloc rate at 5 V power supply. LCD display MC4B is coected to master usig 8 bit wide bidirectioal data bus coected to port D pis. LCD sigals RS, R/W ad E are cotrolled by port C pis PTC to PTC3. Baclight itesity ca be adjusted by geerated PWM sigal o pi PTG4. Variable resistor R 4 set display cotrast. Microcotrollers have oe commo exteral Pierce cloc geerator with frequecy of Hz which is i each by iteral FFL uit multiplied to 5.33 MHz cloc frequecy. This solutio grats that A/D coverters wor at the same cloc frequecy ad iteral real-time cloc has exact oe secod period. Photograph of realized evaluatio uit is i the Fig. its complete schematic is depicted i the Fig.. IV. SOFTWARE IMPLEMENTATION Microcotroller s firmware was developed with respect to their limited system resources. So all implemeted algorithms such as FFT, covolutio ad others must be fully optimized for memory usage ad computatioal efficiecy. Next problem is absece of the hardware floatig poit uit causig low arithmetic performace with this represetatio of real umbers. Due to this fact fixed poit umber represetatio was used. I this format is reserved fixed umber of bits before ad after decimal poit. Big advatage is that all operatios wor with stadard iteger arithmetic which is very fast. I our case was used Q. format which meas bits iteger bits ad fractioal bits. Software was writte i C laguage i Freescale CodeWarrior for Microcotrollers developmet studio versio 6.3 with utilizatio of Processor Expert tool [4], [9]. A. Slave microcotrollers All slave microcotrollers have exactly same firmware so software descriptio will be focused to oly oe slave microcotroller fuctio of others is idetical. After power o sequece microcotroller iitializes all ecessary iteral hardware modules such as cloc geerator module, aalog-to-digital coverter ad serial peripheral iterface. Durig these operatios is BUSY sigal set to high state iformig the master microcotroller that it is ot ready processig commads. Slave Slave Slave Slave 3 MISO MOSI SPSCK SSEL SSEL SSEL SSEL 3 Master Fig. 9 Serial peripheral iterface operatio. Fig. Photograph of the realized evaluatio uit. Issue 6, Volume 6, 373

8 Fig. Evaluatio uit schematics. Issue 6, Volume 6, 374

9 After success iitializatio process BUSY sigal is cleared ad microcotroller waits for commad for sychroized start of A/D coversios. This commad is trasferred via parallel data bus ad has code of x. After commad receptio BUSY sigal is set ad A/D coversios of the four aalog chaels are immediately iitiated. Coversios are processed at full coverter speed with bit resolutio. Samplig frequecy of each chael at maximum bus cloc frequecy of 5.7 MHz is approximately 65 Hz. Coversios are stopped whe 768 samples of each chael are stored to iteral buffers. Remaiig free space of 4 samples legth buffers is filled with zeros. The taes place FFT computatio of sampled iput sigals usig DIT algorithm ad multiplicatio of its results with 56 samples legth Fourier-trasformed bad-pass filter erel. O the multiplicatio result is applied iverse Fourier trasform resultig i bad-pass filtered iput sigals ready for ext processig. Digital filterig stage is fiished be clearig BUSY sigal. At this momet microcotroller waits for commads iitiatig partial four chael beamformig o filtered sigal. Each commad from master must cotai four bytes of data cotaiig iformatio about required time-delay applied to the correspodig chael. Results of summig off all four chaels are immediately trasferred via iterface to the master microcotroller. Beamformig stage is processed for all examied agles required by master microcotroller. It is termiated by commad cotaiig data xffffffff. The BUSY sigal is set to zero ad whole cycle is repeated at the A/D coversio start poit. B. Master microcotroller Similarly as slave microcotrollers master after power o sequece iitializes all ecessary peripherals icludig display. O the LCD is displayed mai meu from which ca user select required actio. There are three available possibilities: SW: Start locator SW: Cofigure basic parameters SW3: USB commuicatio eable At this momet microcotroller waits for user etry. If SW butto was pushed evaluatio uit is switched to autoomous localizatio mode. Microcotroller cotiuously aalyzes oe audio chael with maximum possible samplig frequecy ad waits for a audio evet which triggers localizatio process. Before localizatio process ca be started microcotroller must chec if all slave microcotrollers are ready BUSY sigals must be i low state. If so sychroized A/D coversios start commad is issued o the data bus. At this momet microcotroller waits for the completio of data acquisitio ad digital filterig stage i slave devices by moitorig BUSY sigals. Whe they are i ready state beamformig taes place. Master o the basis of microphoe array geometrical cofiguratio geerates commads for 4 chael partial beamformig ad sums results received from slave microcotrollers. From summed results of partial beamformig is computed RMS value of the sigal ad stored to the array. Whe all examied source agles are processed beamformig is termiated by sedig xffffffff commad to slave devices. Fially i RMS values array fid maximum value which idex directly idicates soud source azimuth i case of agle step variable of the algorithm is set to oe degree. Localizatio result is with audio evet time recorded to memory for future use ad the last oe displayed o the LCD. The whole cycle is repeated from the poit of waitig o audio evet. V. CONCLUSION Paper deals with desig of compact itelliget sesor for audio source localizatio with focus o telecoferecig, security ad robotics applicatios. Hardware desig is fully adapted to the high processig speed with preservatio of low power cosumptio. This was achieved by utilizatio of five Freescale ColdFire V microcotrollers each cocurretly executig part of the localizatio algorithm. Slave microcotrollers perform data acquisitio, digital filtratio ad partial four chael beamformig. Master microcotroller coordiates all evaluatio uit operatios ad does fial calculatios of acoustic source azimuth agle. It also provides commuicatio with user by meas of LCD display ad four push buttos. Implemeted USB iterface is iteded for coectio with supervisio system which ca usig simple ASCII-based commuicatio protocol cotrol device fuctios ad trasfer locator results. Evaluatio uit firmware was completely writte i C laguage i Freescale CodeWarrior IDE ad successfully tested o evaluatio uit hardware. REFERENCES [] Czeriawsi, J., Czyzewsi, A., Kroliowsi, R., Neural Computatio of Directio-Of-Arrival of Soud, Proceedigs of the 3rd WSEAS Iteratioal Coferece o Neural Networs ad Applicatios,, pp [] Freescale Semicoductor. MCF5AC56 ColdFire Itegrated Microcotroller Referece Maual [olie].. [cit. -7-]. Available o WWW: < com>. [3] Future Techology Devices Iteratioal. FT3BM USB UART IC Datasheet Versio. [olie].. [cit. -5-]. Available o WWW: < com>. [4] Doliay J.; Vase V.; Dostale P., Implemetatio ad Applicatio of a Simple Real-time OS for 8-bit Microcotrollers, I Proceedig of th WSEAS iteratioal coferece o electroics, hardware, wireless ad optical commuicatios, Steves Poit, Wiscosi, USA,, ISBN: [5] Moir. T.J., Real-time acoustic beamformig o a PC, WSEAS Trasactios o Sigal Processig, vol.. 6. World Scietific ad Egieerig Academy ad Society, pp [6] Self. D., Acoustic Locatio ad Soud Mirrors [olie]. 4. [cit. -7-]. Available from WWW: museum/comms/ear/ear.htm#steer [7] Smith, S. W., The Scietist ad Egieer's Guide to Digital Sigal Processig, secod editio. Califoria Techical Publishig, 999. [8] Texas Istrumets. Op Amps for Every Oe - Desig Referece [olie].. [cit. -7-4]. Available o WWW: < [9] Vase V.; Dostale P.; Jaacova D.; Kolomazi K.; Zalesa M., Applied Iformatics i Automatic Cotrol Educatio, I Proceedigs of the 7th WSEAS Iteratioal Coferece o Applied Iformatics ad Commuicatios, Athes, Greece, August 4-6, 7. Issue 6, Volume 6, 375