An Analog CMOS Pulse Energy Detector for IR-UWB Non-Coherent HDR Receiver

Transcription

1 W4A-3 An Analog CMOS Pulse Energy Detector for IR-UWB Non-Coherent HDR Receiver Mohamad Mroue 1,2 and Sylvain Haese 2 (1) Mitsubishi Electric ITE-TCL, Rennes, France, (2) IETR-UMR CNRS 6164, INSA, Rennes, France Tel: , Fax: , mroue@tcl.ite.mee.com Abstract This paper presents an analog circuit aimed at performing pulse detection in the Hz UWB band for MB-OOK high data rates receiver. Low cost and low power consumption are targeted. For that we especially focus on CMOS technology. The proposed pulse energy detector includes three stages: squarer, amplification and integration. Theoretical studies and SPICE simulation results in.35 μm CMOS technology are presented to validate this very low complexity approach. In particular, imperfection and mismatch effects between the squarer and amplification stages are considered. Index Terms Analog circuits, CMOS, Current amplifier, Pulse energy detector, Squarer, UWB. I. INTRODUCTION Considering Ultra Wide Band (UWB) radio link, in accordance with the American Federal Communications Commission (FCC) regulation [1], a new method of using the UWB spectrum for High Data Rates (HDR) applications has been presented in [2]. Based on Impulse Radio (IR) technique, this approach supports non-coherent processing. In that case, an On-Off Keying (OOK) modulation appears to be a suitable candidate since it possesses a good optimality regarding channel capacity [3]. The demodulation is based on non trivial energetic threshold comparison (for detailed information see [2] and [4]). To be close to channel capacity, it is proposed to duplicate this basic scheme on several separate frequency sub-bands (about 2). The adopted non-coherent receiver structure per subband is composed of a band-pass filter, a single ended input to balanced output conversion stage, a squarer, a current amplifier and an integrator (see FI. 1). The pulse energy detection includes the last three stages: squarer, amplification and integration. In section II of this paper, the transceiver architecture will be presented. A squaring architecture and a very simple amplifier design based on current mirror topology are presented in section III. Due to its very low complexity, the detector circuit maintains good performance in the Hz UWB band. Also, thanks to CMOS technology, low cost, low power consumption and reduced size chips can be obtained. Imperfection and mismatch effects are identified and studied in section I order to evaluate their effects on the detection process. Finally, SPICE simulation results are given in section V to verify the performance of the proposed pulse energy detector. Fig. 1. ± Non-coherent receiver: energy integration. II. MB-OOK TRANSCEIVER ARCHITECTURE The hardware implementation greatly benefits from the relaxed constraints offered by the non-coherent approach [5]. Firstly, only coarse synchronization is needed, which makes the system robust against clock jitter and any triggering inaccuracy. Secondly, since the treatment is based on energy, the transceiver s performances are nearly insensitive to distortion and phase non-linearity of devices like antennas, amplifiers or filters. Finally, a low power consumption is achieved thanks to the use of mainly passive analog components and of a low power architecture based on active components for the energy detection part. A. Transmitter The transmitter s architecture, depicted in FI. 2, is composed of a pulse generator, a filter bank, switches for OOK modulation, a combiner and an antenna. Covering the whole Hz band, the pulse is generated with a repetition time T r that is greater than the channel delay spread T d to prevent interference between pulses (see FI. 3). In the filter bank, the pulse is simultaneously split into an appropriate number of sub-bands (about 2 sub-bands, each one having a predefined 3-dB bandwidth of 2 to 5 MHz). Then, an OOK modulation is applied on each sub-band at the rate of 1/T r. Finally, the split pulses are combined, amplified and transmitted via an UWB antenna. B. Receiver On the receiver side (see FI. 4), a filter bank splits the signal into the same number of sub-bands as for the transmitter. Then, on each parallelized stage, a pulse energy X/6/$2. 26 IEEE 557

2 Digital data Synchronization B 1 B 1 ± ADC Pulse generation Energy splitter B 2 B n Filter bank Energy splitter B 2 B n Filter bank ± ± Studied part ADC ADC Digital processing Fig. 2. Transmitter implementation sketch. Fig. 4. Receiver implementation sketch. detector follows, whose output is sampled at a rate of 1/T r before performing an energetic threshold comparison. According to link budget studies [2], this technique is able to achieve a high data rate of 6 Mbit/s at 3 meters with 24 sub-bands of 25 MHz, T r = 4 ns and T i =3ns (1 bit/s is expected for low T d and generalized pulse amplitude modulation). An interesting feature to notice is that an easy power control in each sub-band is possible. This kind of flexibility can be useful to fulfill a regional Power Spectral Density (PSD) mask. III. PULSE ENERY DETECTOR With respect to the Hz UWB bandwidth, a pulse energy detector designed for Multi-Band OOK receiver will be presented. It includes three stages that will be studied separately. A. Squaring Stage The main constraint at this stage is the large bandwidth. Analog multipliers can in principle be used for implementing the squaring function, by connecting both inputs to the signal to be squared. But this approach needs elaborate circuitry that limits the input bandwidth. Diode detectors and circuits based on MOS transistors are well-known components that offer square-law non-linear behaviors over wide bands. We can also notice that, usually, circuits with simple architecture have a better capability to operate over large bandwidths. Diode detectors are used to detect small signals close to the noise level [6]. The performance of Schottky diode detector is heavily dependent on its saturation T i T d T r Fig. 3. Repetition time (T r), delay spread (T d ) and integration time (T i ). current, which in turn varies a lot with temperature. At both low and high temperature extremes, this dependence can lead to degradation in performance. Compensation methods for high and low temperature exist [6] [7], but it complicates the circuit design. A MOS transistor detector is less dependent on temperature variations. It presents a better detection sensitivity and the output voltage is directly available without subtracting the bias voltage. The effective noise voltage of the diode detector is four times as high as the MOS transistor noise level [8]. Also, Schottky diodes are not widely available in standard CMOS technology. The advantages of the CMOS technology are that it permits to integrate both analog and digital functions in the same chip. It provides chips with low cost, low power consumption and reduced size. For that, it seems reasonable and preferable to design a squarer based on MOS transistors. A MOS transistor provides a non linear current voltage I-V characteristic. The drain current of a MOS transistor has a large square-law characteristic in both saturation and triode operation regions. 1) Squarer in the saturation region: There are many analog circuits in the literature which synthesize analog functions exploiting the square law transconductance characteristic of the MOS transistor in the saturation region, which can be expressed by the following relation: I DS = K(S V T ) 2 (1) K = 1 W 2 k n (2) L where k n is the process transconductance parameter, W is the induced channel width, L is the induced channel length, S is the gate to source voltage and V T is the threshold voltage. However, the procedure is complicated by the threshold term which introduces linear and offset terms into the basic arithmetic, and also by the limited range of the saturation region. A particular squarer architecture operating in the saturation region, based on Floating ate MOS transistors, has been proposed in [9] and [1]. When included in a squarer circuit [1], the FMOS transistor needs an appropriate adjustment of the bias voltage of an input gate, so that the S window can be shifted within 558

3 the supply rails to achieve the maximum input range and the minimum non linearity. Maintaining this bias voltage creates additional energy consumption. The main drawback is that the capacitive effect is not easy to control in FMOS transistors and it largely affects the output squared signal [1]. Also, the multiple floating and fixed gates need to be properly isolated. 2) Squarer in the triode region: Squarers based on MOS transistors operating in the triode region easily implement input and output signals with the same bias levels without additional circuits. The drain current I D of a MOS transistor, biased with a drain to source voltage V DS around zero in the triode region, can be expressed by the following Taylor series [11]: I D = K + i=1 a i (V i D V i S ) (3) where V D and V S are the voltages on the drain and source respectively, K is given in (2), and the a i coefficients are functions of the transistor parameters, gate bias, and substrate bias [11]. For typical processes and signal levels, the second-order term is larger than any of the higher order terms. Based on the transistor equation given in (3), a square law function can be implemented using two MOS transistors, and (see FI. 5) [11]. The role of these two transistors is to provide an output current proportional to the square of the input voltage. If the circuit is driven by balanced signals and, and when the drain voltage is maintained at zero Volt, the sum of the output drain currents and can be expressed by: I squarer = 2K[a 2 Vin 2 + a 4Vin ] 2Ka 2Vin 2 (4) Use of balanced signals and matched transistors causes the linear term to be suppressed as well as all the high-order odd terms. The approximation shown in (4) can be made because the second-order term is typically much larger than the remaining even-order terms [11]. Due to the simple squarer design, the broadband functionality of MOS transistors is preserved. Also, this architecture can be directly integrated in standard CMOS technology. For that reason, this approach has been retained to realize the pulse energy detector of the high data-rate UWB architecture. B. Amplification Stage The main purpose of this stage is to maintain the best isolation between the squarer and the integrator in order not to perturb the squared signal. It must also provide an input bandwidth of at least 5 MHz to let the useful part of the squared signal pass to the integrator unaffected. An operational amplifier can be gathered with a resistor and the two MOS transistors to form a squarer as explained in [11]. But this approach has several drawbacks. Firstly, the resistor is an undesirable component because it usually introduces unwanted additional nonlinearities. Secondly, state-of-the-art low power operational amplifiers do not have a sufficient input bandwidth to guarantee a good functionality. In addition, they may be quite complex. Another method consists in working with current amplifiers. They provide better performance at higher frequencies compared to conventional voltage amplifiers. Based on simple current mirrors, these circuits have reduced complexity and they are easy to implement. Also, low voltage and low power consumption can be achieved [12]. Our approach consists in adding a current amplification stage to the two MOS transistors. Thus the amplifier will have an open-loop functionality. This current amplifier is composed of 4 PMOS transistors and 4 NMOS transistors operating in the saturation region [12]. The design of this stage is shown in FI. 6 and the equivalent equation is given by: I amplifier = I in (5) where I amplifier is the output current, I in is the input current and is the current gain which is determined by the dimensions of the mirror transistors. = (W/L) MN i (W/L) MNj = (W/L) MP i (W/L) MPj (6) where N-type transistors MN i correspond to MN 1 and MN 2, MN j correspond to MN 3 and MN 4. P-type tran- I bias MP 3 MP 4 V DD MP 1 MP 2 I in I amplifier MN 3 MN 1 I squarer MN 4 MN 2 V SS Fig. 5. Squarer architecture. Fig. 6. Current amplifier architecture. 559

4 sistors MP i correspond to MP 1 and MP 2, MP j correspond to MP 3 and MP 4. Finally, the output voltage is collected by adding an analog passive component (see FI. 7). C. Integration Stage After the squaring operation, the information is contained in the baseband signal. So the integrator has identical pass-band for all parallelized stages. Integration is realized by a capacitor as depicted in FI. 7. Its capacitor output voltage V C is given by: T V C (t) = 1 I C (t)dt + V C () (7) C where, C is the capacitor value, I C is the capacitor input current, V C () is the capacitor voltage for t =. To realize a proper integration function by setting V C () to zero, the capacitor must be discharged after each integration cycle. For that, a switch made of MOS transistor can be added in parallel to the capacitor. this biasing current and the supply voltage V DD are related to each other almost linearly for operation in the saturation region [12]. The circuit depicted in FI. 9,wherethe two MOS transistors are followed by a resistance R, can be used to study the effects of the amplifier s equivalent input impedance. Based on the Taylor series given in (3) with V D = RI R and when R>1/(2Ka 1 ), the resistance current I R can be expressed by: where the first two b i are: I R = b 1 Vin 2 + b 2Vin (8) b 1 = 2Ka 2 (2Ka 1 R 1) b 2 = 8(Ka 2) 3 R 2 (2Ka 1 R 1) 3 (1) where, a 1 and a 2 are given in [11]. Also, a 1 is typically much larger than a 2 [11], so we can deduce that: (9) I R b 1 V 2 in (11) V DD V SS I C C V C This shows that the imperfections caused by the equivalent input resistance of the amplifier do not affect significantly the shape of the signal. Depending on its value, the squared signal is either amplified or attenuated. This can be controlled by adjusting the biasing current I bias. The approximation shown in (11) can be made because the first-order term is typically much larger than the remaining terms. Fig. 7. Pulse detector: output current and output voltage. IV. IMPERFECTIONS AND MISMATCH EFFECTS This section is dedicated to studying the effects of the amplifier s imperfections and mismatches on the squarer s performance and to propose ways to compensate them. The effects correspond to an input and output offset voltage and an input equivalent resistance at the amplification stage (see FI. 8). (I iɛ,v o) I oɛ R B. Mismatch Effect Study The current amplifier is designed with differential supply voltages (V DD = V SS ). Both input and output nodes are set to zero DC voltage level to facilitate direct interconnection with other stages, especially the squarer one. Maintaining zero DC voltage at both extremities requires a perfect control of the MOS transistors dimensions that form this current amplifier. However, during the fabrication process, MOS transistors dimensions and process parameters may slightly vary. This causes that both extremities of the amplifier are not exactly set to zero DC voltage. When connected to the squarer stage, it is important to evaluate the impact of the amplifier s input offset voltage V o on the squared signal. Fig. 8. Imperfection and mismatch effects. I R A. Imperfections Effect Study The problem of imperfections appears especially between the squarer and the amplification stage. The squared signal can be affected by the amplifier s equivalent input resistance, which depends on its biasing current I bias.also, Fig. 9. Squarer architecture: equivalent resistance effect. R 56

5 Fig. 1. I V Squarer architecture: offset voltage effect. The equivalent circuit in FI. 1 can be used in that purpose. It features a DC voltage source V o at the squarer stage output. Then, the output current I V can be given by: where, I V I iɛ 2Ka 2 V 2 in (12) I iɛ =2K[a 1 V o + a 2 V 2 o + a 3V 3 o +...] 2Ka 1V o (13) The approximation given in (13) can be made because the first-order term is typically much larger than the remaining terms [11]. Hence the shape of the squared signal is not significantly affected, only an offset current appears. Since the squarer is composed of two MOS transistors operating in the ohmic region, it can be seen by the amplifier as an equivalent resistance. This explains the offset current I iɛ that appears in (12) when the input node of the amplifier is different from zero DC voltage. I iɛ causes at the amplifier s output a current I oɛ1 = I iɛ. Similarly, an additional offset current I oɛ2 appears at the output of the current amplifier in the same condition as I iɛ (see FI. 8). Then, the global output offset current is given by: I oɛ = I oɛ1 + I oɛ2 (14) Also, the two MOS transistors of the squarer stage must be properly matched in order not to distort the squared signal. The global output offset I oɛ will affect the integration. Some additional procedure is required to eliminate this undesirable offset current. The offset current can be evaluated by setting the squarer s inputs to zero. It can then be compensated in further digital processing steps. Vo Squarer (W/L) 1,2 4/.35 Current amplifier 1.2 V 2 V 1 (W/L) N 6.2/.35 (W/L) P 4/.35 V DD V SS I bias 3-dB Bandwidth Input resistance Power dissipation C Integrator 2 V 2 V 126 μa 1.18 Hz 1.37 kω 1 mw.5 pf TABLE I. Circuit and performance parameters. The squarer stage has been simulated alone in a first step to evaluate the performance of the proposed detector in the Hz UWB band. The results were compared to the same pulse signal squared by an ideal multiplier. As can be seen from FI. 11, the relative error remains lower than 1% in the whole UWB band. Based on circuits given in FI. 9 and 1, the imperfection and mismatch effects were simulated separately. A pulse with Hz band was used. Results for mismatch effects have been obtained after deducting the constant offset current. Simulation results shown in FI. 12 and 13 confirm that the shape of the squared signal is not significantly affected. As can be seen from FI. 14, the offset voltage and the offset current are related to each other almost linearly. This justifies the approximation made in (13). Finally, the global pulse energy detector, shown in FI. 7, was simulated in the time domain. The output current and voltage at the capacitor in the integration stage are shown in FI. 15. CONCLUSION This paper has presented a pulse energy detector architecture for an IR-UWB non-coherent high data rates receiver composed of three stages: squarer, amplification and V. SIMULATION RESULTS In this study, antenna effects and signal distortion in the channel were not considered. To evaluate the performance of the proposed structure, three filter banks ( Hz, Hz and Hz) were designed under Agilent ADS TM software, each one composed of 4 elliptic response bandpass filters with a 3-dB bandwidth of 25 MHz [5]. The circuit was simulated with a pulse at the input of each sub-band. The proposed Pulse Energy Detector was designed and simulated by using SPICE simulator with process parameters of a.35 μm standard CMOS technology. The circuit parameters are given in TABLE I. Fig. 11. Relative error (%) Frequency (Hz) Relative error versus frequency. 561

6 Relative error (%) R (kω) Fig. 12. Error of the squared signal with equivalent input resistance R relatively to the ideal case (R =Ω). VC (mv ) IC (μa) Vin (V ) Time (ns) Relative error (%) V o (mv ) Fig. 13. Error of the squared signal with offset voltage V o relatively to the ideal case (V o =V ). integration. It offers the advantage of having a very low complexity design and thanks to CMOS technology, low cost, low power consumption and reduced size chips can be obtained. Mismatch and imperfection effects were defined and evaluated. Theoretical studies led us to deduce that these effects only slightly affect the shape of the squared signal. Mismatch effects introduce a constant offset current that can be evaluated and later eliminated by a simple procedure. Also the amplifier s input equivalent resistance has almost no effect on the squared signal shape, but its value determines the squarer s gain. SPICE simulation re- Iiɛ (μa) V o (mv ) Fig. 14. Input offset current I iɛ versus input offset voltage V o of the amplification stage. Fig. 15. Input voltage, output current I C and output voltage V C of the pulse energy detector in the Hz sub-band. sults of the pulse energy detector architecture in.35 μm CMOS technology have shown the efficiency of this design in the Hz UWB band. ACKNOWLEDMENT The authors wish to sincerely thank S. Paquelet from Mitsubishi ITE for his valuable participation in the theoretical developments and S. Mallégol from Mitsubishi ITE for his contribution in the filter bank design and simulation. Also, the authors wish to thank A. Bisiaux from Mitsubishi ITE and. El-Zein from IETR for their support. REFERENCES [1] Federal Communications Commission; "First report and order," ET Docket, No , Apr. 22, 22. [2] Paquelet, S.; Aubert, L. M.; Uguen, B.; "An Impulse Radio Asynchronous Transceiver for High Data Rates," UWBST & IWBS, Kyoto, 24. [3] Verdú, S.; "Spectral efficiency in the wideband regime," IEEE Trans. Info. Theory, Vol. 48, No. 6, Jun. 22, pp [4] Paquelet, S.; Aubert, L. M.; "An Energy Adaptive Demodulation for High Data Rates with Impulse Radio," RAWCO4, Atlanta, Sep. 24. [5] Doré, J. B.; Mallégol, S.; Paquelet, S.; Aubert, L. M.; Uguen, B.; "UWB Non-Coherent High Data Rates Transceiver Architecture and Implementation," IWCT Conference, Jun. 25. ( Mallegol.pdf) [6] Agilent Technologies; "Square law and Linear Detection," Application Note 986. [7] Agilent Technologies; "The Zero Bias Schottky Diode Detector at Temperature Extremes - Problems and Solutions," Application Note 19. [8] Ratni, M.; Huyart, B.; Bergault, E.; Jallet, L.; "RF Power Detector Using a Silicon MOSFET," IEEE MTT-Sdigest, ENST Paris, [9] Vlassis, S.; Siskos S.; "Differential-Voltage Attenuator based on Floating-ate MOS transistors and its applications," IEEE Trans. Cir. & Sys. I: Fund. Theory & Appl., Vol. 48, No. 11, Nov. 21. [1] Vlassis, S.; Siskos S.; "Analog Squarer and Multiplier based on Floating-ate MOS Transistors," Elec. Lett., Vol. 34, No. 9, Apr [11] Khoury, J.; Nagari, K.; Trosino, J.; "Sampled-Data and Continuous- Time Squarers in MOS Technology," IEEE J. Sol. St. Circ., Vol. 25, No. 4, Aug [12] Souliotis,.; Chrisanthopoulos, A.; Haritantis, I.; "Current Differential Amplifiers: New Circuits and Applications," Int. J. Circ. Theory & Appl., May