STT READOUT MEETING 25 MAY 2018 PETER WINTZ

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Morgan Fleming
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1 STT READOUT MEETING 25 MAY 2018 PETER WINTZ

2 TOPICS TODAY Overview Decision Process General Readou Saus Sysem Compleion & Resources Individual Saus Repors (ADC) Discussion: Messages a nex CM p. 2

3 DECISION PROCESS OVERVIEW Finances & resources planning for STT & FT sysems a Day 1 (2023) ongoing STT/FT saus repors a CMs and o PANDA officials (Mar/Apr/May/June) STT sysem Complee sysem se up for day 1 sar Open WPs idenified (mech. sysem, gas sysem,..) Cos consolidaion done (e.g. readou sysems, synergies,..) Decision abou final STT readou will be done by PANDA-C Clear readou saus repors, open poins & nex plans needed Inpu from us for he decision High ransparency of decision waned, solid ground for accepance Implicaions for PANDA experimen (FE-layou, PID performance,..) Decision required in June/July p. 3

4 STT COST TALE Requesed by PANDA officials and repored a CM 18/1 Furher ieraion ongoing (open WP,..) Readou sysem cos able se up wihin he wo working groups in February Mainly producion & insallaion & mainenance coss, no re-design STT Work Package / Coss (T EUR) Updae (2018) Risk Synergy Savings Responsible Insiuions RO #1 RO #2 FT Phase0 FZJ Krakow IFIN 3 Elecronic readou 3.1 ASIC/TR ASICv1/FEv1-v3 Design PASTTRECv1/FEv3 (4800 ch) FE-layou/cooling/HV-boards Readou oard/crae: TR3, LVDS Cable, daa links 78 DaaConcenraor 10 TRx/DaaConc for full lumi 100 ASIC/FPGA Mainenance/Lab ADC-based Cables/HV-decoupling 180 Readou oard/crae Amp/ADC/FPGA/DaaConc FPGA Mainenance/Lab 70 p. 4

12x links ASIC/TR READOUT STT-specific ASIC PASTTRECv1 (AGH & JU Krakow) FEv3 for STT developed (small size, low power)

s 1 1 x li n k s Slav eslav Slav TRe e TR TR 11 Slav eslav Slav TRe e TR TR 11 12x link s Scheme by Greg. K.

5 12x links ASIC/TR READOUT STT-specific ASIC PASTTRECv1 (AGH & JU Krakow) FEv3 for STT developed (small size, low power) TR3 sysem wih FPGA-ASIC conrol (SW) Daa concenraor sage in progress (commercial HW) PID by ime-over-hreshold TR3 inegraion ino PANDA-DAQ (SODANe sync.) PANDA-DAQ (CN) se up: sraws (TR3) & EMC (ADC) HARDWARE SETUP ESlow Conrol Gb Sou rce SODANe TR SODANe TR 1 1 x li n k s 1 1 x li n k s Slav eslav Slav TRe e TR TR 11 Slav eslav Slav TRe e TR TR 11 12x link s Scheme by Greg. K. urs uilding Nework 4x 48 channels urs uilding Nework 132x FEE (2112 ch) 132x FEE (2112 ch) Rack1 Rack2 FEv1 FEv mm 2 STT FE-layou Sraw (256ch, TR3) & EMC (3x3 crysals, ADC) & PANDA-DAQ (3 CN) es seup in Krakow p. 5

6 Isochrone residual (µm) TESTEAM RESULTS ASIC/TR ToT / dx (ns/mm) P. Winz, IKP FZJ Deueron 2016, Ar/CO2(10%) Deueron 2018, Ar/CO2(20%) Proon 2018, Ar/CO2(20%) Proon 2018, Ar/CO2(20%), diff. ASIC seing (gain 2) Design goal P. Winz, IKP FZJ Hi filer (~ 15% -elecr...) P / Mc P / Mc ToT resuls (deueron, proon beam & cosmics) S ~ MeV/c, TDR: S ~ 5) S ~ MeV/c, TDR: S ~ 8) S ~ 9 ( 300 MeV/c, TDR: S ~ 13) All TDR separaion power w/ 10% de/dx resoluion ~ 60-70% of TDR separaion power reached by ToT u: low runcaion ye, can rea resuls as lower limis / mean ( ToT/ dx) (%) P / Mc Goal (?) P. Winz, IKP FZJ p. 6

ADC-ASED READOUT STT-specific, non-sandard scheme: fronend elecronics-free HV & signal on same coax line, sraw access from backend (cu off opion) FE-layou: no cooling, low ma.

FPGA (Xilinx Virex7) Daa concenraor sage as Add-on board (hi soring) 160ch readou board, double-sided, wih 2x20 ADC, 1x cenral FPGA (crae fron side) Componens esed in April (in-beam)

7 ADC-ASED READOUT STT-specific, non-sandard scheme: fronend elecronics-free HV & signal on same coax line, sraw access from backend (cu off opion) FE-layou: no cooling, low ma. budge, less space required RO board design by FZJ/ZEA-2, sysem scheme by IFJ PAN/IKP Op-amps, waveform sampling ADC ( MSPS, 12 bi) WF-readou & signal processing by cenral FPGA (Xilinx Virex7) Daa concenraor sage as Add-on board (hi soring) 160ch readou board, double-sided, wih 2x20 ADC, 1x cenral FPGA (crae fron side) Componens esed in April (in-beam) 160ch amplifier board (crae rear side) HV board HV decoupling Processing board Rear uni Fron uni Add-on board Communicaion Sraw ubes ~8m coax HV supply ribbon cable Op-amp shaper 40 ADCs + FPGA p. 7

8 Enries TESTEAM RESULTS ADC-SYSTEM Resuls for FADC (240 MHz) prooype sysem (and direc sraw cabling) Raw mode readou wih full WF informaion, no real-ime FPGA pulse analysis Example: separaion of 2.95/0.55 GeV/c proons: S ~ 8.5 Trea prelim. resuls of S as upper limi (?) New SADC (160 MHz, 12 bi), Op-Amp board brough ino operaion in April ToDo: Op-amp dynamic range o be esed (5-50 kev/cm) ToDo: real-ime FPGA readou, daa sream oupu (HW) K. Pysz (IFJ PAN Krakow) K. Pysz, K. IFJ Pysz Krakow (IFJ PAN Krakow) de/dx (arb. unis) p. 8

9 SYSTEM COMPLETION ESTIMATE ASIC/TR3 Readou Remaining WP lis (min.) Resources (FTE/a) FE-mech. layou / cooling, HV disr., cable rouing scheme 1 Daa concenraor sage (HW seleced) & PANDA-DAQ inegraion 0.5 Real-ime FPGA programming (hi soring, daa concenr., racking,..) 0.5 ASIC, FE-board & FPGA mainenance, design & es lab 1.5 Tracking & PID SW algorihms (offline), es daa analysis 0.5 Toal: ~ 4 FTE/a + (>) 2 PhD ~ -1 FTE synergy wih Forward Tracker (ASIC/FPGA/DAQ) TRx for phase 3, addiional cos incorporaed in cos/resource able TR3 & PANDA-DAQ (CN) es sysem se up, in-beam ess nex (sraws & EMC) STS@HADES seup, ~1800 channel ASIC/TR3 sysem under exp. condiions p. 9

10 SYSTEM COMPLETION ESTIMATE ADC-based Readou Remaining WP lis (min.) Resources (FTE/a) Analog signal par, final cable rouing / hv-supply, insallaion 1 Final Amp/ADC board design & producion 0.5 Communic. board design & producion, PANDA-DAQ inegraion 0.5 WF processing and readou in real-ime (FPGA) 0.5 Pre-series sysem se up, esbeam measuremens 1 Real-ime FPGA programming (hi soring, daa concenr., racking,..) 0.5 Sysem HW & FPGA mainenance, design & es lab 1 Tracking & PID SW algorihms (offline), es daa analysis 0.5 Toal: ~ 5.5 FTE/a + (>) 2 PhD ~ 1 more year (x 4.5 FTE) for compleion & commissioning of pre-series sysem ~ 2 weeks esbeam ime wih de/dx range 5-50 kev/cm p. 10

11 GENERAL REMARKS Spaial (isochrone) resoluion beer han design goal ( = 150µm) expeced for boh readous, same calibraion & racking mehods PID capabiliy demonsraed for boh readous by in-beam ess eer PID expeced for ADC (pulse area pulse widh), bu o be demonsraed in-beam over full de/dx range (pulse shape disorion by amp/shaper expeced) FTEs for work packages no (fully) assigned, EoIs of insiuions exising (parly) MoUs required o esablish WP planning owards STT insallaion Manpower siuaion criical, remains challenging (saff & sudens) Lab capaciies criical (personnel) Experience loss insead of experience build-up, coninuaion of WP difficul Addiional ousourcing of WPs migh be required (e.g. cabling, solder work,..) Temporary personnel o be se up (suden courses,..) p. 11

12 DISCUSSION p. 12

ASIC/TRB Readout Status in Jülich

ASIC/TRB Readout Status in Jülich Peter Wintz (IKP, FZ Jülich) STT RO WShop, Krakow, Jan-30/31 2016 Outline: ASIC/TRB Readout Status in Jül WPs in Jülich System overview Production status Readout status