AMCHIP5 characterization tests

Transcription

1 AMCHIP6 status

2 AMCHIP5 characterization tests Characterization results demonstrate the functionality of the 2 Gbit with a single event and by using the XORAM cell LV_cell seems to have some issue of metastability XORAM cells have been chosen for the AMCHIP6

3 AMCHIP5 tests: TODO list Tests is still ongoing o different temperatures o different power supply ( 10%) Some preliminary tests: some 930 mv (typical case is 1.0 V) MUST investigate it!

4 Foundation flow (place & route)

5 Design complexity mm x mm about 421 millions of transistors 20.5 millions of standard cells Total wire length: about 357 meters 964 pads 4096 XORAM block (full-custom design) transistors 22.4 knets

6 Design complexity vs CPUs mm x mm about 421 millions of transistors 20.5 millions of standard cells Total wire length: about 357 meters 964 pads 4096 XORAM block (full-custom design) transistors 22.4 knets Core 2 Duo Conroe 291,000, Intel 65 nm 143 mm² Itanium 2 Madison 6M 410,000, Intel 130 nm 374 mm² Core 2 Duo Wolfdale 411,000, Intel 45 nm 107 mm² AMCHIP6 421,000, FTK 65 nm 168 mm² Itanium 2 with 9 MB cache 592,000, Intel 130 nm 432 mm² Core i7 (Quad) 731,000, Intel 45 nm 263 mm²

7 Place & Route (Backend) approach Hierarchical approach (bottom up) o needed to reduce computation time Two main block exists: o 2k-pattern block instantiated 64 times o top block Three place & route flow are needed: o one for 2k-pattern block o o one for top block one for the assembled design

8 Place & Route approach Serializer - Deserializer 2k-pattern block

9 2k pattern layout XORAM full custom block containing 64 half patterns Power supplies (VDDfc, VDDcore, and VSS) are routed in vertical stripes

10 2k pattern routing Foundation Flow for this block has been completed! Static timing analysis met the timing constraints

11 Design complexity reduction Standard cell count: o TOP block: 3092 kcells o 2k block: 272 kcells o TOTAL: 20.5 millions Total wire length: o TOP block: 47.5 m o 2k block: 4.8 m o TOTAL: about 357 m

12 AMCHIP: place & route automatic design Hierarchical approach: o o o 2k pattern block: OK TOP with 2k pattern black box: almost OK TOP assembled with the 2k pattern block: may be problematic for the high complexity

13 Simulation power consumption XOR-RAM 1V baseline, leakage (ma) clock distrib (ma) std cell, not bitline prop (ma) bitline propagation (ma) This values have been confirmed by the test measurements!! clock prop. XORAM (ma) SRAM consumption (ma) Total (ma) Voltage (V) Total (W) alfa factor (96%) correction

14 Digital simulation for the validation Computation time with ncsim: o 33 hours for running 4k pattern events o 5 or 6 hours to find bugs

15 We are waiting from ASE + IMEC In last days we submit to IMEC: the dummy tape out to fit the reticle of the wafer: OK the project for a further ESD review the bump assignment for the package (substrate) quotation

16 TODO Design (Milano + Parigi): Run place & route foundation flow in Encounter: 3 weeks o implementation, timing static analysis, time delay extraction Run analog and Encounter Voltus Software (IR drop and electromigration) simulations: 2 weeks Run digital back-annotate simulations: 1-2 weeks DRC & LVS: few days Fabrication (IMEC + ASE + TSMC): Design of package substrate : 2 weeks Assembly: 4 weeks Tooling: 8 weeks Die fabrication: 4 weeks Tests (Milano + Frascati): Chip characterization: 8 or more week Repetitive Tests (20k chip): IMPORTANT contact industry (e.g. Microtest) 8 or more weeks

17 Gantt s diagram

18 Schedule for tests 1) To define a strategy for PRR (production readiness ATLAS Feb ) Contact industry for repetetive tests of 20 kchips before to get the chip at home

19 Backup More technical details

20 First chip floorplan chip size: um x um # of IOs cells: Deserializer (DES_0625TS65LPSSCG) + Serializer (SER_0625TS65LPSSCG) = 11 VDDA = 11 VDDH = 11 VSSS = 22 RX = 20 TX = 2 Single-ended (PDDW0204SCDG) = 10 Analog IO (PDB2A) = 2 clk = 2 Digital power core (PVDD1CDG) = 338 VDDfc = 159 VDDcore = 167 VDDserdes = 12 Digital ground core (PVSS3CDG) = 461 VSS = 461 Digital power IO (PVDD2CDG) = 93 VDDIO = 93 Analog power core (PVDD3A) = 2 VDDA_BGREF = 1 VDDA_LVDS = 1 Analog ground core (PVSS3A) = 3 VSS_BGREF = 1 VSS_LVDS = 2 (come/perche scalano con i consumi?)

21 Bump feature Eutectic ball has been chosen o Library is APRDL o The cell is PAD90APB (diameter = 90 um) Problem: is too small to guarantee the minimum density of Under Ball Metal (UBM). Density across full chip >= 0.09 Real value is only we will move on the more large ball PAD108APB (diameter 108 um) the array: o is a full matrix array with 22 rows and 36 columns o has been created on the core area (coord LL: -70.0,0 UR: 14680,10890) o has a bump pitch of 400 um (horizontal) and 480 um (vertical) o has a edge spacing of dx = 360 and dy = 400

22 First bump assignment Number of bumps: VSS = 313 VDDfc = 206 VDDcore = 199 VDDserdes = 4 VDDA = 6 VDDH = 6 VSSS = 18 VDDA_LVDS = 1 VSS_LVDS = 1 VDDA_BGREF = 1 VSS_BGREF = 1 differential = 24 single-ended = 10 TOTAL = 792

23 last bump assignment VDDcore VDDH + VDDA VSS + VSSS VDDfc VSS VDDcore VDDcore Number of bumps: VSS = 524 VDDfc = 313 VDDcore = 271 VDDserdes = 3 VDDA = 8 VDDH = 6 VSSS = 15 VSS VDDfc VSS VDDcore VSS VDDA_LVDS = 1 VSS_LVDS = 1 VDDA_BGREF = 1 VSS_BGREF = 1 differential = 24 single-ended = 10 TOTAL = 1178 VDDfc

24 Maximum density current AP is I max = 2.7 * width [ma] Mz is I max = 8 * width [ma] Mx is I max = 1.8 * width [ma] M1 is I max = 1.5 * width [ma] RV (via between AP & M6) is I max = 7 per RV Vx I max = per via Vz I max = per via

25 Max current density per bump current [ma] number of bumps current per bump [ma] max current per bump VDDA VDDH VSSS VDDcore VDDfc VSS VDDserdes negligible VDD_LVDS negligible VSS_LVDS negligible VDD_BGREF negligible

26 First power routing approach Power routing ring between IO cells and core composed by 3 M6 stripes (9 um): VSS VDDcore VDDfc Ten horizontal AP stripes (35 um - spaced of 2 um) between bumps Different vertical connection towards and from bumps (cluster with groups of 4 or 2 bumps)

27 Power routing approach Five RV (vias); Inside a 2k pattern block: 13 stripes - M6 (1 um) for VDDcore 8 stripes - M6 (9 um) for VDDfc 5 stripes - M6 (9 um) for VSS The connection from/to the cell arrays is made upon the horizontal routing channel in M6 We place VSS VDDcore VDDfc alternatively: max distance from RV via = 3 blocks of 2k pattern cells =927 um (block height) um (horz-routing channel height)

28 Update power consumption estimation Calculation with the first floorplan has be made with the typical case simulation multiplied x2 or Worst-power + 50% - run analog simulations with the aim to estimate fullcustom block power (RMS, peak) - scale stripes width by considering peak and average (peak between RMS and max/10) - Run power consumption simulation from Encounter Power software (IR drop & electromigration analysis)

29 PClamp After the review with IMEC. Gabriel suggest us to place ESD diodes among bumps. Strict rule: less than 0.1 Ohm from bump PCLAMP cell!

30 PClamp After the review with IMEC. Gabriel suggest us to place ESD diodes among bumps. Strict rule: less than 0.1 Ohm from bump PCLAMP cell!

31 PClamp After the review with IMEC. Gabriel suggest us to place ESD diodes among bumps. Strict rule: less than 0.1 Ohm from bump PCLAMP cell!

32 Thermal sim Slide of Bart Cox will be upload for the end-of- November s review

33 Package AM05: HSBGA wirebonded chip AM06: HFCBGA flip chip Thermally enhanced FCBGA, is the composite package of FCBGA with heatspreader made of Cu, Al, or AlSiC. This method desensitizes the performance deviation out of the chip size, lowers the thermal resistance of junction-to-case and enables the external heat sink or fan to work more effectively. HFCBGA can produce 6~8 watts of power dissipation under natural convection. Task of IMEC & ASE

34 Maximum die size vs package For the HSBGA 23x23 wirebond, the maximum die size is 12x12mm. For the HFCBGA 23x23 -flip chip, the maximum die size is 15.6x15.6mm, so it will be okay for AM06. Our last Floorplan is: um x um HFCBGA is the unique solution also by considering the thermal dissipation

35 Ball assignment Is very different from bump assignment Dummy tape out and substrate estimation under work by IMEC We would like to maintain the same assignment of AMCHIP05

36 Maximum current per ball and bump The maximum current for the BGA 23x23, ball diameter at 0.45mm is 2.23A The maximum current for the bump of 108 um is 200 ma. For AM06, the maximum current estimation is 75 ma per ball and 32 ma per bump, it is still safe within the spec limit.

37 Layout routing details

38 Layout details VSSS isolations for LVDS links

39 JTAG and controls routing

40 Clk and BGref routing