Digital Current Mode Control for Buck-Converter Based on Average Inductor Current Measurement

Transcription

1 ranacion on Elecrical Engineering, Vol. (), No. Digial Curren Mode Conrol for Buck-Converer Baed on Average Inducor Curren Meauremen Miro Milanovič ), Mija runič ), ine onjedic 3) ) Univeriy of Maribor FERI, Maribor, Slovenia, milanovic@uni-mb.i ) Univeriy of Maribor FERI, Maribor, Slovenia, mija.runic@uni-mb.i 3) Univeriy of Maribor FERI, Maribor, Slovenia, ine.konjedic@uni-mb.i Abrac hi paper inroduce a digially performed curren mode and volage conrol for he dc-dc ep down converer baed on volage o frequency converer where he average value of inducor curren and oupu volage are obained. hee curren and volage meauremen are realized by he volage conrol ocillaor (VCO) and couner (digial inegraor). Such an approach enable full digializaion of curren and volage conrol loop. hi paper explore a curren mode conrol for a dc-dc buck converer baed on he average value of he inducor curren meauremen, by uing a volage-conrolled ocillaor eyword DC-DC converer, converer conrol, curren conrol I. INRODUCION Digially conrolled pule-widh modulaion (PWM) converer have many poenial advanage, including programmabiliy, ineniiviy o parameer variaion, reducion of exernal paive componen, a well a he poenial o apply more advanced algorihm for he conrol and proecion. When uing microproceor he compuing capabiliie are no fa enough o calculae he neceary ime criical calculaion for he conrol algorihm during he wich period. Laer, advance in digial echnology promped ome reearch group o ue Field-Programmable Gae Array (FPGA ) or Digial Signal Proceor (DSP ) [], [] and [3]. In he curren mode, he wich or he inducor curren i ened wihin an inner loop and replace he convenional awooh waveform when generaing he Pule Widh Modulaion (PWM) funcion. Such algorihm were ued wihin he domain of he analogue oluion bu recenly, ome algorihm were mainly developed baed on an inananeou curren meauremen and predicion raegy [4], [5]. According o digial approach in order o olve DC-DC converer conrol funcion i mu be noed ha he digial conroller ample he ened curren a lea wice in wiching period and he acual rajecory of he inducor curren i unknown o he conroller. According o digial conrol approach he curren mu be ampled a lea wice during he wiching period in order o olve DC-DC converer conrol funcion wherea he acual rajecory of he inducor curren i i unknown o he conroller. Some reearch work wa done in digializaion area where predicion mehod wa ued. he inducor curren ha been ampled a lea wice, when he curren wa riing (wihin on inerval) or falling (wihin off inerval) a wa dicued in [4]. By uing uch algorihm he peak or valley curren-mode conrol could be applied. Figure. (a) he buck converer chema - analog archiecure; (b) he buck converer chema - curren-mode analog archiecure; (c) curren modulaor-analog oluion; (d) curren-modulaor, digial oluion and digial couner for he inducor curren meauremen. he algorihm wa inveigaed heoreically and verified by imulaion and experimenaion. II. PRINCIPLE OF OPERAION he block diagram of a cacade conrolled buck converer and analog curren mode conrol chema i hown in Fig. (a) and (b) repecively. he curren reference i ref i obained a an oupu of he volage conroller. Beer dynamic repone can be achieved by he ue of currenmode conrol chema. he convenional PI conroller and he aw-ooh waveform generaor (Fig. (a)) which i ued o generae he PWM ignal i replaced wih he inner curren loop. Replacemen of he inner curren loop Fig. (b) i done by he inroducion of he wich (i w ) or inducor curren (i L ) which i compared o he curren reference ignal. he reuling ignal i led o he R-S flipflop in order o generae he riggering pule for he ranior (PWM ignal). For he digial implemenaion he rucure of Fig. (b) canno be direcly ued. he digializaion principle, which will be conidered here, enable and/or provide he curren informaion alo during he ampling inerval. he new digial principle of curren

2 ranacion on Elecrical Engineering, Vol. (), No. - mode conrol i propoed in Fig. (d). Volageconrolled ocillaor (VCO) and digial couner were ued inead of claical A/D converer. VCO i alo known a volage-frequency converer (u/f converer). Such organized conrol of he buck converer i hown in Fig.. he new clock ignal appear a he end of inerval off where he flip-flop i e and he r i wiched ON. A he ame ime anoher couner alo ar, which inegrae he pule of VCO during he inerval on. he ree ignal appear on he R flip-flop inpu when he um of boh couner reach reference curren, and r i wiched OFF. Figure. Curren mode concep:(a) Ordinary PWM approach; (b) Curren-mode conrol replacing he claical PWM.. A. he curren-mode conrol operaion Referring o Fig, in eady ae he curren conrol funcion i ared when he clock pule (cl.) appear. For he ake of impliciy in he block chema only one couner i hown, bu he acual ignal (from u/f) i divided ino wo clock ignal i L(f-on) and i L(f-off) for he wo couner indicaed in ignal diagram in Fig. 3. Boh ignal are led o he appropriae couner. Comparaor ree he flip-flop if he um of boh couner conen mee reference curren i ref, repreened by 6-bi digial number. he couner inegrae he VCO pule i L(f-off) during he off inerval imply by couning and a an oupu he I L(dig) ignal i generaed. B. Curren-meauremen mahemaical analyi he inananeou VCO frequency of hee pule (f i ) can be calculaed from: i il ( ) f = ku + f () where f repreen offe frequency, and k i he VCO conan (for choen VCO, f = 3 MHz and k = 5.6 MHz/V). Volage u il appear on he VCO inpu afer he inducor curren wa meaured a he hun reior (R h ) and amplified wih he (A β ) conan. I yield where u i L il = A R i () ( ) β h L imax a; when r = OFF = imin + a; when r = ON he curren ha a maximum indicaed by i max and minimum indicaed by i min (Fig. 3). Coefficien a and a depend on he circui parameer (u d - u o )/L and -u o /L repecively. (3) Figure 3. he ypical waveform: i L -inducor curren; i L(f-on) -VCO ignal for inducor curren when r i ON, i L(f-off) -VCO ignal for inducor curren when r i OFF, I L(dig) -cone of couner (average inducor curren); cl-flip- flop clock ignal; δ PWM-riggering pule. Boh couner mu be ree o zero in order o ar he new curren meauremen. hi procedure i repeaed during he converer operaion. he VCO generae an oupu ignal i L(f-on) conneced a a clock ignal o he digial couner. he ame VCO oupu ignal i conneced inide he FPGA on he wo couner. VCO frequency ( i off ) f change during inerval off a follow from (), () and (3): f i off = Λ Λ (4) Λ = ka R i + f and Λ = kaβ Rha and alo VCO frequency change during on : where β h max f i on = Γ + Γ (5) where Γ = kaβ Rhimin + f and Γ = kaβ Rha. Equaion (4) and (5) how how he inananeou value of inducor curren change he VCO frequency. In order o evaluae he inducor curren average value nex formula mu be ued: I = i d = f d ( ) ( ) L L i ( fi off ( ) i on ( ) d f d ) = + (6)

3 ranacion on Elecrical Engineering, Vol. (), No. 3 where i digial caling facor. Equaion (6) i modified by uing noaion in Fig. (4) a follow: I L x y ( ) ( ) = f τ dτ + f τ dτ i off i on x y = Λx Λ + Γ y + Γ (7) Where a i he meauremen reior aenuaion, f i he VCO offe frequency and volage u () i repreen by: ( ) u = U () he VCO i ared wih volage o frequency converion and generae a i oupu pule indicaed a u (f) in Fig. 6. A he ame ime hi VCO ignal i couned by couner and a he end of inerval here i an average oupu volage available a follow: Figure 4. he waveform: inide meauremen circui. Figure 5. Concepual cheme of inducor curren meauremen. So a he end of inegraion proce (end of inerval ) inide of FPGA he average value of he inducor curren i available a he ae of adder (refer Fig. 5). I Z Z Z L off on ( il) = + = (8) where off = Λ Λ ( ) and Zon y ( y ) Z x x = Γ + Γ. From (8) i can be evaluaed he inducor curren average value over he inerval, a follow I L = Z( il) (9) C. Volage-meauremen mahemaical analyi Referring o Fig, in eady ae he volage conrol funcion i ared when he clock pule (cl.) appear. he VCO conver volage ino frequency: u ( ) f = a u + f () Figure 6. he volage meauremen waveform: u -oupu volage; u (f) - VCO ignal for oupu volage, U (dig) -cone of couner (average oupu volage); cl-flip- flop clock ignal; δ PWM-riggering pule. U u d f d ( ) = u ( ) = () where i digial caling facor. Equaion () i modified by uing noaion in Fig. (6) a follow: U x f ( ) u d x = τ τ = Π, (3) and a he end of inerval inide of FPGA, he average value of he oupu volage can be evaluaed from (3) a follow: U = Z( u) (4) = Π + Π and repreen he ae of he couner conneced o he VCO dedicaed for volage meauremen and mu be capured from couner for volage conrol purpoe a he end of inerval. where Zu x ( x ) III. RESULS AND DISCUSSION (SIMULAION AND EXPERIMENAION) A. Simulaion he curren-mode conrol baed on he propoed principle ha been imulaed wih he ue of he MALAB- SIMULIN (Fig. 7). he curren meauremen wa performed by uing he u/f converer. he elemen of Simpoweryem oolbox were ued and alo he whole meauremen principle and conroller baed on SIMULIN block wa developed.

4 ranacion on Elecrical Engineering, Vol. (), No. 4 I i precribed ha he wiching frequency i f = 5 khz ( = 4 µ). he parameer ued were: L = 7 µh, C = µf, u = 5 V and u d = V. Fig. 8 how he ranien repone when he oupu volage wa conrolled during he load change from 6.8 Ω o 3.4 Ω, and vice-vera. he propoed algorihm wa alo verified by experimen. he experimen wa e-up by he cacade conrol rucure were he neceary curren reference wa calculaed by he volage conroller. ocillae wih minimum ocillaion frequency, whereby he informaion ha been lo, and herefore addiional adder circui wa added, which allowed he curren meauremen from o A ( - 3 V). Fig. how he analogue par of inducor curren meauremen acquiiion yem. he curren informaion i provided from hun reior and amplified by INA (IC) circui. Aferward he u offe i added o he informaion of he inducor curren. Figure 7. Simulaion chema Figure 9. Experimenal e-up circui. Figure 8. Inpu and oupu volage and curren waveform: reference and oupu volage u ref and u repecively (uper diagram) and inducor curren i L when load changed from 6.8Ω 3.4Ω 6.8Ω. For he curren and volage meauremen he u/f meauremen principle wa applied, a wa oulined in he previou ex. he volage PI conroller parameer were deigned frequency domain by uing he Bode diagram. Small ignal model baed on ae pace averaging mehod were ued a i i propoed in [6]. B. Experimenal e-up Baed on he above decribed principle of operaion he experimenal e-up wih buck-converer circui and appropriae FPGA uni wa build (Fig. 9). A wa claimed in he previou ecion i wa neceary o carry ou appropriae proceing of he inducor curren meaured quaniy wih he aim ha he u/f converer will operae in he righ area. Fir of all, u/f converer oupu frequency ar o vary when i inpu volage i greaer han.7 V. When he meaured and amplified ignal of inducor curren ha le han (u (il) <.7 V) he u/f converer Figure. Analogue daa aquiziion meauremen circui for inducor curren. When he inducor curren informaion i obained and appropriae procee are conneced o he u/f converer (Fig. ). he whole inducor curren meauremen chain wa eed and calibraed a hown in Fig.. Yellow area indicae he inpu volage range u ( ) (, 3 V ). he u/f oupu frequency change il almo linearly a wa preumed in (). he digial caling facor defined in (9) i e a he raio beween he 3V maximum inpu u/f volage range and he um of he wo couner. A followed from Fig. 5 for curren meauremen wo couner inide he FPGA were ued. he fir one coun he curren during he ime period off and he econd one during on. he meaning of conan and hould be explained here. From Fig. follow ha he maximum frequency of u/f converer

5 ranacion on Elecrical Engineering, Vol. (), No. 5 i 4 MHz. So beween wo ignal pule indicaed by cl. (Fig 3. and Fig. 6) can be couned 56 (f vco /f PWM ) of quana. Conan and can be calculaed by: f pwm = = = (5) f 56 vco he volage meauremen wa performed on he ame way. Only one digial couner wa ued inide he FPGA becaue of almo compleely fla volage waveform. hi couner i ynchronized wih he end of riggering pule δ. he analogue acquiiion par of volage meauremen circui i hown in Fig. 3 and u/f chema i hown in Fig. 3 and VCO circui in Fig. 4. Figure 5. he volage and curren waveform when load wa changed from 6,8Ω 3.4Ω 6.8Ω Figure. he chema of volage o frequncy converer for inducor curren meauremen. Figure 6. he volage and curren waveform cu-off; ar-up volage and curren wave-form Figure. he aic characeriic of VCO. Figure 3. Analogue daa aquiziion meauremen circui for buckconverer oupu volage. Figure 4. he chema of volage o frequncy converer for oupu volage meauremen C. Reul and dicuion he curren-mode conrol baed on he propoed principle ha been verified by experimenaion. he curren meauremen wa performed by uing he u/f converer. he wiching frequency i e o f = 5 khz ( = 4 µ) and he buck converer circui parameer are choen a wa uggeed in he imulaion: L= 7 µh, C = µf, u = 5 V and u d = V. he experimen wa e-up by he cacade conrol rucure were he neceary curren reference wa calculaed by he volage conroller. For he curren and volage meauremen he u/f meauremen principle wa applied, a wa oulined in he previou ex. Fig. 5 how he ranien repone when load wa changed a indicaed in he figure capure. he volage reference wa e o 5 V. Fig. 6 how ar-up repone of buck-converer oupu volage and inducor curren. he average inducor curren i limied o.5 A. Fig. 7 and 8 how cloe-up when he load ha changed from 6,8 Ω 3.4 Ω. and 3.4 Ω 6.8 Ω repecively. he volage conroller generae he curren reference which change from.75 A o.5 A and vice-vera. he volage dynamic error wa approximaely ± 4 mv.

6 ranacion on Elecrical Engineering, Vol. (), No. 6 IV. CONCLUSION he volage and curren conrol-mode conrol algorihm can be performed in a digial way a i i hown in hi paper. he VCO baed curren and volage meauremen enable uch approach. he algorihm i baed on average curren and volage meauremen by uing he volage o frequency converion inead of convenional A/D converer. Boh meauremen were performed by uing he VCO. Such an approach i uiable for he implemenaion of all algorihm in he FPGA circui. I i, herefore, adequae for many indurial applicaion uch a high power muliphae DC-DC converer. REFERENCES Figure 7. he volage and curren waveform cu-off; when load wa changed from 6,8 Ω 3,4 Ω. Figure 8. he volage and curren waveform cu-off; when load wa changed from 3.4 Ω 6.8 Ω. [] E. Vidal-Idiare, L. Marnez-Salamero, F. Guinjoan, J. Calvene and S. Gomariz, Sliding and fuzzy conrol of a boo converer uing an 8-bi microconroller, IEE Proceeding-Elecric Power applicaion, vol. 5, N, pp. 5-, Jan. 4 [] M. Milanovic, M. runic, P. Slibar and D. Dolinar, Reconfigurable digial conroller for a buck converer baed on FPGA. Microelecron. Reliab., vol. 47, no., pp. 5-54, January, 7 [3] B. J. Paella, A. Prodic, A. Zirger and D. Makimovic, Highfrequency digial pwm conroller IC for dc-dc converer, IEEE ranacion on Power Elecronic, vol.8, no, pp , January 3. [4] J. A. Gow, C. D. Manning, Novel fa-acing predicive curren mode conroller for power elecronic converer, IEE Proceeding-Elecric Power applicaion, vol 48, N, pp.33-39, March. [5] M. runič, M. Milanovič, E. Vidal-Idiare, C. Carrejo, C. Alono, Digial curren mode and volage conrol for he DC-DC ep-up converer baed on he FPGA echnology. V: 4h Inernaional Power Elecronic and Moion Conrol Conference, EPE-PEMC. [6] R.D. Middlebrook, S. Cuk A General Unified Approach o Modeling Swiching Power Sage. IEEE Power Elecronic Speciali Conference-PESC77, pp , May. 977.