DATASHEET X9430. Programmable Analog Dual Digitally Controlled Potentiometer (XDCP ) with Operational Amplifier

Transcription

1 NOT RECOMMENDED FOR NE DEGNS NO RECOMMENDED RELACEMENT contact our Technical Support Center at INTERL or rogrammable Analog Dual Digitally Controlled otentiometer (XDC ) with Operational Amplifier DATASHEET FN8198 Rev. FEATURES Two CMOS voltage operational amplifiers Two digitally controlled potentiometers Can be combined or used separately Amplifiers Low voltage operation V/V- = ±2.7V to ±5.5V Rail-to-rail CMOS performance 1MHz gain bandwidth product Digitally controlled potentiometer Dual 64 tap potentiometers R total = 1k serial interface V CC = 2.7V to 5.5V DESCRITION The X943 is a monolithic CMOS IC that incorporates two operational amplifiers and two nonvolatile digitally controlled potentiometers. The amplifiers are CMOS differential input voltage operational amplifiers with near rail-to-rail outputs. All pins for the two amplifiers are brought out of the package to allow combining them with the potentiometers or using them as complete stand-alone amplifiers. The digitally controlled potentiometers consist of a series string of 63 polycrystalline resistors that behave as standard integrated circuit resistors. The serial port, common to both pots, allows the user to program the connection of the wiper output to any of the resistor nodes in the series string. The wiper position is saved in the on board E2 memory to allow for nonvolatile restoration of the wiper position. A wide variety of applications can be implemented using the potentiometers and the amplifiers. A typical application is to implement the amplifier as a wiper buffer in circuits that use the potentiometer as a voltage reference. The potentiometer can also be combined with the amplifier yielding a digitally programmable gain amplifier or programmable current source. BLOCK DIAGRAM HOLD V CC R R H R L V SO A1 Control and Memory CR A CR1 V NI V OUT V INV V NI1 V OUT1 V INV1 V SS R 1 R L1 R H1 V- FN8198 Rev. age 1 of 21

2 IN DESCRITIONS Host Interface ins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input () is the serial data input pin. All opcodes, byte addresses and data to be written to the device are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock () The input is used to clock data into and out of the X943. Chip Select () hen is HIGH, the X943 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. LO enables the X943, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LO transition on is required prior to the start of any operation. Hardware rite rotect Input The pin when low prevents nonvolatile writes to the wiper counter register. Hold (HOLD) HOLD is used in conjunction with the pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LO while is LO. To resume communication, HOLD is brought HIGH, again while is LO. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A - A 1 ) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X943. A maximum of 4 devices may occupy the serial bus. otentiometer ins 1 R H (R H - R H1 ), R L (R L - R L1 ) The R H and R L inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. R (R - R 1 ) The wiper output is equivalent to the wiper output of a mechanical potentiometer. Amplifier and Device ins Amplifier Input Voltage V NI (,1) and V INV (,1) V NI and V INV are inputs to the noninverting () and inverting (-) inputs of the operational amplifiers. Amplifier Output Voltage V OUT (,1) V OUT is the voltage output pin of the operational amplifier. Analog Supplies V, V- The Analog Supplies V, V- are the supply voltages for the XDC analog section and the operational amplifiers. System Supply V CC and Ground V SS The system supply V CC and its reference V SS is used to bias the interface and control circuits. 1. Alternate designations for R H, R L, R are V H, V L, V FN8198 Rev. age 2 of 21

3 IN CONFIGURATION IN NAMES V CC R L R H R A1 R L1 R H1 R 1 V SS SOIC X V V OUT V NI V INV A S HOLD V INV1 V NI1 VOUT1 V- Symbol SO A - A1 HOLD R H - R H1, R L - R L1 R - R 1 V NI(,1), V INV(,1) V OUT, V OUT1 Description Serial Clock Serial Input Serial Output Device Address Chip Select Hold otentiometers (terminal equivalent) otentiometers (wiper equivalent) Amplifier Input Voltages Amplifier Outputs SO A V INV V NI V OUT V V CC R L R H R TSSO X HOLD V INV1 V NI1 V OUT1 V- V SS R 1 R H1 R L1 A 1 V,V- V CC V SS Hardware rite rotection Analog and Voltage Amplifier Supplies System/Digital Supply Voltage System Ground RINCILES OF OERATION The X943 is an integrated microcircuit incorporating two digitally controlled potentiometers, two operational amplifiers and their associated registers and counters; and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. Serial Interface The X943 supports the interface hardware conventions. The device is accessed via the input with data clocked in on the rising edge of. must be LO and the HOLD and pins must be HIGH during the entire operation. FN8198 Rev. age 3 of 21

4 otentiometer/array Description The X943 is comprised of two resistor arrays and two operational amplifiers. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and R L ). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (R ) output. ithin each individual array only one switch may be turned on at a time. These switches are controlled by a volatile wiper counter register (CR). The six bits of the CR are decoded to select, and enable, one of sixty-four switches. The CR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the CR. These data registers and the CR can be read and written by the host system. Operational Amplifier The voltage operational amplifiers are CMOS rail-to-rail output general purpose amplifiers. They are designed to operate from dual (±) power supplies. The amplifiers may be configured like any standard amplifier. All pins are externally available to allow connection with the potentiometers or as stand alone amplifiers. V H (,1) HOLD V CC (DR - DR3),1 CR,1 V L (,1) SO A1 A Control and Memory CR CR1 V SS (DR - DR3),1 V (,1) V INV (,1) V N (,1) V OUT (,1) Detailed Block Diagram (One of 2 Circuits) rite in rocess The contents of the data registers are saved to nonvolatile memory when the pin goes from LO to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a write in process bit (I). The I bit is read with a read status command. INSTRUCTIONS AND ROGRAMMING Identification (ID) Byte The first byte sent to the X943 from the host, following a going HIGH to LO, is called the identification byte. The most significant four bits of the slave address are a device type identifier, for the X943 this is fixed as 11[B] (refer to Figure 1). FN8198 Rev. age 4 of 21

5 The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A - A 1 input pins. The X943 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X943 to successfully continue the command sequence. The A - A 1 inputs can be actively driven by CMOS input signals or tied to V CC or V SS. The remaining two bits in the slave byte must be set to. Figure 1. Identification Byte Format Device Type Identifier 1 1 A1 A Instruction Byte The next byte sent to the X943 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the CRs of the two pots, and when applicable, they point to one of four associated data registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format Device Address I3 I2 I1 I R1 R Instructions Register Select CR Select The four high order bits of the instruction byte specify the operation. The next two bits (R 1 and R ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bit ( ) selects which one of the two potentiometers is to be affected by the instruction. The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions exchange data between a wiper counter register and one of the four data registers associated with each. A transfer from a data register to a wiper counter register is essentially a write to a static RAM. The response of the wiper to this action will be delayed t RL. A transfer from the wiper counter register (current wiper position) to a data register is a write to nonvolatile memory and takes a minimum of t R to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their associated registers. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X943; either between the host and one of the data registers or directly between the host and the iper Counter and Registers. These instructions are: 1) Read iper Counter Register, read the current wiper position of the selected pot 2) rite iper Counter Register, i.e. change current wiper position of the selected pot; 3) Read Data Register, read the contents of the selected nonvolatile register; 4) rite Data Register, write a new value to the selected data register; 5)Read Status, returns the contents of the I bit which indicates if an internal write cycle is in progress. The sequence of these operations is shown in Figure 4 and Figure 5. The final command is Increment/Decrement. It is different from the other commands, because it s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each clock pulse (t HIGH ) while is HIGH, the selected wiper will move one resistor segment towards the V H terminal. Similarly, for each clock pulse while is LO, the selected wiper will move one resistor segment towards the V L terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 6 and Figure 7. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. FN8198 Rev. age 5 of 21

6 Figure 3. Two Byte Command Sequence 1 1 A1 A I3 I2 I1 I R1 R Figure 4. Three-Byte Command Sequence (rite) 1 1 A1 A I3 I2 I1 I R1 R D5 D4 D3 D2 D1 D Figure 5. Three-Byte Command Sequence(Read) Don t Care 1 1 A1 A I3 I2 I1 I R1 R S D5 D4 D3 D2 D1 D Figure 6. Increment/Decrement Command Sequence 1 1 A1 A I3 I2 I1 I I N C 1 I N C 2 I N C n D E C 1 D E C n FN8198 Rev. age 6 of 21

7 Figure 7. Increment/Decrement Timing t RID V V OUT INC/DEC CMD Issued REGISTER OERATION Both digitally controlled potentiometers share the serial interface and share a common architecture. Each potentiometer is associated with a wiper counter register (CR), and four data registers. Figure 8 illustrates the control, registers, and system features of the device. Figure 8. System Block Diagram SO A1 A HOLD Control and Memory CR V CC CR1 V SS (DR-DR3),1 CR,1 V H (,1) V L (,1) V (,1) V INV (,1) V N (,1) V OUT (,1) The wiper counter register is a volatile register; that is, its contents are lost when the X943 is powered-down. Although the registers are automatically loaded with the value in R upon power-up, it should be noted this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four nonvolatile data registers (DR). These can be read or written directly by the host and data can be transferred between any of the four data registers and the CR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 1ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could store system parameters or user preference data. Detailed Block Diagram iper Counter (CR) and Analog Control Registers (ACR) The X943 contains two wiper counter registers, one for each XDC. The wiper counter register is equivalent to a serial-in, parallel-out counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the wiper counter register can be altered in four ways: it may be written directly by the host via the write CR instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers (DR) via the XFR data register instruction (parallel load); it can be modified one step at a time by the increment/decrement instruction (CR only). Finally, it may be loaded with the contents of its associated data register zero (R) upon power-up. FN8198 Rev. age 7 of 21

8 REGISTER DESCRITIONS AND MEMORY MA Memory Map CRO CR1 DR DR DR1 DR1 DR2 DR2 DR3 DR3 iper Counter Register (CR) (volatile) (LSB) - 5 identify wiper position. Data Registers (DR, R - R3) iper osition or User Data (Nonvolatile) Instruction Format Notes: (1) A1 ~ A : stands for the device addresses sent by the master. (2) x refers to wiper position data in the iper Counter Register (3) I : stands for the increment operation, held HIGH during active phase (high). (4) D : stands for the decrement operation, held LO during active phase (high). Read iper Counter Register (CR) Read the contents of the iper Counter Register pointed to by 1 - device type device instruction CR identifier addresses opcode addresses Falling 1 1 A 1 A wiper position (sent by X943 on SO) Rising rite iper Counter Register (CR) rite new value to the iper Counter Register pointed to by 1 - device type device instruction CR identifier addresses opcode addresses Falling 1 1 A 1 A Data Byte (sent by Host on ) Rising Read Data Register (DR) Read the contents of the Register pointed to by 1 - and R 1 - R device type device instruction DR/CR identifier addresses opcode addresses Falling 1 1 A 1 A R 1 R Data Byte (sent by X943 on SO) Rising rite Data Register (DR) rite new value to the Register pointed to by 1 - and R 1 - R device type device instruction DR/CR identifier addresses opcode addresses Falling 1 1 A 1 A 1 1 R 1 R Data Byte (sent by host on ) Rising HIGH-VOLTAGE RITE CYCLE FN8198 Rev. age 8 of 21

9 Transfer Data Register (DR) to iper Counter Register (CR) Transfer the contents of the Register pointed to by R 1 - R to the CR Falling device type identifier device addresses 1 1 A 1 instruction opcode A R 1 DR/CR addresses Rising Transfer iper Counter Register (CR) to Data Register (DR) R Transfer the contents of the CR to the Register pointed to by R 1 - R device type device instruction DR/CR identifier addresses opcode addresses Falling 1 1 A 1 A R 1 R Rising HIGH-VOLTAGE RITE CYCLE : -CR, 1-CR1 Increment/Decrement iper Counter Register (CR) Enable Increment/decrement of the CR pointed to by 1 - device type device instruction identifier addresses opcode Falling 1 1 A 1 CR addresses A 1 X X increment/decrement (sent by master on SDA) I/ D I/ D.... I/ D I/ D Rising Global Transfer Data Register (DR) to iper Counter Register (CR) Transfer the contents of all four Data Registers pointed to by R 1 - R to their respective CR Falling Global Transfer iper Counter Register (CR) to Data Register (DR) Falling Read Status device type identifier device addresses 1 1 A 1 instruction opcode A 1 R 1 DR addresses R Rising Transfer the contents of all CRs to their respective data Registers pointed to by R 1 - R device type device instruction DR identifier addresses opcode addresses 1 1 A 1 A 1 R 1 R Rising HIGH-VOLTAGE RITE CYCLE Returns the contents of the I bit which indicates if an internal write cycle is in progress Falling device type identifier device addresses 1 1 A 1 instruction opcode wiper addresses Data Byte (sent by X943 on SO) A I Rising FN8198 Rev. age 9 of 21

10 ABSOLUTE MAXIMUM RATINGS Temperature under bias C to 135 C Storage temperature C to 15 C Voltage on, SCL or any address input with respect to V SS... -1V to 7V Voltage on V (referenced to V SS )...7V Voltage on V- (referenced to V SS )...-7V (V) - (V-)...1V Any V H...V Any V L...V- Lead temperature (soldering, 1 seconds)... 3 C COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OERATING CONDITIONS Temperature Min. Max. Commercial C 7 C Industrial -4 C 85 C Device Supply Voltage (V CC ) Limits X943 5V 1% X V to 5.5V OTENTIOMETER CHARACTERISTI (Over recommended operating conditions unless otherwise stated.) Symbol arameter Limits Min. Typ. Max. Unit Test Conditions R TOTAL End to end resistance -2 2 % ower rating 5 m 25 C, each pot I iper current -3 3 ma R iper resistance 4 1 V = 5V, V- = -5V, I = 3mA 1 25 V = 2.7V, V- = -2.7V, I = 1mA Vv Voltage on V pin X V X Vv- Voltage on V- pin X V X V TERM Voltage on any R H or R L pin V- V V Noise -1 dbv Ref: 1V Resolution (4) 1.6 % Absolute linearity (1) -1 1 MI (3) V w(n)(actual) - V w(n)(expected) Relative linearity (2) MI (3) V w(n 1) - [V w(n) MI ] Temperature coefficient of R TOTAL 3 ppm/ C Ratiometric temperature coefficient ±2 ppm/ C Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (R H - R L )/63, single pot (=LSB) (4) Individual array resolutions FN8198 Rev. age 1 of 21

11 AMLIFIER ELECTRICAL CHARACTERISTI (Over the recommended operating conditions unless otherwise specified.) Symbol arameter Condition Industrial Commercial Min. Typ. Max. Min. Typ. Max. V OS Input Offset Voltage V/V- 3V to 5V mv TC VOS Input Offset Voltage Temp. V/V- 3V to 5V -1-1 µv/ C Coefficient I B Input bias current V/V- 3V to 5V 5 5 pa I OS Input offset current V/V- 3V to 5V pa CMRR Common mode V CM = -1V to 1V 7 7 db rejection ratio SRR ower supply V/V- 3V to 5V 7 7 db rejection ratio V CM Input common mode voltage range T j = 25 C V- V V- V V A V Large signal voltage gain V O = -1V to 1V V/mV V O Output voltage swing V- V I O Output current V/V- = 5.5V V/V- = 3.3V I S Supply current V/V- = 5.V 3 3 ma V/V- = 3.V ma GB Gain-bandwidth prod R L = 1k, C L = 5pf MHz SR Slew rate R L = 1k, C L = 5pf V/µsec M hase margin R L = 1k, C L = 5pf 8 8 Deg Unit V V ma ma V and V- (±5V to ±3V) are the amplifier power supplies. The amplifiers are specified with dual power supplies. V CC and V SS are the logic supplies. All ratings are over the temperature range for the Industrial (-4 to 85 C) and Commercial ( to 7 C) versions of the part unless specified differently. FN8198 Rev. age 11 of 21

12 OTENTIOMETER D.C. OERATING CHARACTERISTI (Over the recommended operating conditions unless otherwise specified.) Symbol ENDURANCE AND DATA RETENTION CAACITANCE OER-U TIMING arameter Limits Min. Typ. Max. Unit Test Conditions I CC1 V CC supply current (active) 4 µa f = 2MHz, SO = Open, Other Inputs = V SS I CC2 V CC supply current (nonvolatile write) 1 ma f = 2MHz, SO = Open, Other Inputs = V SS I SB V CC current (standby) 1 µa = = V SS, Addr. = V SS I LI Input leakage current 1 µa V IN = V SS to V CC I LO Output leakage current 1 µa V OUT = V SS to V CC V IH Input HIGH voltage V CC x.7 V CC.5 V V IL Input LO voltage -.5 V CC x.1 V V OL Output LO voltage.4 V I OL = 3mA arameter Min. Unit Minimum endurance 1, Data changes per register Data retention 1 years Symbol Test Typ. Max. Unit Test Conditions C (5) OUT Output capacitance (SO) 8 pf V OUT = V C (5) IN Input capacitance (A, A1,,, HOLD and ) 6 pf V IN = V C L C H C otentiometer capacitance 1/1/2 pf Symbol arameter Max. Unit t (6) UR ower-up to initiation of read operation 1 ms t (6) U ower-up to initiation of write operation 5 ms A.C. TEST CONDITIONS CE Macro Model Input pulse levels V CC x.1 to V CC x.9 Input rise and fall times 1ns R TOTAL R H Input and output timing level V CC x.5 C C H C L R L Notes: (5) This parameter is periodically sampled and not 1% tested. (6) t UR and t U are the delays required from the time the third (last) power supply (V CC, V or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 1% tested. (7) The power-up order of power supplies are V CC, V and V-. R FN8198 Rev. age 12 of 21

13 AC TIMING Symbol arameter Min. Max. Unit f S/ clock frequency 2. MHz t CYC S/ clock cycle time 5 ns t H S/ clock high time 2 ns t L S/ clock low time 2 ns t LEAD Lead time 25 ns t LAG Lag time 25 ns t SU,, HOLD and input setup time 5 ns t H,, HOLD and input hold time 5 ns t RI,, HOLD and input rise time 2 µs t FI,, HOLD and input fall time 2 µs t DIS SO output disable time 5 ns t V SO output valid time 2 ns t HO SO output hold time ns t RO SO output rise time 5 ns t FO SO output fall time 5 ns t HOLD HOLD time 4 ns t HSU HOLD setup time 1 ns t HH HOLD hold time 1 ns t HZ HOLD low to output in high Z 1 ns t LZ HOLD high to output in low Z 1 ns T I Noise suppression time constant at,, HOLD and inputs 2 ns t deselect time 2 µs t ASU, A and A1 setup time ns t AH, A and A1 hold time ns HIGH-VOLTAGE RITE CYCLE TIMING Symbol arameter Typ. Max. Unit t R High-voltage write cycle time (store instructions) 5 1 ms V CC RAM (sample tested) Symbol arameter Typ. Max. Unit trv CC V CC power-up rate.2 5 V/ms FN8198 Rev. age 13 of 21

14 DC Timing Symbol arameter Min. Max. Unit t RO iper response time after the third (last) power supply is stable 1 µs t RL iper response time after instruction issued (all load instructions) 1 µs t RID iper response time from an active SCL/ edge (increment/decrement instruction) 1 µs SYMBOL TABLE AVEFORM INUTS OUTUTS Must be steady May change from Low to High May change from High to Low Don t Care: Changes Allowed N/A ill be steady ill change from Low to High ill change from High to Low Changing: State Not Known Center Line is High Impedance TIMING DIAGRAMS Input Timing t t LEAD t CYC t LAG t SU t H... t L th... t FI t RI MSB LSB SO High Impedance FN8198 Rev. age 14 of 21

15 Output Timing t V t HO t DIS SO MSB LSB ADDR Hold Timing t HSU t HH SO t RO t FO... t HZ t LZ t HOLD HOLD DC Timing (for All Load Instructions)... t RL MSB... LSB Vx SO High Impedance FN8198 Rev. age 15 of 21

16 DC Timing (for Increment/Decrement Instruction)... t RID Vx... ADDR Inc/Dec Inc/Dec... SO High Impedance rite rotect and Device Address ins Timing (Any Instruction) A A1 t ASU t AH FN8198 Rev. age 16 of 21

17 ALICATIONS INFORMATION Basic Configurations of Electronic otentiometers V R V R V I Three terminal otentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier Voltage Regulator V S V O V IN 317 V O (REG) R 1 R 2 I adj R 1 R 2 V O = (1R 2 /R 1 )V S V O (REG) = 1.25V (1R 2 /R 1 )I adj R 2 Offset Voltage Adjustment Comparator with Hysterisis R 1 V S 1k 1k R 2 TL72 V O V S } R 1 } R 2 V O 1k 1k V UL = {R 1 /(R 1 R 2 )} V O (max) V LL = {R 1 /(R 1 R 2 )} V O (min) 12V -12V FN8198 Rev. age 17 of 21

18 Application Circuits (continued) Attenuator Filter V S C V S R 1 R 2 V O R V O R 3 R 4 All RS = 1k R 1 R 2 V O = G V S -1/2 G 1/2 G O = 1 R 2 /R 1 fc = 1/(2 RC) Inverting Amplifier Equivalent L-R Circuit V S R 1 } R 2 } V O V S C1 R 2 V O = G V S G = - R 2 /R 1 Z IN R 1 R 3 Z IN = R 2 s R 2 (R 1 R 3 ) C 1 = R 2 s Leq (R 1 R 3 ) >> R 2 Function Generator C } R A R 2 R 1 } R B frequency µ R 1, R 2, C amplitude µ R A, R B FN8198 Rev. age 18 of 21

19 ACKAGING INFORMATION 24-Lead lastic Small Outline Gull ing ackage Type S in 1 Index.29 (7.37).299 (7.6).393 (1.).42 (1.65) in 1.14 (.35).2 (.5).598 (15.2).61 (15.49) (4X) 7.92 (2.35).15 (2.65).5 (1.27).3 (.1).12 (.3).1 (.25).2 (.5) X 45.5" Typical (.4).5 (1.27).9 (.22).13 (.33).42".5" Typical FOOTRINT.3" Typical 24 laces NOTE: ALL DIMENONS IN INCHES (IN ARENTHESES IN MILLIMETERS) FN8198 Rev. age 19 of 21

20 ACKAGING INFORMATION 24-Lead lastic, TSSO ackage Type V.26 (.65) BSC.169 (4.3).252 (6.4) BSC.177 (4.5).33 (7.7).311 (7.9).47 (1.2).75 (.19).118 (.3).2 (.6).5 (.15).1 (.25) (.5).3 (.75) Detail A (2X) Gage lane Seating lane (1.78) (4.16) (7.72) (.42) (.65).31 (.8).41 (1.5) ALL MEASUREMENTS ARE TYICAL See Detail A NOTE: ALL DIMENONS IN INCHES (IN ARENTHESES IN MILLIMETERS) FN8198 Rev. age 2 of 21

21 Ordering Information X943 Y T V Device V CC Limits Blank = 5V ±1% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = to 7 C I = Industrial = -4 to 85 C ackage S24 = 24-Lead SOIC V24 = 24-Lead TSSO otentiometer Organization ot ot 1 = 1k 1k Copyright Intersil Americas LLC 25. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN8198 Rev. age 21 of 21