X9111. Preliminary Information. Single Digitally-Controlled (XDCP ) Potentiometer. Single Supply / Low Power / 1024-tap / SPI bus

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1 APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 AN115 AN124 AN133 AN134 AN135 Single Supply / Low Power / 124-tap / SPI bus Preliminary Information X9111 Single Digitally-Controlled (XDCP ) Potentiometer FEATURES 124 Resistor Taps 1-Bit Resolution SPI Serial Interface for write, read, and transfer operations of the potentiometer iper Resistance, 4Ω 5V Four Non-Volatile Data s Non-Volatile Storage of Multiple iper Positions Power On Recall. Loads Saved iper Position on Power Up. Standby Current < 3µA Max V CC : 2.7V to 5.5V Operation 1KΩ End to End Resistance 1 yr. Data Retention Endurance: 1, Data Changes Per Bit Per 14-Lead TSSOP, 15-Lead P (Chip Scale Packaging) Low Power CMOS Single Supply version of the X911 DESIPTION The X9111 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 123 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile iper Counter () and four non-volatile Data s that can be directly written to and read by the user. The contents of the controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR) to the. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM V CC R H SPI Bus Interface Address Data Status Bus Interface & Control rite Read Transfer Control Power On Recall iper Counter () Data s (DR-DR3) iper 1KΩ 124-taps POT V SS NC R R L Characteristics subject to change without notice. 1 of 21

2 DETAILED FUNCTIONAL DIAGRAM V CC HOLD SCK SO SI A A1 Interface and Control Circuitry Data Control Power On Recall DR DR2 DR1 DR3 iper Counter () 1KΩ 124-taps R H R L R P V SS CIRCUIT LEVEL APPLICATIONS Vary the gain of a voltage amplifier Provide programmable dc reference voltages for comparators and detectors Control the volume in audio circuits Trim out the offset voltage error in a voltage amplifier circuit Set the output voltage of a voltage regulator Trim the resistance in heatstone bridge circuits Control the gain, characteristic frequency and Q-factor in filter circuits Set the scale factor and zero point in sensor signal conditioning circuits Vary the frequency and duty cycle of timer ICs Vary the dc biasing of a pin diode attenuator in RF circuits Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS Adjust the contrast in LCD displays Control the power level of LED transmitters in communication systems Set and regulate the DC biasing point in an RF power amplifier in wireless systems Control the gain in audio and home entertainment systems Provide the variable DC bias for tuners in RF wireless systems Set the operating points in temperature control systems Control the operating point for sensors in industrial systems Trim offset and gain errors in artificial intelligent systems Characteristics subject to change without notice. 2 of 21

3 PIN CONFIGURATION SO A NC SCK SI V SS TSSOP X V CC R L R H R HOLD A1 P A B C D E P X9111 SO V CC R L A NC R H NC R SCK P HOLD SI V SS A1 PIN ASSIGNMENTS Pin (TSSOP) Pin (P) Symbol Function 1 A3 SO Serial Data Output 2 B3 A Device Address 3 B2, C2 NC No Connect 4 C3 Chip Select 5 D3 SCK Serial Clock 6 E3 SI Serial Data Input 7 E2 V SS System Ground 8 D2 P Hardware rite Protect 9 E1 A1 Device Address 1 D1 HOLD Device Select. Pause the Serial Bus 11 C1 R iper Terminal of the Potentiometer 12 B1 R H High Terminal of the Potentiometer 13 A1 R L Low Terminal of the Potentiometer 14 A2 V CC System Supply Voltage Characteristics subject to change without notice. 3 of 21

4 PIN DESIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9111. HOLD (HOLD) HOLD is used in conjunction with the pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LO while SCK is LO. To resume communication, HOLD is brought HIGH, again while SCK is LO. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A, A 1 ) The address inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input (A1 A) in order to initiate communication with the X9111. CHIP SELECT () hen is HIGH, the X9111 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. LO enables the X9111, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LO transition on is required prior to the start of any operation. HARDARE RITE PROTECT INPUT (P) The P pin when LO prevents nonvolatile writes to the Data s. Potentiometer Pins R H, R L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. R The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (V CC ) AND SUPPLY GROUND (V SS ) The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins NO CONNECT (NC) Pin should be left open. This pin is used for Xicor manufacturing and test purposes. PRINCIPLES OF OPERATION DEVICE DESIPTION Serial Interface The X9111 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in on the rising SCK. must be LO and the HOLD and P pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9111 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 123 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and R L inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (R ) output. ithin the individual array only one switch may be turned on at a time. Characteristics subject to change without notice. 4 of 21

5 Figure 1. Detailed Potentiometer Block Diagram Serial Data Path From Interface Circuitry (DR) 1 (DR1) 1 1 Serial Bus Input Parallel Bus Input C O U N T E R R H 2 (DR2) 3 (DR3) iper Counter () D E C O D E If = [HEX] then R = R L If = 3FF[HEX] then R = R H R L R These switches are controlled by a iper Counter (). The 1-bits of the ([9:]) are decoded to select, and enable, one of 124 switches. iper Counter () The X9111 contains a iper Counter (see Table 1) for the XDCP potentiometer. The is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 124 switches along its resistor array. The contents of the can be altered in one of three ways: (1) it may be written directly by the host via the write iper Counter instruction (serial load); (2) it may be written indirectly by transferring the contents of one of four associated Data s via the XFR Data ; (3) it is loaded with the contents of its Data zero (DR) upon power-up. The iper Counter is a volatile register; that is, its contents are lost when the X9111 is powereddown. Although the register is automatically loaded with the value in R upon power-up, this may be different from the value present at power-down. Powerup guidelines are recommended to ensure proper loadings of the R value into the. Data s (DR3 to DR) The potentiometer has four 1-bit non-volatile Data s. These can be read or written directly by the host. Data can also be transferred between any of the four Data s and the iper Counter. All operations changing data in one of the Data s is a nonvolatile operation and will take a maximum of 1ms. If the application does not require storage of multiple settings for the potentiometer, the Data s can be used as regular memory locations for system parameters or user preference data. A DR[9:] is used to store one of the 124 wiper position ( ~123). Table 2. Status (SR) This 1-bit status register is used to store the system status (see Table 3). IP: rite In Progress status bit, read only. hen IP=1, indicates that high-voltage write cycle is in progress. hen IP=, indicates that no high-voltage write cycle is in progress. Characteristics subject to change without notice. 5 of 21

6 Table 1. iper Latch, L (1-bit), 9 : Used to store the current wiper position (Volatile, V) V V V V V V V V V V (MSB) (LSB) Table 2. Data, DR (1-bit), Bit 9 Bit : Used to store wiper positions or data (Non-Volatile, NV) Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit NV NV NV NV NV NV NV NV NV NV MSB LSB Table 3. Status, SR (1-bit) IP (LSB) DEVICE INSTRUCTIONS Identification Byte (ID and A) The first byte sent to the X9111 from the host, following a going HIGH to LO, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:] bits is the device ID for the X9111; this is fixed as 11[B] (refer to Table 4). The A1 A bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1 A input pins. The slave address is externally specified by the user. The X9111 compares the serial data stream with the address input state; a successful compare of the address bits is required for the X9111 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A1 A inputs can be actively driven by CMOS input signals or tied to V CC or V SS. The R/ bit is used to set the device to either read or write mode. Byte and Selection The next byte sent to the X9111 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:]). The RB and RA bits point to one of the four registers. The format is shown in Table 5. Table 4. Identification Byte Format Device Type Identifier Internal Slave Address Read or rite Bit ID3 ID2 ID1 ID A1 A R/ 1 1 (MSB) (LSB) Table 5. Byte Format Opcode Selection I2 I1 I RB RA (MSB) RB RA (LSB) DR DR1 DR2 DR3 Characteristics subject to change without notice. 6 of 21

7 Five of the seven instructions are four bytes in length. These instructions are: Read iper Counter read the current wiper position of the selected pot, rite iper Counter change current wiper position of the selected pot, Read Data read the contents of the selected data register; rite Data write a new value to the selected data register. Read Status This command returns the contents of the IP bit which indicates if the internal write cycle is in progress. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the and one of the Data s. A transfer from a Data to a is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t RL. A transfer from the (current wiper position), to a Data is a write to nonvolatile memory and takes a minimum of t R to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status instruction is the only unique format (see Figure 4). Two instructions require a two-byte sequence to complete (see Figure 2). These instructions transfer data between the host and the X9111; either between the host and one of the Data s or directly between the host and the iper Counter. These instructions are: XFR Data to iper Counter This transfers the contents of one specified Data to the associated iper Counter. XFR iper Counter to Data This transfers the contents of the specified iper Counter to the specified associated Data. See format for more details. rite in Process (IP bit) The contents of the Data s are saved to nonvolatile memory when the pin goes from LO to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a rite In Process bit (IP). The IP bit is read with a Read Status command (see Figure 4). Power Up and Down Requirements There are no restrictions on the power-up condition of V CC and the voltages applied to the potentiometer pins provided that the V CC is always more positive than or equal to the voltages at R H, R L, and R, i.e., V CC R H, R L, R. There are no restrictions on the powerdown condition. However, the datasheet parameters for the DCP do not apply until 1millisecond after V CC reaches its final value. Figure 2. Two-Byte Sequence SCK SI 1 1 ID3 ID2 ID1 ID A1 A R/ I2 I1 I RB RA Device ID Internal Address Opcode Address Characteristics subject to change without notice. 7 of 21

8 Figure 3. Four-Byte Sequence (rite or Read for or Data s) SCK SI 1 1 X X X X X X X X ID3 ID2 ID1 ID A1 A R/ I2 I1 I RB RA Device ID Internal Address Opcode Address C R iper Position Figure 4. Four-Byte Sequence (Read Status s) SCK SI X X X X X X X X X X ID3 ID2 ID1 ID A1 A R/ I2 I1 I RB RA IP Device ID Internal Address Opcode Address Status Bit Characteristics subject to change without notice. 8 of 21

9 Table 6. Set Read iper Counter rite iper Counter Set R/ I 3 I 2 I 1 RB RA Operation 1 1 Read the contents of the iper Counter 1 1 rite new value to the iper Counter Read Data / 1/ Read the contents of the Data pointed to RB-RA rite Data 1 1 1/ 1/ rite new value to the Data pointed to RB-RA XFR Data to iper Counter XFR iper Counter to Data / 1/ Transfer the contents of the Data pointed to by RB-RA to the iper Counter / 1/ Transfer the contents of the iper Counter to the Data pointed to by RB-RA Read Status (IP bit) Read the status of the internal write cycle, by checking the IP bit (read status register). Note: (1) 1/ = data is one or zero INSTRUCTION FORMAT Read iper Counter () Falling Device Type Identifier Device 1 1 A1 A R/ = 1 Opcode iper Position (Sent by X9111 on SO) 1 X X X X X X iper Position (sent by X9111 on SO) Rising rite iper Counter () Falling Device Type Identifier Device 1 1 A1 A R/ = Opcode iper Position (Sent by Master on SI) 1 1 X X X X X X iper Position (Sent by Master on SI) Rising Read Data (DR) Falling Device Type Identifier Device 1 1 A1 A R/ = 1 Opcode iper Position (Sent by X9111 on SO) 1 1 RB RA X X X X X X iper Position (sent by X9111 on SO) Rising Characteristics subject to change without notice. 9 of 21

10 rite Data (DR) Falling Device Type Identifier Device 1 1 A1 A R/ = Opcode iper Position or Data (Sent by Master on SI) 1 1 RB RA X X X X X X iper Position or Data (Sent by Master on SI) Rising HIGH-VOLTAGE RITE CYCLE Transfer Data (DR) to iper Counter () Falling Device Type Identifier Device 1 1 A1 A R/ = 1 Opcode 1 1 RB RA Rising Transfer iper Counter () to Data (DR) Falling Device Type Identifier Device 1 1 A1 A R/ = Opcode RB RA Rising HIGH-VOLTAGE RITE CYCLE Read Status (SR) Falling Device Type Identifier Device 1 1 A1 A R/ = 1 Opcode Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) 1 1 X X X X X X X X IP Rising Notes: (1) A and A1 : stand for the device address sent by the master. (2) x refers to wiper position data in the iper Counter (3) X : Don t Care. Characteristics subject to change without notice. 1 of 21

11 ABSOLUTE MAXIMUM RATINGS Temperature under bias C to +135 C Storage temperature C to +15 C Voltage on SCK any address input with respect to V SS... 1V to +7V V = (VH VL)...5V Lead temperature (soldering, 1 seconds)... 3 C I (1 seconds)...±6ma COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial C +7 C Industrial 4 C +85 C Device Supply Voltage (V CC ) Limits X9111 5V ±1% X V to 5.5V ANALOG CHARACTERISTI (Over recommended industrial operation conditions unless otherwise stated.) Symbol Parameter Limits Min. Typ. Max. Units Test Conditions R TOTAL End to End Resistance 1 kω End to End Resistance Tolerance ±2 % Power Rating 5 m 25 C, each pot I iper Current ±3 ma R iper Resistance 4 11 Ω iper Current = ± 5µA, V CC = 5V 15 3 Ω iper Current = ± 5µA, V CC = 3V V TERM Voltage on any R H or R L Pin V SS 5 V V SS = V Noise -12 dbv Ref: 1V Resolution 1.6 % Absolute Linearity (1) ±1 MI (3) R w(n)(actual) R w(n)(expected), where n=8 to 16 ±1.5 ±2. MI (3) R w(n)(actual) R (6) w(n)(expected) Relative Linearity (2) ±.5 MI (3) R w(m + 1) [R w(m) + MI], where m=8 to 16 ±.5 ±1. MI (3) R w(m + 1) [R w(m) + MI] (6) Temperature Coefficient of R TOTAL ±3 ppm/ C Ratiometric Temp. Coefficient 2 ppm/ C C H /C L /C Potentiometer Capacitancies 1/1/25 pf See Macro model Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 123 or (R H R L ) / 123, single pot (4) n =, 1, 2,,123; m =, 1, 2,, 122. (5) ESD Rating on RH, RL, R pins is 1.5KV (HBM, 1.µA leakage maximum), ESD rating on all other pins is 2.KV. Characteristics subject to change without notice. 11 of 21

12 D.C. OPERATING CHARACTERISTI (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions I CC1 I CC2 V CC supply current (active) V CC supply current (nonvolatile write) 4 µa f SCK = 2.5 MHz, SO = Open, V CC =5.5V Other Inputs = V SS 1 5 ma f SCK = 2.5MHz, SO = Open, V CC =5.5V Other Inputs = V SS I SB V CC current (standby) 3 µa SCK = SI = V SS, Addr. = V SS, = V CC = 5.5V I LI Input leakage current 1 µa V IN = V SS to V CC I LO Output leakage current 1 µa V OUT = V SS to V CC V IH Input HIGH voltage V CC x.7 V CC + 1 V V IL Input LO voltage 1 V CC x.3 V V OL Output LO voltage.4 V I OL = 3mA V OL Output LO voltage V CC -.8 V I OH = -1mA, V CC +3V V OL Output LO voltage V CC -.4 V I OH = -.4mA, V CC +3V ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum Endurance 1, Data changes per bit per register Data Retention 1 years CAPACITANCE Symbol Test Max. Units Test Conditions C (6) IN/OUT Input/Output capacitance (SI) 8 pf V OUT = V (6) C OUT Output capacitance (SO) 8 pf V OUT = V (6) C IN Input capacitance (A,, P, HOLD, and SCK) 6 pf V IN = V POER-UP TIMING Symbol Parameter Min. Max. Units (6) t r V CC V CC power-up rate.2 5 V/ms (7) t PUR Power-up to initiation of read operation 1 ms (7) t PU Power-up to initiation of write operation 5 ms Notes: (6) This parameter is not 1% tested (7) t PUR and t PU are the delays required from the time the (last) power supply (V CC -) is stable until the specific instruction can be issued. These parameters are not 1% tested. Characteristics subject to change without notice. 12 of 21

13 A.C. TEST CONDITIONS Input pulse levels V CC x.1 to V CC x.9 Input rise and fall times 1ns Input and output timing level V CC x.5 EQUIVALENT A.C. LOAD CIRCUIT 5V 3V SPICE Macromodel SO pin 2714Ω 1462Ω 1pF SO pin 1217Ω 1382Ω 1pF R H C L 1pF R TOTAL C 25pF C L 1pF R L R AC TIMING Symbol Parameter Min. Max. Units f SCK SSI/SPI clock frequency 2. MHz t CYC SSI/SPI clock cycle time 4 ns t H SSI/SPI clock high time 15 ns t L SSI/SPI clock low time 15 ns t LEAD Lead time 15 ns t LAG Lag time 15 ns t SU SI, SCK, HOLD and input setup time 5 ns t H SI, SCK, HOLD and input hold time 5 ns t RI SI, SCK, HOLD and input rise time 5 ns t FI SI, SCK, HOLD and input fall time 5 ns t DIS SO output disable time 5 ns t V SO output valid time 1 ns t HO SO output hold time ns t RO SO output rise time 5 ns t FO SO output fall time 5 ns t HOLD HOLD time 4 ns t HSU HOLD setup time 5 ns t HH HOLD hold time 5 ns t HZ HOLD low to output in high Z 1 ns t LZ HOLD high to output in low Z 1 ns T I Noise suppression time constant at 2 ns SI, SCK, HOLD and inputs t deselect time 1 ns t PASU P, A, A1 setup time ns t PAH P, A, A1 hold time ns Characteristics subject to change without notice. 13 of 21

14 HIGH-VOLTAGE RITE CYCLE TIMING Symbol Parameter Typ. Max. Units t R High-voltage write cycle time (store instructions) 5 1 ms XDCP TIMING Symbol Parameter Min. Max. Units t RPO iper response time after the third (last) power supply is stable 5 1 µs t RL iper response time after instruction issued (all load 5 1 µs instructions) SYMBOL TABLE AVEFORM INPUTS OUTPUTS Must be steady May change from Low to High May change from High to Low Don t Care: Changes Allowed N/A ill be steady ill change from Low to High ill change from High to Low Changing: State Not Known Center Line is High Impedance Characteristics subject to change without notice. 14 of 21

15 TIMING DIAGRAMS Input Timing t t LEAD t CYC t LAG SCK t SU t H... th t L... t FI t RI SI MSB LSB SO High Impedance Output Timing SCK... t V t HO... t DIS SO MSB LSB SI ADDR Hold Timing t HSU t HH SCK t RO t FO... SO t HZ t LZ SI t HOLD HOLD Characteristics subject to change without notice. 15 of 21

16 XDCP Timing (for All Load s) SCK... t RL SI MSB... LSB R SO High Impedance rite Protect and Device Address Pins Timing (Any ) P A A1 t PASU t PAH. Characteristics subject to change without notice. 16 of 21

17 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers V R +V R R I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier Voltage Regulator V S + V O V IN 317 V O (REG) R 1 R 2 I adj R 1 R 2 V O = (1+R 2 /R 1 )V S V O (REG) = 1.25V (1+R 2 /R 1 )+I adj R 2 Offset Voltage Adjustment Comparator with Hysterisis R 1 V S 1KΩ 1KΩ + R 2 TL72 V O V S } R 1 + } R 2 V O 1KΩ 1KΩ V UL = {R 1 /(R 1 +R 2 )} V O (max) RL L = {R 1 /(R 1 +R 2 )} V O (min) +12V -12V Characteristics subject to change without notice. 17 of 21

18 Application Circuits (Continued) Attenuator Filter V S C + V S R 1 + R 2 V O R V O R 3 R 4 R1 = R 2 = R 3 = R 4 = 1kΩ R 1 R 2 V O = G V S -1/2 G +1/2 G O = 1 + R 2 /R 1 fc = 1/(2πRC) Inverting Amplifier Equivalent L-R Circuit V S R 1 } R 2 } + V O V S C 1 R 2 + V O = G V S G = - R 2 /R 1 Z IN R 1 R 3 Z IN = R 2 + s R 2 (R 1 + R 3 ) C 1 = R 2 + s Leq (R 1 + R 3 ) >> R 2 Function Generator C + } R A R 2 R 1 + } R B frequency R 1, R 2, C amplitude R A, R B Characteristics subject to change without notice. 18 of 21

19 15-Bump Chip Scale Package (P B15) Package Outline Drawing a d A3 A2 A1 9111TBZ Y I Lot# k f B3 B2 B1 C3 C2 C1 D3 D2 D1 E3 E2 E1 b m j e l Top View (Sample Marking) Bottom View (Bumped Side) Side View e Side View c Package Dimensions Millimeters Symbol Min Nominal Max Package idth a Package Length b Package Height c Body Thickness d Ball Height e Ball Diameter f Ball Pitch - idth j.5 Ball Pitch - Length k.5 Ball to Spacing idth l Ball to Spacing - Length m Ball Matrix A SO Vcc R L B A NC* R H C NC* R D SCK P HOLD E SI Vss A1 * True no-connect bump Characteristics subject to change without notice. 19 of 21

20 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Code V14.25 (.65) BSC.169 (4.3).177 (4.5).252 (6.4) BSC.193 (4.9).2 (5.1).41 (1.5).75 (.19).118 (.3).2 (.5).6 (.15) (.5).29 (.75) Detail A (2X).1 (.25) Gage Plane Seating Plane.31 (.8).41 (1.5) See Detail A NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Characteristics subject to change without notice. 2 of 21

21 ORDERING INFORMATION X9111 Y P T V Device V CC Limits Blank = 5V ±1% 2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = C to +7 C I = Industrial = 4 C to +85 C Package V14 = 14-Lead TSSOP B15 = 15-Lead P Potentiometer Organization Pot T = 1KΩ LIMITED ARRANTY Xicor, Inc. 23 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct rite, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,44,475; 4,45,42; 4,486,769; 4,488,6; 4,52,461; 4,533,846; 4,599,76; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,98,859; 5,12,132; 5,3,197; 5,23,694; 5,84,667; 5,153,88; 5,153,691; 5,161,137; 5,219,774; 5,27,927; 5,324,676; 5,434,396; 5,544,13; 5,587,573; 5,835,49; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Characteristics subject to change without notice. 21 of 21