High speed electronics (in optical communications)

Transcription

1 High speed electronics (in optical communications) SOK-2013 Conference January 30/31, February 1, 2013 Ljubljana Franz Dielacher Marc Tiebout, Rudolf Lachner, Klaus Aufinger, Herbert Knapp, Koen Mertens, Werner Simbuerger

2 OUTLINE Introduction Optical communications and drivers Emerging silicon technologies and design considerations SiGe:C technology and ewlb package for optical applications Implementation examples O/E Module High-speed AD/DA converters VCO Summary and a few statements

3 Internet connectivity July, 2010 Page 3

4 Optical Fiber Thin glass wire with higher refractive index in the core to contain and guide the light Typically transmitted at 1300 nm: zero dispersion for standard single-mode fibers 1550 nm: lowest loss, widely employes in telecommunications Advantages: Large data rates, e.g. Gbps to Tbps Immune to electrical interference Low loss long reach Resistant to corrosion Small in size Disadvantages: Expensive to install

5 Evolution of Optical Links Krishnamoorthy et al., "Progress in Low-Pow Set date Page 5

6 Gartner hype cycle OPTO: many years to mainstream adoption July, 2010 Page 6

7 VCSEL-based Optical Link Structure VCSEL: Vertical Cavity Surface Emitting Laser Krishnamoorthy et al., "Progress in Low-Power Set date Page 7

8 High Speed Transistor Technologies Page 8

9 Requirements on Technologies for Optical Transceiver Circuits Improved RF performance (ft, fmax, rf gain, ) Lower noise, higher output power Higher RF integration more Tx channels more Rx channels frequency control and stabilization Higher logic content self test self calibration surveillance during operation digital interfaces Fmax --> 1 THz

10 Gain [db] Improved Gain/Stage with increased ft/fmax Gain (db) ~ -20 db x log (f op /f max ) Gain~14dB 10 Gain~10dB 0 0, Frequenz [GHz] f op =77 Ghz f max =250 Ghz f max =500 Ghz f max =400 Ghz

11 fmax (GHz) Why will high f t /f max save power / current? Lower current / power same performance fmax (IC) 0 0,1 0,1 0,2 0, IC (ma) Improved same current / power consumption 400 GHz PDP rel =0.62 W E =0,12µm L E =2,0µm 250 GHz PDP rel =1.00 W E =0,18µm; L E =2,7µm PDP rel =relative power*delay product ~ V CC * I / f max

12 Comparision metal losses of CMOS Digital and BiCMOS M6 Oxide / Nitride Aluminum Copper M5 Tungsten Silicon Distance of top metal to ground plane (M1) M6 M5 M4 M3 M2 M1 M4 M3 M2 M1 130 nm CMOS 130 nm RF BiCMOS Loss 1.2 db/mm 0.5 db/mm Source: STM

13 OUTLINE Introduction Optical communications and drivers Emerging silicon technologies and design considerations SiGe:C technology and ewlb package for optical applications Implementation examples O/E Module High-speed AD/DA converters VCO Summary and a few statements

14 Lower Cost & Earlier Time to Market with Si / SiGe Bipolar nm f t [GHz] 100 (0,3µm / 200 Ghz) SiGe:C NPN SiGe NPN Si NPN (0,045 µm / 200 Ghz) 22nm 32nm 3-4 Gen 45nm 65nm 130nm 250nm CMOS 100 L G [nm] nm or even 45 nm CMOS would be needed to be comparable to current state-of-the-art SiGe (pure Bipolar or BiCMOS)! July, 2010 Page 14

15 Si / SiGe Bipolar versus CMOS <= 65 nm CMOS would be needed for sufficient ft/fmax VHNRE (very high non recurring engineering cost) < 30 nm CMOS for f cut-off ~ 400 GHz Other factors favoring bipolar/ BiCMOS for analog millimeter wave applications: Lower 1/f noise Better current drive capability Better matching Better linearity Higher voltage (output power) July, 2010 Page 15

16 Gate Delay [ps] BiCMOS and SiGe Roadmap 100 OXIS3 B6HFC OXIS3: 75 ps (1985) B6HF: 25 ps (1993) B7HFC: 10 ps (2000) B7HF200: 3.8 ps (2007) B7HF500: 2.5 ps (2012) B7HF700: 1.5 ps (2015) 10 B7HFC B7HF200 B7HF500 B7HF Year July, 2010 Page 16

17 High-Speed SiGe Bipolar Technology self-aligned SiGe HBT emitter width 0.18 µm transit frequency 200 GHz max. oscillation frequency C-E breakdown voltage gate delay 200 GHz 1.8 V 3.7 ps GHz Transit Frequency 206 GHz Ref: T. Meister et al., Infineon, BCTM2003 f T 120 V BC = -1.0 V 80 V BC = -0.5 V 40 V BC = 0 V A E = 0.18 x 2.8 µm I C ma

18 SiGe:C Technology available components Three types of npn transistors Vertical pnp transistor Varactor Three resistor types Two polysilicon resistor types TaN thin film resistors MIM capacitor 4 copper metallization layers Automotive qualified and productive

19 Photonics integration, Rx+Tx Young, JSSC, Jan 2010 July, 2010 Page 19

20 Chip assemply: high frequency, precision mechanics, heat control Ref. : M. Möller, Uni Saarland, Micram July, 2010 Page 20

21 The high-speed and RF suited Package Comparison Wirebond BGA/Flip-Chip BGA/WLB DC 76 mω 7.5 mω 3.2 mω 5 GHz 375 mω 41 mω 15 mω L 1.1 nh 52 ph 18 ph Interconnect BGA Wirebond BGA Flip Chip WLB High Package parasitics Low Passive Integration in redistribution layers Package EM co-simulation July, 2010 Page 21

22 ewlb embedded wafer-level ballgrid array 300µm Organic Redistribution Chip Solder Dielectric Layer (Cu) Metallization Ball Slide 22

23 ewlb Passives: Measurement Results Parameter Min. line width [µm] Min. line spacing [µm] Value Number of layers 1 2 Typical area (1 nh) [mm 2 ] Typical area (30 nh) [mm 2 ] ewlb High-Q single / double layer inductors L = nh Q = F res = 1 35 GHz Impact of tolerances DW, DH 1 µm DL 1.5% Name N Q max L(Q max ) [nh] f(q max ) [GHz] f res [GHz] R DC [Ohm] Area [mm 2 ] L L L L L N low = 2.5 N up = 3 N =

24 Chip / Package Co-Design Interaction of package metallization and on-chip transmission lines and inductors EM co-simulation Radiation analysis Tolerance analysis Thermal management Constraints on chip size and pad placement Slide 24

25 Challenges Complex geometry of package Electrically large structures Many fine details much smaller than wavelength Consider only the important details Many parasitic effects present In the microwave transitions Reflection, mode conversion, losses In the full package Radiation, coupling to other ports Full wave 3D EM Simulation needed (HFSS, Microwave-studio, ) Large number of discrete cells needed July, 2010 Page 25

26 OUTLINE Introduction Optical communications and drivers Emerging silicon technologies and design considerations SiGe:C technology and ewlb package for optical applications Implementation examples O/E Module High-speed AD/DA converters VCO Summary and a few statements

27 Schematic of a low noise, high gain transimpedance amplifier Diff. Low input imp. I I Low noise Limiting V QD2 Limiting V QD3 Output 50 Ohm output stage TIA Amplifier Amplifier Buffer V QD1 U QD High-Frequency stages

28 Transimpedance amplifier Low noise, high gain broadband transimpedance amplifier OUT1 Silicon-Germanium technology Area: 0.97 x 0.97 mm 2 Data rate up to 10.7 Gbit/s -18dBm optical input sensitivity High transimpedance: 6 kw Low Power: 170 mw Single Power Supply: +5V Internal DC compensation loop Fits to low cost TO package OUT2 IN

29 100-Gb/s Broadband Amplifier in SiGe technology Eye diagram at 100 Gb/s X-axis: 5 ps/div, y-axis:250mv/div 3-dB bandwidth: Gain: 1-dB compr. point (input): 62 GHz 16 db -9.5 dbm 3 rd -order interc. point (input):2.1 dbm Ref.: W. Perndl

30 110 GHz Dynamic Frequency Divider in SiGe Bipolar Ref. H. Knapp et al.

31 110 GHz Dynamic Frequency Divider in SiGe Bipolar Ref. H. Knapp et al

32 110 GHz Dynamic Frequency Divider in SiGe Bipolar Ref. H. Knapp et al.

33 110 GHz Dynamic Frequency Divider in SiGe Bipolar Ref. H. Knapp et al.

34 AD- and DA- converters needed Pre-emphasis Higher Level QAM/DQPSK OFDM Multi Format, Adaptive Tx Equalization in binary Tx Higher Level QAM/DQPSK OFDM Multi-Format, Adaptive Rx Set date Page 34

35 Speed Resolution Limits ADC Time interleaved Flash FOM = 4kT BW DR P 2 N 2BW P

36 High-Speed ADC Trend: Speed vs. Resolution BiCMOS Time Interleaved ADC Enhance Speed Low Power Channel Alignment Voff Gain Jitter Krishnamoorthy et al., "Progress in Low-Pow Set date Page 36

37 High-Speed ADC Trend: Energy Efficiency Krishnamoorthy et al., "Progress in Low-Pow Set date Page 37

38 Performance overview of high-speed time-interleaved ADCs Page 38

39 CMOS 65nm flash ADC Pipelining & ping pong new bubble sort concept no boosted switches 6 Bit flash ADC in c65 65 nm CMOS Technology 6 Bit 2 * 3 5 ENOBs 250 mw

40 SiGe BICMOS 22Gs/s DAC Macro 6-bit DAC performance Technology 0.13 um SiGe BiCMOS Die area (DAC only) 1.8 x 2.5 mm 2 Transistors (DAC only) Clock DNL INL SFDR Settling time Glitch energy Power dissipation 569 bipolar 22GHz < 0.4LSB < 0.4LSB 43 35dB up to 8GHz full/half scale < 0.5pVs 3.3V supply Transmitter Pre-distortion in 10G edco Krishnamoorthy et al., "Progress in Low-Pow Set date Page 40

41 Beyond 100 GbE Next step will be 400 GbE Data rates up to 448 Gb/s including FEC Keet WDM grid -> higher order modulation formats DA-converters mandatory in Tx Very high bandwidth/enob ADCs may become bottleneck again Set date Page 41

42 Low Phase Noise VCO Design Set date Page 42

43 VCO in SiGe:C Technology VCO Technology SiGe B7HF200 SiGe B7HF200 VDD 3.3V 3.3V Pout Frequency range 19-22GHz Fc=2.6GHz VCO Phase Noise minus 136 dbc per Hz at 10 MHz minus 134 dbc per Hz at 1 MHz

44 OUTLINE Introduction Optical communications and drivers Emerging silicon technologies and design considerations SiGe:C technology and ewlb package for optical applications Implementation examples O/E Module High-speed AD/DA converters VCO Summary and a few statements

45 Summary and some statements Fiber optics was the only answer and everything else was interim SiGe:C and latest CMOS push the limits Cisco packs silicon photonics on 3D ICs 0 ADCs exploring the limits

46 Sales are deteriorating Our plan is to invent a kind of thingy, that everyone wants to buy So, I have fulfilled my job as visionary leader, how long will you need for yours? Thank you for your attention