Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

Transcription

1 C Analog Integrated Circuits and Signal Processing, 28, , Kluwer Academic Publishers. Manufactured in The Netherlands. Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle ANTONIO J. LÓPEZ-MARTÍN, ALFONSO CARLOSENA Department of Electrical and Electronic Engineering, Public University of Navarra, Arrosadía s/n. E Pamplona, Spain antonio.lopez@unavarra.es; carlosen@unavarra.es Received August 26, 1999; Revised November 3, 2000; Accepted December 8, 2000 Abstract. In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation. Key Words: analog multiplier/dividers, voltage-translinear circuits, analog CMOS circuits 1. Introduction Analog multipliers are circuits that can be readily found in many analog systems, ranging from the conventional RMS-DC converters, peak detectors, modulators, phase detectors and synthesizers, to the more recent ones, such as square-root domain transconductors [1], artificial neural networks and fuzzy logic controllers. A lot of work has been carried out in the field of analog multiplier design, and many solutions in CMOS technology are already available, either using transistors in the linear region (e.g. [2]) or in the saturation region (e.g. [3]). A recent work [4] has made apparent the underlying principles of almost all CMOS multipliers reported in the literature, which can be reduced to two basic modes of operation or, to be more precise, of nonlinearity cancellation. However, this classification applies only to the transconductance type of multipliers, i.e., those whose inputs are voltages and outputs are currents. There is still another approach that is based on the use of the translinear principle in MOS transistors operating in the saturation region, which naturally leads to current relationships of the type required, without the need for nonlinearity cancellation schemes. Address correspondence to: Antonio J. López-Martín, Dpto. Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra, Arrosadía s/n. E Pamplona, Spain, Tel.: , Fax: , antonio.lopez@unavarra.es This approach is exemplified by reference [5], where the authors apply the voltage- translinear principle with some success, but introducing a degree of complexity in the design that seems unnecessary. In the following paragraphs, novel current-mode analog multiplier/divider circuits based on either stacked or up-down voltage-translinear loops are proposed. They are suitable for standard CMOS fabrication and can be successfully applied to a wide range of different analog systems. Their main features are simplicity, precision, an area-efficient implementation due to the fact that only MOS transistors are employed, and wide dynamic range originating from the currentmode approach followed. In addition, insensitivity to temperature and process variations is inherited from its voltage-translinear nature. This paper is organized as follows: in Section 2, the basic idea behind the multiplier/divider design will be presented, which is nothing but the cascade connection of a geometric-mean cell and a slightly modified version of it; in Section 3, the voltage-translinear principle will be reviewed, in the light of its ability to produce a geometric-mean cell and also the desired multiplier/dividers. Section 4 deals with the design of the multiplier/divider using either stacked or up-down voltage-translinear loops. Simulation and measurement results obtained from both versions of the multiplier/ divider will be provided in Section 5. Finally, some conclusions will be presented in Section 6.

2 266 López-Martín and Carlosena 2. Principle of Operation Consider the following expression: I z = I x I y (1) I w I x, I y, I w and I z being current signals. Equation (1) can be equivalently written as: ( ) 2 k Ix I y I z = (2) k 2 I w k being a nonzero arbitrary constant. It becomes apparent that if we were able to calculate the geometric mean of two currents, i.e.: I out = k I x I y (3) and then to introduce the output current into a squarer/ divider circuit having the following input-output characteristic: I out = I in 2 (4) k 2 I w then, according to (2), a current-mode multiplier/ divider implementing (1) could be obtained rather elegantly. This idea is shown schematically in Fig. 1, where the geometric-mean and squarer/divider outputs have been assumed to be flowing out. Note also that the two functions required, given by equations (3) and (4), are the inverse of each other, and therefore it can be expected that both could be implemented with the same basic topology, interchanging input and output and properly adapting the impedances. The design of such two functions, geometric-mean and squarer/divider circuits, will be addressed in the following sections. 3. The Voltage-Translinear Principle The classical translinear principle based on the exponential I-V relationship of BJTs and MOS transistors in weak inversion [6] has recently been extended [7] to topologies comprising loops of MOS transistors operating in strong inversion, in which the square law characteristics lead to the realization of sums of squareroots of currents. These so-called voltage-translinear circuits [8] are based on the linear dependence of the transconductance of a MOST operating in strong inversion and the saturation mode on the gate-source voltage. Although the square law conformity on which the voltage-translinear principle relies is not as precise as the exponential conformity of BJTs, and its validity entails only approximately 1.5 decades of current [9], this principle can be successfully employed in several applications. Consider, for instance, the circuits of Figs. 2a and 2b. They represent a four-transistor voltage-translinear loop in stacked and up-down topology, respectively, with two MOSTs connected clockwise and another pair connected counterclockwise. Applying the KVL and assuming equal MOS transconductance factors and threshold voltages, the following expression is obtained for both cases: I 1 (W 1 /L 1 ) + I 2 (W 2 /L 2 ) I 3 = (W 3 /L 3 ) + I 4 (W 4 /L 4 ) (5) I i and W i /L i being the drain current and aspect ratio, respectively, of transistor M i (i = 1, 2, 3, 4). The up-down topology has some important advantages, not the least of them being the possibility of decreasing the supply voltage requirements (if a proper biasing is applied), and alleviating the V TH mismatch due to the body effect that adversely affects the stacked topology if technology precludes the connection of MOST source terminals to their bulk terminals (i.e., NMOS loops in n-well technology). Assuming, for the sake of clarity, identical transistors in the loop, and squaring both sides in equation (5), we obtain the following expression: Fig. 1. Principle of the multiplier/divider circuit. 2 I 1 I 2 + I 1 + I 2 = 2 I 3 I 4 + I 3 + I 4 (6)

3 Current-Mode Multiplier/Divider Circuits 267 Fig. 2. Voltage-translinear loop. (a) Stacked topology and (b) Up-down topology. By forcing currents I 3 and I 4 to be equal and of value: I 3 = I 4 = I 1 + I 2 + 2I z 4 where I z is a copy of the output current, I out, then: (7) I out = I 1 I 2 (8) A factor can be included in the above expression when the aspect ratio of transistors M 3 and M 4 is not equal to that of M 1 and M 2. Thus, a current-mode geometricmean function is obtained, and in order to achieve this only current copiers and adders are required to fulfil the constraint given by expression (7). The squarer/divider circuit is obtained by inverting the roles of I 1 or I 2 with I out. Since the multiplier/divider is obtained by cascading two such blocks, and the squaring (and geometric mean) functions are based directly on the square law of MOS transistors, there is no need for a linearization scheme and the multiplying/division operation will be accurate as long as the MOS transistors exhibit a square law. 4. Multiplier/Divider Design The geometric-mean and squarer/divider blocks shown in Fig. 1 can be implemented using either stacked or up-down voltage-translinear loops [10], thus leading to different multiplier/divider circuit realizations; both options will be presented subsequently. A. Stacked Topology (1) Geometric-Mean Circuit A geometric-mean circuit can be readily obtained from the stacked loop of Fig. 2a by setting: I 1 = I x, I 2 = I y, I 3 = I 4 = I x + I y + I z (9) When the four transistors are dimensioned in the following way: 4(W 1 /L 1 ) = 4(W 2 /L 2 ) = W 3 /L 3 = W 4 /L 4 (10) then, according to (5), the following dependence for I z is obtained: I z = 2 I x I y (11) Fig. 3 shows the resulting circuit; a similar approach is followed in a well-known geometric-mean circuit proposed in [7], which is also based on the aforementioned stacked topology. However, in our design PMOS transistors have been employed in the loop in order to create them in separate wells (since a n-well technology was employed), thus allowing an independent connection of their bulk terminals. The voltage-translinear loop is formed by transistors M 1 M 10 ; note that the bulk terminals of these transistors are connected to their sources, thus avoiding the body effect. M 13 and M 26 are diode-connected transistors included for alleviating the channel-length modulation effect in M 1 and M 2, respectively. Transistors M 11 M 12 form a current mirror and M 14 M 25 constitute high-swing cascode current copiers employed for injecting the required combinations of currents into the voltage-translinear loop. The circuit is designed for V DD = 5 V and V CN = 2.3 V. The aspect ratios chosen are given in Table 1. (2) Squarer/Divider Circuit The squarer/divider, shown in Fig, 4, is obtained by performing a minor change on the geometric-mean Table 1. Transistor aspect ratios in the circuit of Fig. 3a. M 1 10 M M 13 M M 26 L (µm) W (µm)

4 268 López-Martín and Carlosena Fig. 3. Geometric-mean cell using stacked loop. (a) Schematic, (b) Symbol and (c) Microphotograph. cell of Fig. 3, in order to transform its geometric-mean output into a low-impedance squarer/divider input, and one of its low-impedance inputs into the highimpedance squarer/divider output. The transistors in the squarer/divider circuitry where these changes are operated are enclosed in dotted ellipses in Fig. 4. The squarer/divider output current I out is obviously given by the inverse of equation (11): I out = I 2 z 4I w (12) (3) Multiplier/Divider Introducing as the I z input of the squarer/divider in Fig. 4 the mirrored output of the geometric-mean cell of Fig. 3, a current multiplier/divider is obtained, since: I out = I 2 z 4I w = ( 2 Ix I y ) 2 4I w = I x I y I w (13) Fig. 5 shows the resulting multiplier/divider circuit, where the output of the geometric-mean cell is inverted by a current mirror in order to properly inject it into the squarer/divider. The aspect ratio of transistors M 1 M 4

5 Current-Mode Multiplier/Divider Circuits 269 Fig. 4. Squarer/divider cell using stacked loop. (a) Schematic and (b) Symbol. Fig. 5. Voltage-translinear multiplier/divider, stacked version. forming this cascode current mirror was W/L = (56 µm/5.6 µm). B. Up-Down Topology (1) Geometric-Mean Circuit As mentioned elsewhere, the stacked topology of Fig. 2a suffers from the body effect if technology does not allow an independent connection of the bulk terminals; this can seriously affect the loop behavior. In addition, due to the pair of stacked transistors in the loop, a minimum supply voltage of twice the V GS plus the V DS of a saturated MOST carrying the maximum current for which the circuit is designed has to be ensured. Both shortcomings can be greatly alleviated by using a suitably biased up-down topology. Consider the four-most voltage-translinear loop of Fig. 2b, having equally sized MOSTs and currents: I 1 = I x, I 2 = I y, and I 3 = I 4 = (I x + I y + 2I z )/4 (14) Thus, according to (5) (7), the following output current is obtained: I z = I x I y (15) Fig. 6 illustrates this idea, which is analogous to that proposed by Mulder et al. [11]. The circuit does in

6 270 López-Martín and Carlosena Fig. 6. Geometric-mean cell using up-down loop. (a) Schematic and (b) Symbol. practice require a similar voltage supply to the stacked topology, due to the stacking of diode-connected transistors employed, thus not fully exploiting its lowvoltage capability. In [12] the authors proposed an alternative biasing scheme, allowing operation at a supply voltage as low as one V GS plus two V DS of a saturated MOST operating at the maximum current level. This is achieved by avoiding diode-connected transistors at the sources of the loop transistors. Nevertheless, this approach will not be followed here because of the lack of experimental results. The up-down voltage-translinear loop is formed by transistors M 17 M 20. Transistors M 1 M 16 and M 21 M 22 constitute simple current mirrors employed for injecting the appropriate currents into the voltagetranslinear loop; their large size allows some voltage room, and leads to a minor channel-length modulation effect and improved transistor matching (though the penalty to be paid is more chip area). The circuit is designed for V DD = 3.3 V. The aspect ratios chosen are given in Table 2. Table 2. Transistor aspect ratios in the circuit of Figure 6a. M 1 16 M M L (µm) W (µm) (2) Squarer/Divider Circuit In close agreement with previous results, a slight modification operated on the input and output branches of the geometric-mean cell of Fig. 6 leads to the current squarer/divider shown in Fig. 7. Aspect ratios were kept to their values in the original geometric-mean cell. The squarer/divider output current I out is given by: I out = I 2 z I w (16) (3) Multiplier/Divider Circuit Introducing as the I z input of the squarer/divider in Fig. 7 the mirrored output of the geometric-mean cell

7 Current-Mode Multiplier/Divider Circuits 271 Fig. 7. Squarer/divider cell using up-down loop. (a) Schematic and (b) Symbol. of Fig. 6, a current multiplier/divider is obtained, since: I out = I ( ) z 2 2 Ix I y = = I x I y (17) I w I w I w The resulting circuit is shown in Fig. 8. The aspect ratio of transistors M 1 M 4 forming the cascode current mirror was W/L = (76.8 µm/5.6 µm); V DD was 3.3 V and V CN = 1.8V. It could be clarifying at this point to remark the differences of our proposed multipliers with respect to the most widely known of the transconductance class of multipliers. In particular, multiplier Type V (according to the classification given in [4]) employs exactly the same translinear up-down loop, and thus equation (6) is also valid for it. However, the output current is obtained as: I out = I 1 + I 2 I 3 I 4 = 2 I 3 I 4 2 I 1 I 2 (18) Since currents depend quadratically on gate-source voltages, the right side of the equation (18) is composed of a linear combination of products of V GS and V TH, which cancel properly in order to give the desired product of two voltages. C. Second-Order Effects Errors due to the body effect have already been mentioned, and can be reduced by either choosing the updown topology or using independent wells for the loop transistors in the stacked topology. Other secondorder effects that can affect circuit performance include mobility degradation, channel-length modulation and threshold voltage mismatches. A brief discussion follows; a deeper treatment of second-order effects in voltage-translinear circuits can be found in [9] and [10].

8 272 López-Martín and Carlosena Fig. 8. Voltage-translinear multiplier/divider, up-down version. (a) Schematic and (b) Microphotograph. Mobility Degradation Under high field conditions in the channel, mobility of carriers decrease as a firstorder approach according to the expression: µ = µ 0 1 θ(v GS V T ) (19) where µ 0 represents the zero field mobility of carriers and θ is the mobility degradation parameter which varies typically from V 1 to 0.1 V 1. Its effect in voltage-translinear loops is to introduce high-order terms in the expression for the output current, but the deviation is usually modest for a practical range of input currents. Channel-Length Modulation The variation of the effective channel length with changes in V DS is usually modeled by modifying the expression for the drain current as follows I d = β 2 (V GS V T ) 2 (1 + λv DS ) (20) where λ is the channel-length modulation parameter, which reduces as the channel length is made larger. Transistors with low V DS (e.g., diode-connected or cascoded transistors) are almost unaffected by this effect. Since long channel transistors have been employed in our proposed multiplier/dividers, this effect tends to be negligible.

9 Current-Mode Multiplier/Divider Circuits 273 Threshold Voltage Mismatches Mismatch in the threshold voltage V TH of the loop transistors leads to a DC offset in equation (5). This DC component can be regarded as an error in the bias input currents of the multiplier/divider, and can be compensated in practice by slightly deviating them from their theoretical values. Such input bias exist if the circuit is not simultaneously employed as both multiplier and divider. 5. Simulation and Experimental Results The circuits formerly described were implemented on a monolithic IC using a n-well 2.4 µ CMOS Alcatel/ MIETEC technology. The stacked and up-down versions will be treated separately. measured multiplier/divider DC characteristics obtained for I w = 10 µa, I y values ranging from 0 µa (lower line) to 10 µa (upper line) in 2.5 µa steps and I x swept from 0 to 100 µa. Note that the resulting nonlinearity depends on the bias current setting selected for each case. Fig. 10 shows the measured output THD at 10 khz as a function of the I P /I DC ratio, I x being a 10 khz input sinusoid with peak amplitude I P and DC component I DC = 50 µa; I y and I w were set to 10 µa. Note that input current amplitudes as large as 45 µa can be safely used, leading to THD values lower than 2%. This figure is similar to that obtained in [4] for the best multipliers under similar current levels. When lower gains are required (i.e., lower I y /I w ratios), these distortion figures are notably improved. A. Stacked Topology The multiplier/divider shown in Fig. 5 was first tested. Supply voltage was V DD = 5 V. Fig. 9 illustrates the B. Up-Down Topology Similar results were obtained for the up-down version of Fig. 8; a certain loss in dynamic range is observed Fig. 9. Measured DC transfer characteristics of the multiplier/divider (stacked version) for different bias currents.

10 274 López-Martín and Carlosena Fig. 10. THD of the output waveform for different input amplitudes. since a 3.3 V supply was employed. Fig. 11 shows its output current I out measured across a 10 k resistance for identical input current sinusoids I x, I y and I w obtained by mirroring a 100 khz, 40 µa peak-to-peak input current, thus testing the circuit performance as both multiplier and divider simultaneously. From (17) and since I x = I y = I w, current I out should also be identical to them. Fig. 11 shows that this is the case. The magnitude spectrum of the output waveform is shown in Fig. 12. The measured THD is about 3%, and can be partly attributed to differences in the input currents caused by mismatching in the external circuitry that injects them. When the circuit is employed as a programmable gain cell, I y being as before and I x, I w being 10 µa bias currents, the second harmonic decreases 5 db, leading to an output THD of 1.5%. Distortion is mainly second-order in both measurements; this fact was also observed for its stacked counterpart. A four-quadrant multiplier can be readily obtained from the above multiplier/divider circuits by using a couple of them in a balanced structure. This configuration had to be simulated since only one multiplier of each type was integrated; transistor models provided by the foundry for this fabrication run were employed. Fig. 13 shows how the balanced version of the circuit of Fig. 5 can be employed as a frequency doubler. I x and I y hada10µa DC component, whereas their AC component was 5 sin(2πft) µa, with f = 10 khz; I w was equal to 10 µa. A 20 khz AC output current is observed, as expected. Similarly, Fig. 14 illustrates its simulated operation as an amplitude modulator. I x and I w were chosen as before, whereas I y was the modulating waveform, corresponding to a triangular periodic wave. The balanced arrangement also helps even-order harmonic distortion; simulations show that the secondorder harmonic is in that case 19 db lower than in the non-balanced topology at 10 khz and for identical output levels. When compared to other state-of-the-art voltagetranslinear CMOS multiplier/divider circuits, such as that proposed in [5], the performance of the multiplier/ dividers proposed here behave similarly in terms of linearity and dynamic range. Nevertheless, the circuits proposed in this paper employ just a couple of

11 Current-Mode Multiplier/Divider Circuits 275 Fig. 11. Measured multiplier/divider (up-down version) output waveform for a 100 khz, 40 µa pp input. Fig. 12. Magnitude spectrum of the multiplier/divider output waveform.

12 276 López-Martín and Carlosena Fig. 13. Balanced multiplier as a frequency doubler. Fig. 14. Balanced multiplier as an amplitude modulator. 10 khz carrier sinusoid (upper waveform); 1 khz modulating signal (middle waveform); AC modulated output (lower waveform).

13 Current-Mode Multiplier/Divider Circuits 277 Table 3. Summary of circuits performance and comparison. Ours, Ours, Multiplier/Divider Gai et al. [5] Stacked Up-Down Technology 2 µ CMOS 2.4 µ CMOS 2.4 µ CMOS Supply Voltage 5 V 5 V 3.3 V No. of MOS TL loops Max. Rel. Error 0.65% 1.2% 1.9% as multiplier (simulated) (measured) (measured) THD as gain cell Not 1% 1.5% (input: 10 KHz, available (measured) (measured) 20 µa peak) Simulated small- 18 MHz 12.3 MHz 3 MHz signal BW as gain cell Area Not 0.32 mm mm 2 available Power consumption Not 700 µw 600 µw (10 µa input bias) available voltage-translinear loops, whereas in [5] three loops are required, thus unnecessarily complicating the design and leading to an increase in power and area consumption. Table 3 summarizes some relevant results of the multiplier/dividers proposed and allows a deeper comparison. Note that speed has been sacrificed in the design at the expense of more accuracy, by using fairly large gate length transistors. 6. Conclusions A novel analog multiplier/divider scheme has been proposed; obtained by means of a rather simple and elegant method, it presents interesting features such as precision and simplicity, and can be implemented in a small area. Two versions, based on either stacked or up-down voltage translinear loops, have been presented and carefully tested. Due to the aforementioned properties, they constitute versatile building blocks suitable for being applied in a varied repertory of analog applications, including square-root domain systems, artificial neural networks and analog fuzzy hardware. References 1. López-Martín, A. J. and Carlosena, A., A systematic approach to the synthesis of square-root domain systems, In Proc. of IEEE Int. Symp. on Circuits and Systems, Orlando, FL, vol. V, 1999, pp Liu, S. I., Low voltage CMOS four-quadrant multiplier. Electron. Lett. 30(25), pp , December Saxena, N. and Clark, J. J., A four-quadrant CMOS analog multiplier for analog neural networks. IEEE Journal of Solid- State Circuits 29(6), pp , June Han, G. and Sanchez-Sinencio, E., CMOS transconductance multipliers: A tutorial. IEEE Transactions on Circuits and Systems II 45(12), pp , December Gai, W., Chen, H. and Seevinck, E., Quadratic-translinear CMOS multiplier-divider circuit. Electron. Lett. 33(10), pp , May Gilbert, B., Translinear circuits: A proposed classification. Electron. Lett. 11(1), pp , January Seevinck, E. and Wiegerink, R. J., Generalized translinear circuit principle. IEEE Journal of Solid-State Circuits 26(8), pp , August Gilbert, B., Translinear circuits: An historical overview. Analog Integrated Circuits and Signal Processing 9(2), pp , March Wiegerink, R., Analysis and Synthesis of MOS Translinear Circuits. Ph.D. Thesis, Twente University of Technology, Enschede, Eskiyerli, M. and Payne, A. J., Square Root Domain filter design and performance. Analog Integrated Circuits and Signal Proc. 22, pp , March Mulder, J., van der Woerd, A. C., Serdijn, W. A. and van Roermund, A. H. M., A 3.3 V current-controlled - domain oscillator. Analog Integrated Circuits and Signal Processing 16(1), pp , April López-Martín, A. J. and Carlosena, A., Geometric-mean based current-mode CMOS multiplier/divider. In Proc. of IEEE Int. Symp. on Circuits and Systems, Orlando, FL, vol. I, 1999, pp Acknowledgment Financial support from the CICYT under grant (TIC 97/0418-C02-01) and the Gobierno de Navarra are gratefully acknowledged. Antonio J. López-Martín obtained its M.Sc. and Ph.D. degrees from the Public University of Navarra, Pamplona (Spain) in 1995 and 1999, respectively. He has been at the New Mexico State University, Las

14 278 López-Martín and Carlosena Cruces, and the Swiss Federal Institute of Technology, Zurich, as an invited researcher. Currently, he is Assistant Teacher at the Public University of Navarra. His research interest include companding analog signal processors, low-voltage analog and mixed-mode integrated circuits, integrated sensor interfaces and fuzzy hardware. the Ph.D. in physics in 1985 and 1989, respectively from the University of Zaragoza, Spain. From 1986 to 1992 he was Assistant Teacher in the Department of Electrical Engineering and Computer Science of the University of Zaragoza. From October 1992, he has been an Associate Professor at the Public University of Navarra, where he has also served as Head of the Technology Transfer Office. In March 2000 he promoted to Full Professor in the same University. He has also visited other Universities such as the Swiss Federal Institute of Technology (Zurich) and the New Mexico State University. His research interests are in the areas of classical circuit theory, analog circuits and signal processing, digital signal processing and instrumentation, where he has published about fifty papers in international journals and a similar number of conference presentations. Alfonso Carlosena was born in Navarra (Spain) in He received the M.Sc. degree with honors and