THE phase-locked loop (PLL) is a major component

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1 1220 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 A 150-MHz Translinear Phase-Locked Loop Alison Payne, Member, IEEE, Apinunt Thanachayanont, and C. Papavassilliou, Member, IEEE (Invited Paper) Abstract This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode log-domain oscillator in a classical PLL topology to obtain these features. The PLL has been fabricated in a 0.6-m 12-GHz BiCMOS process, and measured results show a capture range of 15 MHz at a center frequency of 150 MHz. The circuit operates from a single 3-V supply and draws 6 ma at 150 MHz. A phase noise of 080 dbc/hz at 1 khz offset was obtained with the PLL locked onto an input reference frequency of 151 MHz. The PLL response to a frequency-modulated input has also been examined, and the demodulated output at 100 khz showed less than 030-dB total harmonic distortion. Index Terms Integrated oscillators, log-domain circuits, phase-locked loops, translinear circuits. I. INTRODUCTION THE phase-locked loop (PLL) is a major component in numerous applications. particularly in the field of communication electronics, such as demodulators, frequency synthesisers, clock recovery, and tracking filters [1]. A conventional voltage-mode PLL employs a voltage-controlled oscillator (VCO), phase detector and loop filter, and (optionally) a variable gain circuit to control the oscillation amplitude [2]. In practice, the voltage-mode operation of the PLL may limit the tuning range of the VCO, the linear dynamic range of the multiplying phase detector, and the maximum oscillation amplitude, particularly when operating at low supply voltages. Current-mode analog signal processing has emerged more recently as an alternative approach to traditional voltage-mode designs [3]. In certain applications, a current-mode solution may lead to performance advantages such as increased bandwidth or dynamic range under low power supply operation, due to reduced voltage swings. Translinear circuits and log-domain filters are both true current-mode synthesis methods which exploit the largesignal exponential characteristics of bipolar junction transistors (BJT s). The translinear principle (TLP), as originally proposed in 1975 by Gilbert [4], is typically used to implement large-signal linear and nonlinear real-time functions [5]. More recently, the state-space synthesis of log-domain filters has Manuscript received December 2, 1997; revised May 3, This paper was recommended by Guest Editor C. Toumazou. The authors are with the Department of Electrical and Electronic Engineering, Imperial College of Science, Technology, and Medicine, London SW7 2BT, U.K. Publisher Item Identifier S (98) Fig. 1. The PLL architecture. been described by Frey [6], and the log-domain technique has since received considerable interest due to the potential for high-frequency operation, inherent tunability, and wide dynamic range under low power supply voltages. Various logdomain synthesis methods and circuit implementations have been reported to date, e.g. [6] [11]. This paper presents a true current-mode analog PLL implemented in BiCMOS technology. The PLL architecture is comprised of a phase detector, a loop filter, and a controlled oscillator, as shown in Fig. 1. A four-quadrant translinear current multiplier is used for phase detection, and a currentmode low-pass filter is employed for loop filtering. A currentcontrolled current-mode log-domain oscillator is realized using state-space synthesis; since the log-domain oscillator has a wide linear tuning range over several decades of frequency [11], the operational frequency range of the current-mode PLL is not limited by the linear frequency tuning range of the controlled oscillator, as in a conventional voltage-mode PLL. A translinear current gain cell is added to control the level of oscillation, and a current amplifier adjusts the overall loop gain of the PLL. This paper is organized as follows. Section II describes the design of the individual PLL components. Section III discusses the effect of transistor nonidealities, measured results are presented in Section IV, and conclusions are given in Section V. II. PLL COMPONENTS A. Log-Domain Oscillator The operation of an ideal oscillator can be described by the linear transfer function where defines the frequency of oscillation. (2-1) /98$ IEEE

2 PAYNE et al.: A 150-MHz TRANSLINEAR PHASE-LOCKED LOOP 1221 Fig. 2. Log-domain oscillator. Equation (2-1) is equivalent to the following set of statespace equations: (2-2) where is the input, is the output, and and are the state variables. The following exponential mappings are defined: (2-3) where is the reverse saturation current and is the thermal voltage corresponding to the large-signal exponential characteristic of a forward-biased BJT. Applying these mappings to the state-space equations given in (2-2), and multiplying by a constant scaling factor results in a set of nodal equations: (2-4) where The left-hand side of (2-4) represents currents flowing through a pair of grounded capacitors, each of value having voltages and across them, respectively. The nonlinear expressions on the right-hand side of (2-4) can be implemented using simple current-mode processing blocks [11]. Fig. 2 shows a complete schematic diagram of the logdomain oscillator. MOSFET s are used to provide dc bias currents, since p-n-p devices in this technology exhibit poor characteristics. The output of the oscillator can be taken from the collector current of the transistor In the complete PLL, the oscillator is required to drive the following differential current gain cell. This is obtained by a push pull output Fig. 3. Current gain cell. configuration having an extra buffered output current, which is mirrored off the positive supply by using an additional current mirror. A large-signal analysis shows that the dc current at the emitters of and should be tuned to place the poles slightly to the right-hand side of the complex frequency plane in order to start oscillation [11] The frequency of oscillation is linearly tuned by varying the bias current in the PLL application, the signal tuning current from the loop amplifier is superimposed onto the dc tuning current Since the sensitivity of the log-domain oscillator is given by (2-5) Since can be fairly large (1 MHz/ A), the PLL lock range is not limited by the controlled oscillator, as in a conventional voltage-mode PLL. At large the maximum frequency of the oscillator tuning range is limited by the drain-source voltage required to operate the MOSFET current sources.

3 1222 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 Fig. 4. Current multiplier as a phase detector. The dc level of the output current varies as the sum of bias current and the control current. A current gain cell is, therefore, required to control the dc level and amplitude of the oscillator output current before feeding it to a current multiplier (phase detector). The effects of transistor nonidealities on oscillator performance will be discussed in Section III. B. Current Gain Cell A current gain cell is used to control the dc level and amplitude of oscillation and generates a differential output current to drive the following balanced phase detector. The translinear gain cell shown in Fig. 3 is a modified version of the well-known Gilbert gain cell [5]. Applying the TLP to the loop of transistors and neglecting the effect of base currents: (2-6) where is a modulation index defined as the ratio of the peak amplitude of the signal to the dc bias current, i.e., Since the differential output current (2-7) The small-signal current gain is equal to and can easily be adjusted by varying the ratio of bias currents. In practice, is set to control the dc level of the output current, while controls the small-signal current gain [13]. As the modulation index increases, nonlinear output terms are generated. These are generally removed by the PLL loop filter, however, the input modulation of the gain cell should be limited to ensure that false locking of the PLL onto one of these spurious harmonics does not occur. The effects of transistor nonidealities on the performance of the gain cell are similar to those discussed by Gilbert in [14] and will only be mentioned briefly here. The current gain cell is sensitive to finite beta which causes constant dc gain error, while transistor area mismatches and series ohmic resistances introduce distortion terms at the output. C. Current-Multiplier Phase Detector The PLL circuit employs a current-mode phase detector which is implemented by a standard four-quadrant translinear multiplier with predistortion circuit [5]. Fig. 4 shows the current multiplier, where the input (reference) differential current signal is applied to the predistortion circuit and while the differential output current from the current gain cell is applied to the emitters of transistors The sensitivity of the phase detector depends on the amplitude of the input signal and the oscillator output, thus, a preceding gain stage is required in practical circuits for better controllability of the input signal [12]. Distortion in the multiplier due to transistor nonidealities is well addressed by Gilbert in [15]. Area mismatches and ohmic resistances lead to parabolic (even-order) and cubic (odd-order) distortions, respectively, while finite beta affects the gain accuracy of the multiplier, but has negligible impact on distortion. D. Loop Filter The order of the PLL system is determined by the loop filter. A higher order loop filter will provide greater attenuation for high-frequency noise components, but makes the loop susceptible to gain and temperature variations and may cause stability problems. A first-order lead lag filter was, therefore, chosen, since it provides a larger phase margin than a simple low-pass filter and, as a result, the PLL is more stable, leading to a shorter pull-in time. However, the tradeoff is a degradation in the attenuation of high-frequency signals. The lead lag filter is implemented using two log-domain lossy integrators [16], as shown in Fig. 5. A zero is obtained by implementing a feedforward path via transistors and Applying the TLP to one-half of the circuit neglecting finite base currents, gives (2-8) where the capacitor current and Combining these expressions and noting that where gives the transfer function of the lead lag filter: (2-9)

4 PAYNE et al.: A 150-MHz TRANSLINEAR PHASE-LOCKED LOOP 1223 Fig. 5. Lead lag filter. Fig. 7. Log-domain integrator. Fig. 6. Current amplifier. where and is, thus, used to set the pole position, while is tuned to adjust the position of the zero and the dc gain of the filter. Note that, if required, the number of transistors can be further reduced by combining the functions of the multiplier and the lead lag filter, as demonstrated in the recently proposed translinear circuit for phase detection [17]. E. Current Amplifier The beta-immune type A translinear Gilbert gain cell [5] is used as a current amplifier to adjust the overall loop gain of the PLL system. The gain cell is shown in Fig. 6, and applying the TLP to transistors (neglecting finite base currents) shows that the signal gain of this cell is equal to the ratio The amplifier is separated from the loop filter, allowing independent control of the loop gain and bandwidth. Distortion caused by area mismatches and ohmic resistances is similar to that of the current gain cell (Section II-B). Finite beta has almost no effect on the accuracy of the circuit due to its beta immunity [14], provided that values are closely matched. III. EFFECTS OF TRANSISTOR NONIDEALITIES AND NOISE ON DYNAMIC TRANSLINEAR CIRCUITS Log-domain and translinear circuits are synthesized by assuming an ideal exponential characteristic between collector current and base emitter voltage. In practice, nonideal effects, such as series ohmic resistance and finite base currents, will degrade the true exponential relationship. Due to a lack of space, in the following section, the effects of transistor nonidealities will be analyzed for a simple log-domain integrator. The result from this analysis will be used to draw more general conclusions for the oscillator and lead lag filter circuits. The effects of transistor nonidealities for the translinear multiplier and gain cells have been briefly discussed in Section II [13], [14] and will not be repeated here. The schematic diagram of the log-domain lossy integrator [16] is drawn in Fig. 7. Assuming an ideal exponential characteristic for each transistor, applying the TLP to gives (3-1) Since and (3-1) can be written as which clearly describes a lossy integrator. (3-2) A. Area Mismatches Emitter area mismatches cause variations in the saturation current between transistors. Taking the emitter area into account, (3-2) can be rewritten as (3-3) where It is clear from (3-3) that area mismatches introduce only a change in the proportionality constant or dc gain of the

5 1224 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 integrator and do not have any effect on the linearity or time constant of the circuit. The gain error can be compensated for easily by adjusting one of the dc bias currents. B. Finite Beta Assuming all transistors have equal (3-2) becomes modified to the nonlinear differential equation given in (3-4) (neglecting the terms with or higher in the denominator): (3-4) An analytic solution to (3-4) is difficult to obtain, thus, a qualitative discussion is presented. At low frequencies, neglecting the differentiation terms, finite beta causes a dc gain error and a quadratic (even-order) distortion. At high frequencies, (3-4) shows that the differentiation term is modified depending on the values of and Therefore, scalar error and modulation in the time constant of the integrator are expected. In practice, the effects of finite beta are further complicated, due to its dependence on frequency and device collector current. C. Ohmic Resistances Ohmic resistances include the base and emitter diffusion resistance and the resistance of interconnect and contact interfaces. For simplicity, all these resistances can be referred to the emitter as an equivalent ohmic emitter resistance. A new effective base emitter voltage can be written as the difference of the applied p n junction diode voltage and the voltage dropped across the equivalent emitter resistance : thus, where (3-5) By writing the collector currents as in (3-5) and assuming all emitter resistances are equal, the log-domain integrator can now be described by a nonlinear differential equation, approximately given by (3-6) Equation (3-6) can be solved by using a brute-force method [18]. The results show that the distortion caused by the equivalent emitter resistance is frequency dependent and peaks around the cutoff frequency of the integrator. Equation (3-6) also indicates an error in the time constant of the integrator (a shift in cutoff frequency; see [19]). Moreover, this error Fig. 8. Microphotograph of the test chip. is related to the instantaneous value of the input and output signal levels. D. Early Effect The Early effect (basewidth modulation) causes the collector current to vary with the collector emitter and base-collector voltages. Considering the variation of collector emitter voltage, the collector current can be written as where is the forward-biased Early voltage. An analysis of the integrator shows that the Early effect of the BJT s introduces a scalar error to the dc gain of the circuit, as in the case of the effect of area mismatches. In practice, the basewidth modulation of the devices also introduces distortion, because and are signal dependent. However, since voltage swings in current-mode circuits are minimized this is not believed to be a major source of distortion. This qualitative analysis has shown that transistor nonidealities, including finite beta, ohmic resistance, and Early voltage are sources of error within log-domain circuits. Drawing general conclusions for the PLL lead lag filter, we can expect a dc gain error, a shift in the cutoff frequency (which depends on the input signal level), and output distortion terms which are frequency dependent. Similarly, for the oscillator, we can expect a shift in the oscillation frequency (which is signal dependent) and output distortion terms (which are frequency dependent). The signal-dependent frequency error in the oscillator may be critical in determining phase noise performance, therefore, it is crucial to minimize these device nonidealities. Oscillator phase noise is discussed further in Section III-F. E. Noise Noise in instantaneous companding systems and dynamic translinear (log-domain) circuits has been discussed in some detail elsewhere [20] [23], and a complete treatment is beyond the scope of this paper. For linear (noncompanding) circuits, noise is generally assumed to be independent of signal level, and signal-to-noise ratio (SNR) increases with signal level. This is not true for log-domain systems. At small input signal levels, the noise

6 PAYNE et al.: A 150-MHz TRANSLINEAR PHASE-LOCKED LOOP 1225 (a) (a) (b) Fig. 9. Frequency tuning characteristic of the log-domain oscillators. (a) 4-pF oscillator. (b) 2-pF oscillator. Fig. 10. (b) Measured output harmonic distortion. (a) f o =70:5 MHz (4-pF oscillator). (b) f o = 650 MHz (2-pF oscillator). value can be assumed approximately constant, and an increase in signal level will give an increase in SNR. At high signal levels, the instantaneous value of noise will increase and, thus, the SNR levels out at a constant value. This can be considered as an intermodulation of signal-noise power [21]. For class-a circuits, which are employed in the PLL circuits presented here, the peak value of the signal is limited by the dc bias current. In this case, the large-signal noise is found to be of the same order of magnitude as quiescent noise and, thus, a linear approximation is generally acceptable [23] (this is not the case for class-ab circuits). F. Phase Noise The phase noise of an oscillator can be considered as the inverse of the SNR of the circuit. In a linear (noncompanding) oscillator, the phase noise is usually reduced by enlarging the oscillation amplitude [24], therefore, increasing the SNR, since noise is generally signal independent. This method of reducing phase noise is efficient as long as the oscillation amplitude is within the maximum allowable signal swing of the circuit. This approach can also be employed in the log-domain circuits up to a certain point. As the signal level increases, the SNR will also increase until it saturates to a value determined by the capacitance value and the excess noise factor of the circuit [22]. Therefore, one way to improve the phase noise of the logdomain oscillator is to have the capacitance values as large as possible, which, of course, is at the expense of power consumption. A further problem with increasing the signal level is that the effects of transistor nonidealities become more pronounced.

7 1226 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 (a) Fig. 12. Tuning characteristic of the filter 03-dB bandwidth. voltage is determined by the oscillator requirements, and all other circuits could operate down to 2 V. The power supply requirements of the oscillator could be further reduced by using an alternative log-domain architecture [9]. Balun transformers were used to convert single-ended to fully differential signals, and vice versa. Frequency-domain measurements were obtained using an HP-8560A spectrum analyzer and an HP- 8753D network analyzer. All simulation results presented here were obtained using HSPICE with layout-versus-schematic (LVS) matched circuits, including the test environment (except balun transformers). (b) Fig. 11. Measured output spectra of the oscillator around the fundamental frequencies. (30-kHz resolution bandwidth). (a) f o =70 MHz (4-pF oscillator). (b) f o =650MHz (2-pF oscillator). In particular, the oscillation frequency error increases with input signal amplitude, as described above, and may cause significant phase noise. Also, distortion and harmonic terms increase, which may further mix within the oscillator, causing additional noise terms close to the oscillation frequency. These issues are currently still under investigation. IV. EXPERIMENTAL RESULTS The PLL was fabricated in a 0.6- m 12-GHz BiCMOS technology provided by Ericsson. Fig. 8 shows the microphotograph of the test chip, which is housed in a standard leadless chip carrier (LCC) package. The prototype chip includes a complete PLL, two oscillator test circuits, a lead lag filter test circuit, and a current-multiplier phase-detector test circuit. The active area of the PLL (including probe pads) is 0.6 mm Unless stated otherwise, all measurements reported here were conducted with a single 3-V supply; this power supply A. Log-Domain Oscillator Test Circuits Two separate log-domain oscillators were implemented. These were identical, except for the capacitor values, which are 2 and 4 pf, respectively. The output of the oscillator test circuits were measured using a high-frequency (ground signal ground) Cascade Microtech probe to eliminate the issue of package parasitics. An on-chip 50- resistor was placed between the collector of and the positive supply (see Fig. 2) to convert the output current to voltage and to provide correct termination for the probe. The main disadvantage was the relatively low signal level to the spectrum analyzer, so a wide-band preamplifier was included between the probe output and the spectrum analyzer, in order to boost the signal level and improve the SNR of the test setup. Fig. 9 compares the simulated and measured frequency tuning characteristic of the oscillators and shows a measured tuning range of over 200 MHz for the 4-pF oscillator and 600 MHz for the 2-pF oscillator. At higher current levels, the measured oscillation frequency for a given is lower than the simulated value, due to errors in the MOSFET current mirrors and, also, to increased operating temperatures at high oscillation frequencies. Since (see Section II), an increase in temperature will lead to a reduction in

8 PAYNE et al.: A 150-MHz TRANSLINEAR PHASE-LOCKED LOOP 1227 (a) (a) (b) Fig. 13. Pole tuning of the lead lag filter. (a) Magnitude response. (b) Phase response. (b) Fig. 14. Zero tuning of the lead lag filter. (a) Magnitude response. (b) Phase response. the oscillation frequency In practice, this variation would be eliminated by ensuring that is proportional to absolute temperature (PTAT). Also, increased voltage drops across ohmic resistances at high current levels will cause a shift in the oscillation frequency (see Section III). Fig. 10 shows the measured output harmonic distortion of the oscillator test circuits. The second harmonic products are at 30 dbc, and these distortion figures remain fairly constant over the tuning range. In the complete PLL implementation, a fully balanced configuration is employed and, so, the second harmonic components are expected to be cancelled. Fig. 11 shows the oscillators output spectra around a fundamental frequency of 70.5 and 650 MHz for the 4- and 2-pF oscillators, respectively. The spectrum resolution bandwidth is 30 khz, so the measured phase noise values are estimated at 93 dbc/hz for the 4-pF oscillator and 85 dbc/hz for the 2-pF oscillator at 1-MHz offset. Phase noise values of 90 and 78 dbc/hz were obtained at 100-kHz offset from the carrier at oscillation frequencies of 5 and 40 MHz, respectively. B. Multiplier Phase Detector and Current Gain Cell The current multiplier and the current gain cell were combined as one test circuit. The input signals, supplied as voltages, were converted to differential input currents by using off-chip balun transformers together with on-chip V- I converters, designed as simple degenerated emitter-coupled pairs. The measured conversion gain of the current-multiplier phase detector was 10 A/rad at an input signal power of 15 dbm. The conversion gain is linearly dependent on the power of the input signal up to 10 dbm. The functionality of the gain cell was also experimentally verified.

9 1228 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 Fig. 15. Measured two-tone intermodulation products of the lead lag filter. Fig. 17. filter. Measured third-order intermodulation intercept point (IP3) of the Fig. 16. Measured harmonic distortion of the lead lag filter. C. Log-Domain Lead Lag Filter The loop filter in the complete PLL test circuit was implemented with 4-pF capacitors. A fully balanced input signal current was supplied by an off-chip balun transformer together with external 10-k resistors and 10-nF dc-blocking capacitors. The signal level of a class-a circuit is assessed meaningfully by quoting its modulation index which is defined as the ratio of the peak amplitude of the signal to the dc bias current (see Section II-B). Frequency responses of the filter were measured with an input modulation index of Fig. 12 compares the measured and simulated 3-dB bandwidth of the lead lag Fig. 18. Measured output of the PLL in freerunning and locked conditions (10-kHz resolution bandwidth). filter as is varied. Fig. 13 shows the effect of tuning the bias current, which controls the position of the pole and, also, the dc gain of the filter [refer to (2-9)]. Fig. 14 shows the effect of tuning which controls the position of the compensating zero and also varies the filter dc gain. The linearity of the lead lag filter was examined by both harmonic and two-tone intermodulation distortion tests. The output of the filter was taken from the balun transformer, which converts a differential output current to a single-ended voltage. Fig. 15 shows the third-order intermodulation products, with the input tones at 5.5 and 6 MHz and a filter bandwidth of 15 MHz. The in-band third-order

10 PAYNE et al.: A 150-MHz TRANSLINEAR PHASE-LOCKED LOOP 1229 Fig. 19. Measured waveforms when the PLL locks at 140 MHz (upper trace: input signal; lower trace: oscillator output). (a) Fig. 20. (b) Measured demodulated signal at 100 khz when the PLL locks at 140 MHz. (a) Time-domain waveform. (b) Frequency-domain spectrum.

11 1230 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 9, SEPTEMBER 1998 TABLE I MEASURED PLL PERFORMANCE intermodulation products are 40 db below the fundamental, and the second-order products are greatly reduced. Fig. 16 shows the output harmonic distortion of the filter, with an input signal at 5 MHz and a filter bandwidth of 20 MHz. The second and third harmonics are at 50 and 40 db, respectively. Fig. 17 shows the output-referred third-order intermodulation intercept point (IP3) of the filter as 15 dbm. D. PLL Operation The PLL was tested using a 4-pF oscillator. An input reference signal, supplied as a voltage from an HP-8647A RF signal generator, is converted to a differential current by using an off-chip balun transformer and an on-chip V I converter, designed as a simple degenerated emitter-coupled pair. A single-ended output from the gain cell is mirrored into a 10-k resistor, which is driven off chip. The control input to the oscillator is also mirrored as an output into an off-chip 1- nf capacitor, which is used to monitor the demodulated output when the PLL functions as an FM demodulator. The PLL was able to lock onto input frequencies from 1 to 150 MHz, exhibiting a capture range of 15 MHz at a freerunning frequency of 150 MHz. For symmetrical input of the following gain cell, the bias current must be twice as large as the dc offset current of the push pull outputs of the oscillator, which is in the order of and increases with frequency. The maximum allowable drain-source voltage of the MOSFET current source limits the maximum value of which, in turn, decides the maximum value of, hence, the maximum operating frequency of the PLL. Fig. 18 shows the measured outputs in the frequency domain with a resolution bandwidth of 10 khz. The spectrum to the left corresponds to the freerunning frequency of the PLL at 151 MHz, exhibiting a phase noise of 70 dbc/hz at 250-kHz offset. The phase noise greatly reduces to 80 dbc/hz at 1-kHz offset (determined by the phase noise of the reference input signal) when the PLL is locked, as shown by the spectrum to the right. Fig. 19 shows the PLL input and the mirrored output of the current gain cell when the loop is locked at 140 MHz. The measured PLL closed-loop bandwidth is 8.7 MHz. The response of the PLL to a frequency-modulated input was also examined by applying an FM signal with 100-kHz modulation centered at 140 MHz. Fig. 20 shows the demodulated signal in both time and frequency domain, suggesting a total harmonic distortion less than 30 db. This value is large due to the distortion introduced by the simple on-chip V I converters, which, unfortunately, could not be eliminated. Table I summarizes the performance of the PLL. The prototype PLL has demonstrated the feasibility of using simple translinear circuits in a more complex system. The proposed technique is attractive for the complete controllability and tunability of the PLL, however, much work still has to be done to improve the PLL performance, particularly phase noise, speed, and dynamic range, while reducing power consumption. In comparison with some of the recently reported PLL s operating in the same frequency range [25], [26], the current-mode PLL operates with wide tuning range and dissipates less power under lower supply voltage. V. CONCLUSION This paper has described the design and implementation of a current-mode PLL using a log-domain oscillator. The loop is realized by simple current-mode building blocks based upon the TLP, thus, it has the potential for high-frequency operation, inherent electronically tunability, and wide dynamic range under low supply voltage. An experimental prototype PLL dissipates 18 mw from a single 3-V supply when locked onto an input reference signal at 150 MHz, with a capture range of 15 MHz. With emerging low-voltage high-frequency log-domain techniques [23], [27], the authors believe that the current-mode operation of the PLL could be pushed into the gigahertz frequency range. In contrast to more conventional state-of-the-art PLL s [28], [29], the major benefit of these current-mode log-domain circuits is thought to be the potential for wide tuning range under low power supply voltages. ACKNOWLEDGMENT The authors would like to thank the Ericsson Microelectronics Research Centre for fabricating the test chip and, in particular, N. Tan for good hospitality and cooperation during the time of layout in Sweden. REFERENCES [1] B. Razavi, Monolithic Phase-Locked-Loops and Clock Recovery Circuits. Piscataway, NJ: IEEE Press, [2] F. M. Gardner, Phaselock Techniques. New York: Wiley, [3] C. Toumazou, F. J. Lidgey, and D. G. Haigh, Eds., Analog IC design: The current-mode approach, in IEE Circuits and Systems Series 2. London, U.K.: Peregrinus, 1990.

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