PAPER A 1-V, 1-V p-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors

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1 750 IEICE TRANS. ELECTRON., VOL.E82 C, NO.5 MAY 1999 PAPER A 1-V, 1-V p-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors Koichi TANNO a), Okihiko ISHIZUKA, and Zheng TANG, Members SUMMARY In this paper, a four-quadrant analog multiplier consisting of four neuron-mos transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supplyvoltage. The theoretical harmonic distortion caused bymobilitydegradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-polylayer. Simulations of the proposed multiplier demonstrate that the linearityerror of 0.77% and a total harmonic distortion of 0.62% are obtained with fullscale input conditions. The maximum power consumption and 3 db bandwidth are 9.56 µw and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm. key words: multiplier, low voltage, low-power, neuron-mos transistor, analog integrated circuit 1. Introduction Analog multipliers are important building blocks in many signal processing circuits such as modulation circuits, frequency translation circuits, fuzzy controllers and neural networks. In particular, many multipliers are required for development of fuzzy controllers. In the realization of defuzzification circuits (located in the last block of fuzzy controllers), the number of multipliers is directly proportional to the number of fuzzy rules [1]. When the product-sum composition is used as a fuzzy reasoning method, the number of multipliers strongly depends on not only the number of fuzzy rules but also the number of fuzzy variables [2]. Furthermore, the circuits with a large input range are required because various signals from sensors are treated in the fuzzy controllers [1]. From the above discussion, it is determined that low-power and wide-input-range multipliers are required for development of fuzzy controllers with many fuzzy rules. In other words, the low-power and wideinput-range multipliers ease restrictions on the number of fuzzy rules which accumulate in LSI. On the other hand, the Gilbert cell, using the variable transconductance technique, is very popular in bipolar technology and is widely used [3], [4]. MOS analog multipliers using the same technique which are the MOS version of the Gilbert cell or the voltagecontrolled transconductance technique which is realized Manuscript received July 13, Manuscript revised October 29, The authors are with the Faculty of Engineering, Miyazaki University, Miyazaki-shi, Japan. a) tanno@esl.miyazaki-u.ac.jp by MOS transistors operating in the triode region have also been proposed [5] [7]. In particular, some multipliers using the multi-tail technique were proposed by Kimura [8]. They consist of a small number of devices and can be operated at low voltages. Recently, a novel analog multiplier has been proposed by Mehrvarz and Kwok [9]. This multiplier consists of neuron-mos transistors (νmos transistors)proposed by Shibata and Ohmi [10]. The input range of the νmos multiplier is equal to 100% of the supply voltage with very small values of nonlinearity and total harmonic distortion (THD). This improvement is a distinctive feature of the νmos multiplier. However, this multiplier needs high supply voltages such as ±5 V. According to Mehrvarz and Kwok [9], the supply voltages can be reduced to ±2 V, but there is no guarantee that the full-scale input range will be achieved. In this paper, a four-quadrant multiplier with low power and wide input range is proposed. The proposed multiplier consists of four νmos transistors and can be operated at a power supply of only 1 V with a fullscale input range (namely, 1 V p-p). Therefore, the proposed multiplier is very useful for hardware realization of fuzzy controllers. The design specifications of the multiplier were determined with respect to the application to fuzzy controllers. The detailed specifications are a power consumption less than 20 µw (in order to accumulate 100 fuzzy rules), both linearity error and THD less than 1% and bandwidth larger than 10 MHz under the full-scale input condition [1]. First, the conditions for the full-scale input range are derived. Next, the νmos multiplier operable at 1 V with the full-scale input range is designed based on the derived conditions. Then, the second-order effects, such as mobility degradation, load resistance mismatch, transconductance parameter mismatch, threshold voltage mismatch and capacitive weight mismatch, are analyzed in detail. Finally, the proposed multiplier is evaluated using HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. 2. Four-Quadrant νmos Multiplier 2.1 νmos Transistor Figure 1(a)shows the basic structure of the νmos transistor proposed by Shibata and Ohmi as a func-

2 TANNO et al: A 1-V, 1-V P-P INPUT RANGE, FOUR-QUADRANT ANALOG MULTIPLIER 751 (a) (b) (c) larger than the threshold voltage of the νmos transistor, as seen from the floating gate (V T ), the drain to source voltage (V ds )is larger than V fs V T and the initial charge of the floating-gate equals 0, the νmos transistor operates in the saturation region. I ds of the k-input νmos transistor under the saturation region is [10], [11] ( k I ds = 1 2 µc W C i OX L C 0 + k j=1 C V i j = K 2 V s V T ) 2 i=1 ( k ) 2 W i V i V s V T, (1) i=1 where µ is the electron mobility, C OX is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, C i is the capacitance between the floating gate and i-th input gate, C 0 is the oxide capacitance between the floating gate and the substrate, V s is the source voltage of the νmos transistor and V T is the threshold voltage of the νmos transistor, as W seen from the floating-gate. In Eq. (1), K = µc OX and W i = C i C 0 + P k j=1 C j are defined and referred to a transconductance parameter and capacitive weight, respectively. L 2.2 Principle of Operation (d) Fig. 1 Neuron-MOS transistor (νmos transistor). (a) An illustration of the cross-sectional structure of a νmos transistor with two inputs, (b) capacitive model of the νmos transistor, (c) symbolic representation of the νmos transistor and (d) physical layout of the νmos transistor. tional MOS transistor featuring a gate-level weighted sum and threshold operation [10]. It consists of an n- channel MOS transistor with a floating gate (first poly layer)over the channel and, in some cases, extends to the field-oxide area. Multiple input gates are formed by the second poly layer over the floating gate. The capacitive coupling between the multiple input gates and the floating gate is shown in Fig. 1(b). C 0 shown in Figs. 1(a)and 1(b)is the capacitance between the floating gate and the substrate. Figure 1(c)is the symbolic representation of a νmos transistor. Now, in the case of a k-input νmos transistor, capacitances between the multiple input gates and the floating gate are defined as C 1, C 2,, C k, in order, from the drain side as shown in Fig. 1(c)(Fig. 1(c)is an example of the case of k = 2). Figure 1(d) shows an example of the physical layout of a νmos transistor. When the floating gate to source voltage (V fs )is Figure 2(a)shows the proposed four-quadrant νmos multiplier. The difference between the Mehrvarz s multiplier [9] and the one proposed is the tail current source, which is removed in the proposed multiplier. The tail current source is required to have a high output resistance for highly accurate operation. In order to achieve this, a double cascode current mirror is often used. However, the operation voltage increases when the double cascode current mirror is used as the tail current source, meaning that the power consumption increases. Besides, since the tail current source is not required in the proposed multiplier, we can expect that the proposed multiplier operates at a low voltage. On the other hand, the linearity error and bandwidth of the multipliers strongly depend on the currents through the νmos transistors. The increase of the current causes the decrease of the linearity error and the increase of the bandwidth. However, the the power consumption increases. Because the linearity and bandwidth of Mehrvarz s multiplier can be set by the value of the tail current, they can be adjusted by the external or internal current source, while the linearity and bandwidth of the proposed multiplier cannot be adjusted because they can be set by W/L of νmos transistors. With the foregoing and the design specification in mind, the

3 752 IEICE TRANS. ELECTRON., VOL.E82 C, NO.5 MAY 1999 I ds1 = K [ W1 (v x + V B1 )+W 2 (v y + V B1 ) 2 ] 2 + W 3 V B2 V T (2) I ds2 = K 2 (W 1V B1 + W 2 V B1 + W 3 V B2 V T ) 2 (3) I ds3 = K [ W1 (v x + V B1 )+W 2 V B1 2 ] 2 + W 3 V B2 V T (4) I ds4 = K [ W1 V B1 + W 2 (v y + V B1 ) 2 ] 2 + W 3 V B2 V T (5) By setting C 1 equal to C 2, v out, using Eqs. (2) (5), is given by (a) v out = V o2 V o1 = R L (I o1 I o2 ) [ = R L (Ids1 + I ds2 ) (I ds3 + I ds4 ) ] = KW1 2 R L v x v y. (6) Thus, Eq. (6)yields four-quadrant multiplication. The gain of the multiplier is dependent on K, W 1 and R L. The output is converted into a current signal by using a current mirror instead of resistors R L. Figure 2(b)shows the differential input version of the proposed νmos multiplier. The operation of this multiplier can be derived in the same way as for the single input version (Fig. 2(a)). The output voltage of the differential version is also given by Eq. (6). 2.3 Realization of Full-Scale Input Range and Detailed Design (b) Fig. 2 Proposed four-quadrant analog νmos multiplier. (a) Single input version and (b) differential input version. proposed multiplier should be designed with some margins in order to satisfy the design specification. In actual design, the linearity error of 0.77% and the 3dB bandwidth of 107 MHz with the power consumption of 9.56 µw could be achieved as mentioned in Sect. 4. In addition, Mehrvarz s multiplier requires a p-well process for avoiding the body effect, while the proposed multiplier is not influenced by the body effect because the source terminals of νmos transistors are connected directly to the ground. That is, the proposed multiplier is not restricted by the fabrication process. If we assume that νmos transistors M 1 M 4 are identical and operate in the saturation region, from Eq. (1), I ds1 I ds4 are given by The input range of the proposed multiplier is restricted by the saturation condition of M 1 M 4. For a νmos transistor to be in the saturation region, two conditions are required [11]: V fs >V T (7) V ds >V fs V T. (8) The supply voltage and input range in the design specification are 1 V and 1 V p-p, respectively. Therefore, we selected that V DD =1V,v x,max = v y,max = 0.5V, v x,min = v y,min = 0.5 V, so that V B1 =0.5V, as shown in Fig. 3. The input range of the proposed multiplier is restricted by the saturation condition of M 1 because M 1 has two input signals v x and v y. Substituting Eqs. (7)and (8)into M 1,wehave W 3 > V T V B2 (9) KR L < 2(V DD V f1 + V T ) (V f1 V T ) 2 +(V f2 V T ) 2, (10) where V f1 and V f2 are the floating-gate voltages of M 1

4 TANNO et al: A 1-V, 1-V P-P INPUT RANGE, FOUR-QUADRANT ANALOG MULTIPLIER 753 Fig. 3 Input signal and bias voltage. various mismatchs on the harmonic distortion. In this section, the second-order effects are estimated using the normalized harmonic distortion which is defined as HD n = HD n, HD 1 where HDn is the n-th order harmonic distortion and HD 1 is the basic component. 3.1 Mobility Degradation The mobility of electrons in the inversion layer is smaller than bulk mobility due to an increasing electric field. For a given temperature, this surface mobility depends primarily on the floating-gate field and may be modeled approximately by [11] and M 2, respectively and are represented by V f1 = W 1 (v x + v y +2V B1 )+W 3 V B2 and V f2 =2W 1 V B1 + W 3 V B2. In order to satisfy Eq. (9), V B2 should be assigned a large value. Accordingly, V B2 = V DD =1.0Vwas set. As the result, we have W 3 > 0.7 in the case of V T = 0.7 V (typical value of the MOS transistor parameters). In the actual design, we select W 3 = 0.75 with the process variation (for consideration of the maximum V T and to avoid operation in the para-saturation region) in mind. Next, we discuss the values of C 1 (= C 2 ) and C 3. We can derive the value of C 0 using MOS transistor parameters, and obtain C 0 = 270 ff. In this design, we selected C 1 = C 2 = 200 ff and C 3 =2pF by using W 3 = 0.75 and C0 = 270 ff. As the result, W 1 = W 2 = and W 3 =0.749 is obtained. On the other hand, Eq. (10)indicates the gain restriction of the proposed multiplier. For V DD = V B2 = 1V, V B1 =0.5V, v x,max = v y,max =0.5V dc (worst case), V T =0.7V, W 1 = W 2 =0.0749, W 3 =0.749, we have KR L < In the actual design, KR L = 27 is used. Next, we discuss the values of W/L and R L. In order to reduce the channel-length modulation effect, we used long-channel MOS transistors, such as those with L =10 µm. Using MOS transistor parameters and KR L = 27, we selected RL = 160 kω and W/L =42 µm/10 µm in order to satisfy v out =35mV p-p (design specification). Namely, the gain of the proposed multiplier is KW1 2R L = Therefore, v out =37.7 mv p-p can be obtained. 3. Second-Order Effects In this section, we discuss the influence of various effects of nonideality of νmos transistors. Practically, various second-order effects, such as channel-length modulation effect, body effect, mobility degradation effect and device mismatchs will degrade circuit performance. The body effect is neglected in the proposed multiplier, as mentioned previously. Furthermore, the influence by the channel-length modulation effect can be reduced by using long-channel devices. Therefore, we discuss the contribution of mobility degradation and µ 0 µ = 1+θ (V fs V T ), (11) where µ 0 represents the zero-field mobility of carriers and θ is the mobility degradation parameter. Substituting Eq. (11)into Eqs. (2) (5)and using Fourier expansion, it can be shown that dominant second- and third-harmonic distortion occur at the output of the proposed multiplier. Then, the normalized second and third harmonic distortion ( HD 2 and HD 3 )are given by HD 2 2θW 1 V α V AC = (2V α ) 2 +3(θW 1 V AC ) 2 (12) HD 3 (θw 1 V AC ) 2 = (2V α ) 2 +3(θW 1 V AC ) 2, (13) where V α =1+θ (2W 1 V B1 + W 3 V B2 V T )and one of the inputs, v y, is kept constant and the other input is v x = V AC sin ω 0 t. For W 1 =0.0749, W 3 =0.749, V B1 = 0.5V, V B2 = 1V, V T = 0.7V, V AC = 0.5V and θ =0.05 V 1, HD 2 and HD 3 are 60.6 db and 121 db, respectively. In Mehrvarz s multiplier, the HD 2 term does not appear and HD 3 is 55 db [9] for the same value of θ (=0.05). If HD 3 ( 121 db is enough small)can be ignored in the proposed multiplier, the harmonic distortion of the proposed multiplier is 5 db smaller than that of Mehrvarz s multiplier when a comparison is made between HD 3 of Mehrvarz s multiplier and HD 2 of the proposed multiplier. 3.2 Load Resistance Mismatch The load resistance mismatch also causes the harmonic distortion. To investigate the load resistance mismatch, R L0 (a mean value)can be considered as the reference resistance, so that each resistance shown in Fig. 2(a) has mismatch with respect to R L0. Then, we can define R Li = R L0 + i R L0 (for i =1, 2), (14) where R L1 and R L2 are the resistors on the left side and the right side shown in Fig. 2(a), respectively, and R L0 is their mean value.

5 754 IEICE TRANS. ELECTRON., VOL.E82 C, NO.5 MAY 1999 By substituting Eq. (14)into Eq. (6), it can be shown that the second harmonic distortion dominates and is given by HD 2 = W 1 V AC ( 2 1 ) 4[V β ( 1 2 )+W 1 v y (1 + 1 )],(15) where V β =2W 1 V B1 + W 3 V B2 V T. Furthermore, it was discovered that HD 3 = 0 in this analysis. For W 1 =0.0749, W 3 =0.749, V B1 =0.5V, V B2 =1V, V T =0.7V, V AC =0.5V, v y =0.5Vdc and 1 = 2 = 1%, HD 2 is 45.3 db. In Mehrvarz s multiplier, the load resistance mismatch contributes to the output offset voltage and the even-order harmonic distortion which is below 85 db [9]. This value is much smaller than that of the proposed multiplier. We should ensure adjacent placement and placement in close proximity of the matched load resistors in order to reduce the load resistance mismatch when the physical layout is designed. 3.3 Transconductance Parameter Mismatch The transconductance parameter mismatch is modeled as [9], [11] K i = K 0 + i K 0 (for i =1,, 4), (16) where K 1 K 4 are the transconductance parameters of M 1 M 4, respectively, and K 0 is the mean value. Substituting Eq. (16) into Eqs. (2) (5), the dominant second harmonic distortion term appears and is given by HD 2 = W 1 V AC ( 4 1 ) 4[V β ( 1 4 )+W 1 v y (1 + 1 )].(17) This equation is similar to Eq. (15). Furthermore, HD 2 depends on 1 and 4. For 1 = 4 = 1%, we have HD 2 = 45.3 db. It was discovered that HD 3 does not appear in the proposed multiplier. On the other hand, in Mehrvarz s multiplier, HD 2 caused by the transconductance parameter mismatch, is 51 db under the same condition [9]. The HD 2 value of Mehrvarz s multiplier is smaller than that of the proposed multiplier. However, we should pay attention to HD 3 in Mehrvarz s multiplier. The value is 58 db and cannot be ignored, while in the proposed multiplier, HD 3 does not appear as mentioned above. 3.4 Threshold Voltage Mismatch In the same manner, the threshold voltage mismatch can be modeled as [9], [11] V Ti = V T 0 + i V T 0 (for i =1,, 4), (18) where V T 1 V T 4 are the threshold voltage of M 1 M 4, respectively and V T 0 is the mean value. Substituting Eq. (18) into Eqs. (2) (5), we have HD 2 = HD 3 = HD 4 = 0. Namely, the threshold voltage mismatch does not influence the harmonic distortion, while the HD 2 of Mehrvarz s multiplier is 65 db [9]. Concerning the threshold voltage mismatch, we clarified the advantage of the proposed multiplier. 3.5 Capacitive Weight Mismatch The proposed multiplier consists of four νmos transistors with three input gates. Furthermore, the condition C 1 = C 2 is required, as mentioned above, therefore, the capacitive weight mismatch should be modeled as in Refs. [9], [11]: W 1,i = W 1 + 1,i W 1 (for i =1,, 4) W 2,j = W 1 + 2,j W 1 (for j =1,, 4) W 3,k = W 3 + 3,k W 3 (for k =1,, 4), (19) where W x,y implies W x of M y (x =1,, 3 and y = 1,, 4). Substituting Eq. (19) into Eqs. (2) (5), we have HD 2 = ( ) W 1 V AC 2 d 2 a 4{ a [ a W 1 V B1 + b W 1 (V B1 +v y )+ c W 3 V B2 V T ] d [( d + e )W 1 V B1 + f W 3 V B2 V T ]} where a = 1+ 1,1 b = 1+ 2,1 c = 1+ 3,1 d = 1+ 1,4 e = 1+ 2,4 f = 1+ 3,4. (20) (21) From Eqs. (20)and (21), it is found that HD 2 strongly depends on 1,1 and 1,4. Figure 4 shows the relation between HD 2 and the capacitive weight mismatch under the condition that W 1 =0.0749, W 3 =0.749, V B1 =0.5V, V B2 =1V,V T =0.7V, V AC =0.5V, v y =0.5V dc, 1,1 ( 1,4 )is varied from 0% to 5% and the other deviations are set to 0%. From Fig. 4, we can see that the dependence of the 1,1 is larger than that of 1,4 and HD 2 = 70 db at 1,1 = 3%. In Mehrvarz s multiplier, the capacitive weight mismatch contributes to the values of HD 2 and HD 3 which are 60 db and 70 db, respectively. When a comparison is made between HD 2 of Mehrvarz s multiplier (Fig. 4 in Ref. [9])and the proposed multiplier (Fig. 4), HD 2 of the proposed multiplier is clearly smaller than that of Mehrvarz s multiplier. From the above theoretical analyses, we should ensure adjacent placement and placement in close proximity of the matched νmos transistors and load resistors in order to reduce device mismatchs when the physical layout is designed.

6 TANNO et al: A 1-V, 1-V P-P INPUT RANGE, FOUR-QUADRANT ANALOG MULTIPLIER 755 Fig. 4 Relation between HD 2 and the capacitive weight mismatch under the condition that W 1 = , W 3 = 0.749, V B1 =0.5V, V B2 =1V,V T =0.7V, V AC =0.5V, v y =0.5V dc, 1,1 ( 1,4 ) is varied from 0% to 5% and the other deviations are set to 0%. Fig. 6 Worst-case linearityerror: input v y = 0.5 V dc, for v out /v x = 1 and input v x consists of a 250 Hz ramp swing between 0.5 V and +0.5V. Fig. 5 Simulated dc transfer characteristics. Fig. 7 Relation between total harmonic distortion (THD) and v x under the condition that v y =0.5V dc. 4. Simulation Results The proposed νmos multiplier is estimated using HSPICE simulations with the standard 2.0 µm CMOS process with a double-poly layer. As mentioned previously, W/L, C 1 (= C 2 )and C 3 of νmos transistors are 42 µm/10 µm, 200 ff and 2 pf, respectively, and R L is 160 kω in order to satisfy the design specifications of V DD =1V,v x = v y =1V p-p and v out =35mV p-p. The bias voltages V B1 and V B2 are 0.5 V and 1 V, respectively. Figure 5 shows the dc transfer characteristics of the proposed multiplier under the condition that v x = 0.5V +0.5 V and v y is varied from 0.5 V to +0.5 V in steps of 0.1 V. From Fig. 5, we can see that the mul- tiplier has high linearity and v out =37mV p-p. Figure 6 shows the worst-case linearity error, where v y =0.5V dc, and the output differential amplifier gain is adjusted to yield v out /v x = 1. The input signal v x consists of a 250 Hz ramp swing between 0.5 V and +0.5 V. Because a good linearity margin was left for the W/L of the proposed multiplier in order to satisfy the design specification (as mentioned in Sect. 2.2), we could prevent linearity error below 1%. From HSPICE simulations, the worst-case linearity error was 0.77% with the full-scale input conditions. Figure 7 shows the relation between THD and v x under the condition that v y = 0.5 V dc, v x is varied from 0.2V p-p to 1 V p-p and the frequency (f)of v x is varied to 1 khz, 10 khz, 100 khz and 1 MHz. The simulated THD was 0.62% under v x =1V p-p and f = 1 MHz. From HSPICE

7 756 IEICE TRANS. ELECTRON., VOL.E82 C, NO.5 MAY 1999 Fig. 8 Product of a 50 khz sine wave and a 1 khz sine wave. Fig. 9 Physical layout of the proposed νmos multiplier. simulations, it was discovered that mobility degradation is the principal cause of the deterioration of THD. According to the HSPICE simulation results, the value of THD caused by the mobility degradation was approximately 0.23%. Besides, the theoretical value of THD derived in Sect. 3.1 is nearly equal to THD of the HSPICE simulation results and is approximately 0.19% (from Eq. (12)), while the channel-length modulation coefficient (λ)value used in HSPICE simulation is relatively large (λ = V 1 ). However, THD deterioration caused by the channel-length modulation effect was small and was less than 0.1%, because longchannel devices were used in the proposed multiplier and the changes in V ds of M 1 M 4 were small. Figure 8 shows the multiplier as a modulator, where a 50 khz sine wave is modulated by a 1 khz sine wave. The 3 db bandwidth and maximum power consumption were 107 MHz and 9.56 µw, respectively. In the same way as for the linearity error, a large bandwidth could be achieved when the W/L value was chosen in consideration of the required bandwidth. The power consumption satisfied the design specification and was a very small value. Figure 9 shows the physical layout of the proposed multiplier. All νmos transistors are located in close proximity in order to reduce the mismatchs. The active area of the proposed multiplier is 210 µm 140 µm. 5. Conclusion In this paper, a novel four-quadrant multiplier using νmos transistors has been proposed. The noteworthy features of the proposed multiplier are low-voltage operation and full-scale input range. The operation conditions for full-scale input range have been derived and the νmos multiplier operable at 1 V with a full-scale input range has been designed based on these conditions. Furthermore, the second-order ef- fects, such as mobility degradation, load resistance mismatch, transconductance parameter mismatch, threshold voltage mismatch and capacitive weight mismatch, have been analyzed in detail. The simulated linearity error and THD were 0.77% and 0.62% (at a input signal of 1 MHz), respectively, under full-scale input. A 3 db bandwidth and maximum power consumption were 107 MHz and 9.56 µw, respectively. Finally, the physical layout of the proposed multiplier was designed. The active area was 210 µm 140 µm. The propose multiplier has the potential of becoming an important building block in fuzzy controllers. Acknowledgments A part of this work was supported by the grant-in-aid for Scientific Research of the Ministry of Education, Science, Sports and Culture of Japan under Grant: References [1] K. Tanno, O. Ishizuka, and Z. Tang, Design and analysis of the current-mode CMOS analog defuzzification circuit for fuzzycontrollers, IEICE Trans., vol.j79-a, no.7, pp , July1996. [2] M. Sugeno, Fuzzycontrol, IndustryDaily, Ltd., Tokyo, Japan, [3] B. Gilbert, A precise four-quadrant multiplier with subnanosecond response, IEEE J. Solid-State Circuits, vol.sc-3, no.4, pp , Dec [4] B. Gilbert, A high-performance monolithic multiplier using active feedback, IEEE J. Solid-State Circuits, vol.sc- 9, no.6, pp , Dec [5] D.C. Soo and R.G. Meyer, A four-quadrant NMOS analog multiplier, IEEE J. Solid-State Circuits, vol.sc-17, no.6, pp , Dec [6] S.C. Qin and R.L. Geiger, A ±5 V CMOS analog multiplier, IEEE J. Solid-State Circuits, vol.sc-22, no.6, pp , Dec [7] C.W. Kim and S.B. Park, New four-quadrant CMOS analogue multiplier, Electron. Lett., vol.23, no.24, pp.1268

8 TANNO et al: A 1-V, 1-V P-P INPUT RANGE, FOUR-QUADRANT ANALOG MULTIPLIER , Nov [8] K. Kimura, An MOS four-quadrant analog multiplier based on the multitail technique using a quadritail cell as a multiplier core, IEEE Trans. Circuits & Syst. I, vol.42, no.8, pp , Aug [9] H.R. Mehrvarz and C.Y. Kwok, A novel multi-input floating-gate MOS four-quadrant analog multiplier, IEEE J. Solid-State Circuits, vol.31, no.8, pp , Aug [10] T. Shibata and T. Ohmi, A functional MOS transistor featuring gate-level weighted sum and threshold operation, IEEE Trans. Electron Devices, vol.39, no.6, pp , June [11] K. Tanno, J. Shen, O. Ishizuka, and Z. Tang, Neuron-MOS V T cancellation circuit and its application to a low-power and high-swing cascode current mirror, IEICE Trans. Fundamentals, vol.e81 A, no.1, pp , Jan Zheng Tang was born in Jiangsu, China in He received his B.S degree from Zhejiang University, Zhejiang, China in 1982 and M.S. and Ph.D. degrees from Tsinghua University, Beijing, China in 1984 and 1988, respectively. From 1988 to 1989, he was an instructor at the Institute of Microelectronics, Tsinghua University. In 1989, he joined Miyazaki University, Miyazaki, Japan, where he is currentlyan Associate Professor in the Department of Electrical & Electronic Engineering. His current research interests include neural networks, multiple-valued logic, fuzzycontrol and analog-integrated circuit design. Dr. Tang is a member of IEEE. Koichi Tanno was born in Miyazaki, Japan, on April 22, He received his B.E. and M.E. degrees from the Facultyof Engineering, Miyazaki Universityin 1990 and 1992, respectively. Between 1992 and 1993, he was with the Microelectronics Products Development Laboratory, Hitachi, Ltd., Yokohama, Japan. He was engaged in research on low-power supplyvoltage continuoustime filters. Since 1994, he has been with the Facultyof Engineering, Miyazaki Universityas a research associate in the Department of Electrical & Electronic Engineering. His main research interests include analog integrated circuit design, multiple-valued logic circuit design, fuzzycontrol, and neural networks. Mr. Tanno is a member of IEEE. Okihiko Ishizuka was born in Kumamoto, Japan on September 7, He received his B.E. degree in 1964 from Kagoshima University, and M.E. and Ph.D. degrees from Kyushu University in 1966 and 1978, respectively. He is a Professor of Electrical & Electronic Engineering at Miyazaki University, Miyazaki, Japan. His research interests are network synthesis, circuit analysis on multiplevalued logic, threshold logic and fuzzy logic. Dr. Ishizuka is a member of IEEE and the Executive Subcommittee of the IEEE Computer SocietyTechnical Committee on Multiple-Valued Logic.