VLSI Design Course File

Transcription

1 VLSI Design Course File

2 Course file contents 1. Cover Page 2. Syllabus copy 3. Vision of the Department 4. Mission of the Department 5. PEOs and POs 6. Course objectives and outcomes 7. Brief Notes 8. Perquisites, If any 9. Instructional Learning Outcomes 10. Course mapping with PEOs and POs 11. Class Time Table 12. Individual Time Table 13. Lecture Schedule with Methodology being used 14. Detailed notes 15. Additional topics 16. University previous Question papers 17. Question Bank 18. Assignment topics 19. Unit wise bits 20. Tutorial class sheets 21. Known gaps 22. Discussion Topics 23. References, Journals, websites and E-links 24. Quality Control Sheets a. Course end survey b. Teaching Evaluation 25. Student List 26. Group-Wise students list for discussion topics

3 GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF Electrical and Electronics Engineering (Name of the Subject / Lab Course) :VLSI Design (JNTU CODE -- A60432) Programme : UG Branch: ECE Version No : 01 Year: 3 rd Updated on :26/11/2015 Semester: II, No.of pages :95 Classification status (Unrestricted / Restricted ) Distribution List : Prepared by : 1) Name : G. Sree Lakshmi 1) Name :K.V.S.Nagaraju 2) Sign : 2) Sign : 3) Design : Assoc.professor 3) Design :Assistant Professor 4) Date : 26/11/2015 4) Date : 26/11/2015 Verified by : 1) Name : * For Q.C Only. 2) Sign : 1) Name : 3) Design : 2) Sign : 4) Date : 3) Design : 4) Date : Approved by : (HOD ) 1) Name : 2) Sign : 3) Date :

4 2. JNTU Syllabus: UNIT I UNIT II UNIT III UNIT IV UNIT V INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS. BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ; Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters. VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 _m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling. GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance Units, Calculations Delays, Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers DATA PATH SUBSYSTEMS: Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters. Array Subsystems: SRAM, DRAM, ROM, Serial Access Memories, Semiconductor Integrated Circuit Design: PLAs,FPGAs, CPLDs, Standard cells, Programmable Array Logic Design Approach, Parameters influencing low power design CMOS TESTING : CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip level Test Techniques.

5 Books / Material Text Books Text-1. Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, PHI,2005 Edition. Text-2. Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, Suggested / Reference Books Ref-1. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, Ref-2. VLSI Technology S.M. SZE, 2nd Edition, TMH, Ref-3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, Web Sites a. b. c. d. * For the topics Internal & external Circlips, Gaskets and seals (stationary and rotary)

6 3. Vision of the Department To impart quality technical education in Electronics and Communication Engineering emphasizing analysis, design/synthesis and evaluation of hardware/embedded software using various Electronic Design Automation (EDA) tools with accent on creativity, innovation and research thereby producing competent engineers who can meet global challenges with societal commitment. 4. Mission of the Department i. To impart quality education in fundamentals of basic sciences, mathematics, electronics and communication engineering through innovative teaching-learning processes. ii. To facilitate Graduates define, design, and solve engineering problems in the field of Electronics and Communication Engineering using various Electronic Design Automation (EDA) tools. iii. To encourage research culture among faculty and students thereby facilitating them to be creative and innovative through constant interaction with R & D organizations and Industry. iv. To inculcate teamwork, imbibe leadership qualities, professional ethics and social responsibilities in students and faculty. 5. Program Educational Objectives of B. Tech (ECE) Program : I. To prepare students with excellent comprehension of basic sciences, mathematics and engineering subjects facilitating them to gain employment or pursue postgraduate studies with an appreciation for lifelong learning. II. To train students with problem solving capabilities such as analysis and design with adequate practical skills wherein they demonstrate creativity and innovation that would enable them to develop state of the art equipment and technologies of multidisciplinary nature for societal development. III. To inculcate positive attitude, professional ethics, effective communication and interpersonal skills which would facilitate them to succeed in the chosen

7 profession exhibiting creativity and innovation through research and development both as team member and as well as leader. 5. Program Outcomes of B.Tech ECE Program: 1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve complex engineering problems of Electronics and Communication Engineering systems. 2. An ability to model, simulate and design Electronics and Communication Engineering systems, conduct experiments, as well as analyze and interpret data and prepare a report with conclusions. 3. An ability to design an Electronics and Communication Engineering system, component, or process to meet desired needs within the realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability and sustainability. 4. An ability to function on multidisciplinary teams involving interpersonal skills. 5. An ability to identify, formulate and solve engineering problems of multidisciplinary nature. 6. An understanding of professional and ethical responsibilities involved in the practice of Electronics and Communication Engineering profession. 7. An ability to communicate effectively with a range of audience on complex engineering problems of multidisciplinary nature both in oral and written form. 8. The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental and societal context. 9. A recognition of the need for, and an ability to engage in life-long learning and acquire the capability for the same. 10. A knowledge of contemporary issues involved in the practice of Electronics and Communication Engineering profession 11. An ability to use the techniques, skills and modern engineering tools necessary for engineering practice.

8 12. An ability to use modern Electronic Design Automation (EDA) tools, software and electronic equipment to analyze, synthesize and evaluate Electronics and Communication Engineering systems for multidisciplinary tasks. 6. Course Objective and Outcomes Course Objectives: The students should have ability to: To understand the steps involved in IC fabrication. Ability to demonstrate the fundamentals of IC Technology such as various MOS fabrication technologies. To get the knowledge about basic electrical properties of MOS &BIOS circuits. To understand VLSI circuit design processes representations of stick diagram &layout diagram. To develop the gate level design &delays. To know different combinational & sequential circuits to design the subsystems like ALUs, shifters, adders etc. To understand the importance of CPLDs and FPGAs for implementing the variety logic functions. Course outcomes: CO 1: Demonstrate the Fabrication of IC using cadence tools. CO2: Calculate compute electrical properties of MOS circuits. CO3: Design various gates, adders, Multipliers and Memories using stick diagrams, layouts. CO4: Apply design rules to get Layout of IC. CO5: Demonstrate semiconductor IC design such as PLA s, PAL, FPGA, CPLDs. CO6: Design various forms of memories. CO7: Implement Subsystems with CMOS Technology. CO8: Design a Logic Circuit with MOS Transistors. CO9: Demonstrate VHDL synthesis, simulation, design captures tools, design verification tools. CO10: Demonstrate differential strategies for testing of IC s and CMOS testing.

9 7. Brief note on Important Topics In this course, we will study the fundamental structures of VLSI Systems at the lowest levels of system abstraction, namely those associated with the direct application of VLSI devices to particular problems of interest. At its most basic level, VLSI design is concerned with the set of principles governing MOS (metal oxide semiconductor) devices and their behaviours. We start by looking at the CMOS transistors (n-channel and p-channel) and the ways in which we can use them to create the most basic structure the digital switch. We can proceed to build a range of VLSI structures from this switch, including NAND/NOR gates, Multiplexers, Latches and Registers. Continuing in a bottom-up fashion, we can examine the structure of more complex VLSI design components (those at Digital Logic and Register Transfer levels of abstraction) using these primitives. While learning how to construct fundamental VLSI systems structures from primitive circuit structures, we also will learn about the processes associated with fabricating CMOS devices. Using CMOS as our technology, we examine the circuit level design rules associated with circuit geometries and their layout according to a set of process technology-specific design rules. We also look at factors affecting design: capacitance, clocking, delay and power. These characteristics of a circuit technology have a profound effect on the circuit's behaviour as we move to ever smaller geometries. Circuit feature sizes and device densities. Finally, we will develop a complete picture of the VLSI systems design flow, starting at the Systems level, proceeding through the Register Transfer Level, to the Digital Logic, Circuit and the Device Geometry levels therefore having a complete picture of the VLSI systems architecture and engineering design process and associated design methods. We will use VHDL as the medium for describing our design artefacts, and will likely use gate-level simulation, along with circuit layout tools, as a means for exploring the knowledge in this domain. Course Outline: The course outline is as follows: 1. Introduction to CMOS Design. Rabaey et al., Chapter CMOS Device Fabrication Processes. Rabaey et al., Chapter CMOS Transistor Device Models. Rabaey et al., Chapter CMOS Interconnect Wire Models. Rabaey et al., Chapter CMOS Inverter Model. Rabaey et al., Chapter Combinational and Sequential Design. Rabaey et al., Chapters 6 & 7 (selected

10 sections). 7. Projects. 8. Prerequisites, If Any MOSFET concepts, Basics of STLD 9. Instructional Learning Outcomes UNIT I: Introduction of IC Technology Students should be able to: Know about IC Technology. Get the idea on fabricating various MOS transistor on silicon wafer. Understand the difference between CMOS and BIPOLAR Technologies. Get the knowledge on advantage of BICOS Technology. Understand the basic electrical properties of MOS and BICMOS circuits. Get the knowledge about Ids-Vds relationships. Know the MOS transistor threshold Voltage, gm, gds, figure of merit. Know the NMOS Inverter, Various pull ups. Understand the CMOS Inverter analysis and design, Bi-CMOS Inverters. UNIT II: VLSI circuit design processes After the completion of the unit the students should be able to: Know the VLSI Design Flow. Understand the MOS layers. Draw the stick diagrams and layouts for NMOS and CMOS inverters and gates. Get the knowledge about 2 _m CMOS Design rules for wires, Contacts. Know the Scaling of MOS circuits. UNIT III: Gate level design After the completion of the unit the student should be able to: Develop the Logic Gates and Other complex gates. Know about Sheet Resistance RS and its concept to MOS. Get the concept of driving large Capacitive Loads. Know the Wiring Capacitances. Understand the concept of Fan-in and fan-out.

11 UNIT IV: Data Path Subsystems and Array Subsystems After the completion of the unit the student should be able to: Know the knowledge of Shifters, Adders. Develop the ALUs, Multipliers. Get the knowledge of Parity generators, Comparators. Design the various counters. Get the knowledge about Zero/One Detectors. Get the knowledge about memory architecture. Understand the concept of static RAM. Get the knowledge of DRAM. Know the knowledge of Serial access memory. UNIT V: Programable Logic Devices and CMOS Testing After the completion of the unit the student should be able to: Get the knowledge about PLA and PAL. Understand the concept of FPGA and its applications. Get the knowledge about CPLD and its applications. Know the knowledge about Standard cells. Get the knowledge of Programmable Array Logic Design Approach. Understand the needs of testing in VLSI design. How to apply test principles. Know the Chip level Test Techniques. 10. Mapping of Course outcomes to Program Outcomes: 1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve complex engineering problems of Electronics and Communication Engineering systems. 2. An ability to model, simulate and design Electronics and Communication Engineering systems, conduct experiments, as well as analyze and interpret data and prepare a report with conclusions. 3. An ability to design an Electronics and Communication Engineering system, component, or process to meet desired needs within the realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability and sustainability. 4. An ability to function on multidisciplinary teams involving interpersonal skills.

12 5. An ability to identify, formulate and solve engineering problems of multidisciplinary nature. 6. An understanding of professional and ethical responsibilities involved in the practice of Electronics and Communication Engineering profession. 7. An ability to communicate effectively with a range of audience on complex engineering problems of multidisciplinary nature both in oral and written form. 8. The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental and societal context. 9. A recognition of the need for, and an ability to engage in life-long learning and acquire the capability for the same. 10. A knowledge of contemporary issues involved in the practice of Electronics and Communication Engineering profession 11. An ability to use the techniques, skills and modern engineering tools necessary for engineering practice. 12. An ability to use modern Electronic Design Automation (EDA) tools,. software and electronic equipment to analyze, synthesize and evaluate Electronics and Communication Engineering systems for multidisciplinary tasks. S.No. Course Outcome POs 1 Demonstrate the Fabrication of IC using PO2, PO3,PO8,PO11 cadence tools. 2 Calculate compute electrical properties of MOS circuits. 3 Design various gates, adders, Multipliers and Memories using stick diagrams, layouts. PO1,PO2 PO4 4 Apply design rules to get Layout of IC. PO5 5 Demonstrate semiconductor IC design such as PO13

13 PLA s, PAL, FPGA, CPLDs. 6 Design various forms of memories. PO3,PO4,PO12 7 Implement Subsystems with CMOS PO2,PO3,PO6 Technology. 8 Design a Logic Circuit with MOS Transistors. PO3,PO6,PO8 9 Demonstrate VHDL synthesis, simulation, PO11 design captures tools, design verification tools. 10 Demonstrate differential strategies for testing of IC s and CMOS testing. PO3 11. Class Time Table: 12. Individual Time Table 13.Lecture Shedule with methodology being used GEETHANJALI COLLEGE OF ENGINEERING & TECHNOLOGY CHEERYAL (V), KEESARA (M), RR District. Department of Computer science and engineering Year and Semester to Whom Subject is Offered: IV B.TECH-I Semester Name of the Subject: VLSI DESIGN Name of the Faculty: S.Vasu Krishna Designation: Assoc. prof Department: ECE

14 Micro Plan:- FOR ECE - 4 rd Year 13.1 Micro Plan:- Subject: VLSI Design Class: IV ECE-A Name of the Faculty: G Sreelakshmi Lecture Shedule S. no Unit Regular / Teaching aids used DATE Topics to be covered No Additional LCD/OHP/BB 1 1 Introduction to VLSI Regular BB 2 Introduction to IC Technology Regular BB 3 MOS Transistor, Enhancement and Depletion Regular BB/OHP Mode 4 MOS Fabrication Process Regular BB/OHP 5 Fabrication Process :NMOS,PMOS Regular BB/OHP 6 Fabrication Process :CMOS Regular BB/OHP 7 Berkeley n-well Process,Twin Tub Process Regular BB/OHP 8 Fabrication Process :BICMOS Regular BB/OHP 9 BICMOS Regular BB/OHP Latch up susceptibility Missing BB 10 Oxidation, Lithography, Diffusion Regular BB 11 Ion implantation, Metallization, Encapsulation Regular BB 12 Probe testing, Integrated Resistors and Regular BB Capacitors 13 CMOS Nanotecchnology Regular BB 14 Tutorial class on unit 1 -revision Regular BB 15 2 BASIC ELECTRICAL PROPERTIES : Basic Regular BB Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships 16 MOS transistor threshold Voltage Regular BB 17 gm, gds, figure of merit?o; Pass transistor, Regular BB NMOS Inverter 18 NMOS Inverter Regular BB 19 Various pull ups Regular BB 20 CMOS Inverter analysis and design Regular BB 21 Bi-CMOS Inverters Regular BB Remarks 22 Tutorial class on unit 2 -revision Regular 23 3 VLSI CIRCUIT DESIGN PROCESSES : Regular BB VLSI Design Flow 24 MOS Layers, Stick Diagrams Regular BB 25 Stick Diagrams Regular BB 26 Design Rules and Layout Regular BB 27 2 nm CMOS Design rules for wires Regular BB 28 Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates Regular BB

15 29 Scaling of MOS circuits Regular BB 30 Tutorial class on unit3 -revision Regular BB 31 4 GATE LEVEL DESIGN : Logic Gates and Other complex gates Regular BB 32 Switch logic, Alternate gate circuits Regular BB Gallium Arsenide Devices Additional BB 33 Time Delays Regular BB 34 Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers Regular BB 35 Tutorial class on unit4 -revision Regular BB 36 5 SUBSYSTEM DESIGN : Subsystem Design, Regular BB Shifters 37 Adders, ALUs Regular BB 38 Multipliers, Parity generators Regular BB 39 Comparators, Zero/One Detectors, Counters Regular BB 40 Tutorial class on unit5 -revision Regular BB 41 6 Array Subsystems :SRAM,DRAM Regular BB 42 ROM, Serial Access Memories Regular BB Dynamic Register Element Additional BB 43 Content Addressable Memory Regular BB 44 Tutorial class on unit6 -revision Regular BB 45 7 SEMICONDUCTOR INTEGRATED Regular BB CIRCUIT DESIGN : PLAs 46 FPGAs Regular BB 47 CPLDs Regular BB 48 Standard Cells, Programmable Array Logic Regular BB System Partioning Missing Missing BB 49 Design Approach Regular BB 50 Parameters influencing low power design Regular BB 51 Tutorial class on unit 7 -revision Regular 52 8 CMOS TESTING : CMOS Testing Regular BB 53 Need for testing Regular BB 54 Test Principles Regular BB 55 Design Strategies for test Regular BB 56 Chip level Test Techniques Regular BB/OHP 57 System-level Test Techniques Regular BB/OHP 58 Layout Design for improved Testability. Regular BB/OHP and Tutorial class on unit8 -revision 59 Revision of previous papers Regular BB/OHP 60 Revision of previous papers Regular BB/OHP 61 Revision of previous papers Regular BB/OHP 62 Revision of previous papers Regular BB/OHP Subject: VLSI Design Class: IV ECE-B Name of the Faculty: S Vasu Krishna

16 Lecture Shedule S. no Unit Regular / Teaching aids used DATE Topics to be covered No Additional LCD/OHP/BB 1 1 Introduction to VLSI Regular BB 2 Introduction to IC Technology Regular BB 3 MOS Transistor, Enhancement and Depletion Regular BB/OHP Mode 4 MOS Fabrication Process Regular BB/OHP 5 Fabrication Process :NMOS,PMOS Regular BB/OHP 6 Fabrication Process :CMOS Regular BB/OHP 7 Berkeley n-well Process,Twin Tub Process Regular BB/OHP 8 Fabrication Process :BICMOS Regular BB/OHP 9 BICMOS Regular BB/OHP Latch up susceptibility Missing BB 10 Oxidation, Lithography, Diffusion Regular BB 11 Ion implantation, Metallization, Encapsulation Regular BB 12 Probe testing, Integrated Resistors and Regular BB Capacitors 13 CMOS Nanotecchnology Regular BB 14 Tutorial class on unit 1 -revision Regular BB 15 2 BASIC ELECTRICAL PROPERTIES : Basic Regular BB Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships 16 MOS transistor threshold Voltage Regular BB 17 gm, gds, figure of merit?o; Pass transistor, Regular BB NMOS Inverter 18 NMOS Inverter Regular BB 19 Various pull ups Regular BB 20 CMOS Inverter analysis and design Regular BB 21 Bi-CMOS Inverters Regular BB 22 Tutorial class on unit 2 -revision Regular 23 3 VLSI CIRCUIT DESIGN PROCESSES : Regular BB VLSI Design Flow 24 MOS Layers, Stick Diagrams Regular BB 25 Stick Diagrams Regular BB 26 Design Rules and Layout Regular BB 27 2 nm CMOS Design rules for wires Regular BB 28 Contacts and Transistors Layout Diagrams for Regular BB NMOS and CMOS Inverters and Gates 29 Scaling of MOS circuits Regular BB 30 Tutorial class on unit3 -revision Regular BB Remarks 31 4 GATE LEVEL DESIGN : Logic Gates and Other complex gates Regular BB 32 Switch logic, Alternate gate circuits Regular BB Gallium Arsenide Devices Additional BB 33 Time Delays Regular BB 34 Driving large Capacitive Loads, Wiring Regular BB

17 Capacitances, Fan-in and fan-out, Choice of layers 35 Tutorial class on unit4 -revision Regular BB 36 5 SUBSYSTEM DESIGN : Subsystem Design, Regular BB Shifters 37 Adders, ALUs Regular BB 38 Multipliers, Parity generators Regular BB 39 Comparators, Zero/One Detectors, Counters Regular BB 40 Tutorial class on unit5 -revision Regular BB 41 6 Array Subsystems :SRAM,DRAM Regular BB 42 ROM, Serial Access Memories Regular BB Dynamic Register Element Additional BB 43 Content Addressable Memory Regular BB 44 Tutorial class on unit6 -revision Regular BB 45 7 SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN : PLAs Regular 46 FPGAs Regular BB 47 CPLDs Regular BB 48 Standard Cells, Programmable Array Logic Regular BB System Partioning Missing Missing BB 49 Design Approach Regular BB 50 Parameters influencing low power design Regular BB 51 Tutorial class on unit 7 -revision Regular 52 8 CMOS TESTING : CMOS Testing Regular BB 53 Need for testing Regular BB 54 Test Principles Regular BB 55 Design Strategies for test Regular BB 56 Chip level Test Techniques Regular BB/OHP 57 System-level Test Techniques Regular BB/OHP 58 Layout Design for improved Testability. Regular BB/OHP and Tutorial class on unit8 -revision 59 Revision of previous papers Regular BB/OHP 60 Revision of previous papers Regular BB/OHP 61 Revision of previous papers Regular BB/OHP 62 Revision of previous papers Regular BB/OHP BB Subject: VLSI Design Class: IV ECE-C Name of the Faculty: M Krishna Chaitanya Lecture Shedule S. no Unit No DATE Topics to be covered Regular / Additional Teaching aids used LCD/OHP/BB Remarks

18 1 1 Introduction to VLSI Regular BB 2 Introduction to IC Technology Regular BB 3 MOS Transistor, Enhancement and Depletion Regular BB/OHP Mode 4 MOS Fabrication Process Regular BB/OHP 5 Fabrication Process :NMOS,PMOS Regular BB/OHP 6 Fabrication Process :CMOS Regular BB/OHP 7 Berkeley n-well Process,Twin Tub Process Regular BB/OHP 8 Fabrication Process :BICMOS Regular BB/OHP 9 BICMOS Regular BB/OHP Latch up susceptibility Missing BB 10 Oxidation, Lithography, Diffusion Regular BB 11 Ion implantation, Metallization, Encapsulation Regular BB 12 Probe testing, Integrated Resistors and Regular BB Capacitors 13 CMOS Nanotecchnology Regular BB 14 Tutorial class on unit 1 -revision Regular BB 15 2 BASIC ELECTRICAL PROPERTIES : Basic Regular BB Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships 16 MOS transistor threshold Voltage Regular BB 17 gm, gds, figure of merit?o; Pass transistor, Regular BB NMOS Inverter 18 NMOS Inverter Regular BB 19 Various pull ups Regular BB 20 CMOS Inverter analysis and design Regular BB 21 Bi-CMOS Inverters Regular BB 22 Tutorial class on unit 2 -revision Regular 23 3 VLSI CIRCUIT DESIGN PROCESSES : Regular BB VLSI Design Flow 24 MOS Layers, Stick Diagrams Regular BB 25 Stick Diagrams Regular BB 26 Design Rules and Layout Regular BB 27 2 nm CMOS Design rules for wires Regular BB 28 Contacts and Transistors Layout Diagrams for Regular BB NMOS and CMOS Inverters and Gates 29 Scaling of MOS circuits Regular BB 30 Tutorial class on unit3 -revision Regular BB 31 4 GATE LEVEL DESIGN : Logic Gates and Other complex gates Regular BB 32 Switch logic, Alternate gate circuits Regular BB Gallium Arsenide Devices Additional BB 33 Time Delays Regular BB 34 Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers Regular BB 35 Tutorial class on unit4 -revision Regular BB 36 5 SUBSYSTEM DESIGN : Subsystem Design, Regular BB Shifters 37 Adders, ALUs Regular BB

19 38 Multipliers, Parity generators Regular BB 39 Comparators, Zero/One Detectors, Counters Regular BB 40 Tutorial class on unit5 -revision Regular BB 41 6 Array Subsystems :SRAM,DRAM Regular BB 42 ROM, Serial Access Memories Regular BB Dynamic Register Element Additional BB 43 Content Addressable Memory Regular BB 44 Tutorial class on unit6 -revision Regular BB 45 7 SEMICONDUCTOR INTEGRATED Regular BB CIRCUIT DESIGN : PLAs 46 FPGAs Regular BB 47 CPLDs Regular BB 48 Standard Cells, Programmable Array Logic Regular BB System Partioning Missing Missing BB 49 Design Approach Regular BB 50 Parameters influencing low power design Regular BB 51 Tutorial class on unit 7 -revision Regular 52 8 CMOS TESTING : CMOS Testing Regular BB 53 Need for testing Regular BB 54 Test Principles Regular BB 55 Design Strategies for test Regular BB 56 Chip level Test Techniques Regular BB/OHP 57 System-level Test Techniques Regular BB/OHP 58 Layout Design for improved Testability. Regular BB/OHP and Tutorial class on unit8 -revision 59 Revision of previous papers Regular BB/OHP 60 Revision of previous papers Regular BB/OHP 61 Revision of previous papers Regular BB/OHP 62 Revision of previous papers Regular BB/OHP Subject Contents Synopsis page for each period (62 pages) Detailed Lecture notes containing: 1. ppts 2. ohp slides 3. subjective type questions(approximately 5 t0 8 in no) 4.objective type questions(approximately 20 to 30 in no) 5.Any simulations Course Review (By the concerned Faculty): (I)Aims (II) Sample check (III) End of the course report by the concerned faculty

20 2 GUIDELINES: Distribution of periods : No. of classes required to cover JNTU syllabus : 40 No. of classes required to cover Additional topics : 4 No. of classes required to cover Assignment tests (for every 2 units 1 test) : 4 No. of classes required to cover tutorials : 8 No. of classes required to cover Mid tests : No of classes required to solve University : 4 Question papers Total periods Detailed notes UNIT 1 INTRODUCTION Synthetic detail of an integrated circuit through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish), and substrate (green). Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid-20thcentury technology advancements in semiconductor device fabrication. The integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuit's mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography rather than being constructed one transistor at a time. Furthermore, much less material is used to construct a packaged IC die than a discrete circuit. Performance is high since the components switch quickly and consume little power (compared to their discrete counterparts) because the components are small and positioned close together. As of 2006, chip areas range from a few square millimeters to around 350 mm 2, with up to 1 million transistors per mm IC Fabrication Process: An integrated circuit consists of a single crystal chip of silicon. Containing both active and passive elements, and their interconnection.

21 The basic structure of an IC consists of four layers of materials, such that: 1.Substrate 2.Epitaxialgrowth 3.Diffusion 4. Metallization Substrate: The p-type silicon bottom layer (6 mils thick) and serves where the Integrated circuit is to be built known as Substrate. Epitaxial growth: The second n-type layer (25µm=1mil) where all active and passive component are built, which is grown as a single crystal extension is called Epitaxial growth. Diffusion: The third layer of IC fabrication is Diffusion process. Active and passive component are made by diffusing p-type and n-type impurities. The selective diffusion of impurities is accomplished by using SiO2 as a barrier. Metallization: Finally a fourth material (aluminum) Layer is added to supply the necessary interconnection between components. It provided contact among the components Al is used for metallization. Diode Fabrication:

22 Transistor Fabrication: CMOS: Fabrication: MOSFET Fabrication:

23 Monolithic IC: \ Fabrication process:

24 IC characteristics / Elimination: 1. Typical value of Resistance 10Ω < R < 30 kω & Capacitance <30pf. 2. Poor tolerance typical value is 10% only. 3. High thermal co-efficient & voltage resistive. 4. No transfer & inductor can be fabricated. 5. Higher cost for small scale production. BASIC ELECTRICAL PROPERTIES

25 The MOS transistor evolves from the use of a voltage on the gate to induce a charge in the channel between source and drain, which may then be caused to move from source to drain under the influence of an electric field created by voltage Vds applied between drain and source. Since the charge induced is dependent on the gate to source voltage then Ids is dependent on both Vgs and Vds. polysilicon gate W t ox n+ L n+ p-type body SiO2 gate oxide (good insulator, ox = 3.9) MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Qchannel = CV C = Cg = eoxwl/tox = CoxWL V = V gc V t = (V gs V ds /2) V t Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = me m called mobility E = Vds/L Time for carrier to cross channel: t = L /V Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross I ds Qchannel W t = Cox W V C L V V V ds If Vgd < Vt, channel pinches ox off near gs drain, t When Vds 2 > Vdsat L = Vgs Vt Now drain voltage no longer increases current V V V ds V dsat V 2 2 V 2 gs Vt 2 V I Vgs V t ds V ds gs t dsat 0 Vgs Vt I V V ds V V V cutoff linear

26 Characteristics of nmos transistor: V gs = 5 I ds (ma) V gs = 4 V gs = V gs = 2 V 0 gs = V ds MOS Transistor threshold voltage: The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow the flow of electrons through the gate-source junction. FIGURE OF MERIT: A figure of merit is a quantity used to characterize the performance of a device, system or method, relative to its alternatives. In engineering, figures of merit are often defined for particular materials or devices in order to determine their relative utility for an application. In commerce, such figures are often used as a marketing tool to convince consumers to choose a particular brand. CMOS INVERTER:

27 This is a CMOS inverter, a logic gate which converts a high input to low and low to high. Click on the input at left to change its state. When the input is high, the n-mosfet on the bottom switches on, pulling the output to ground. The p-mosfet on top switches off. When the input is low, the gate-source voltage on the n-mosfet is below its threshold, so it switches off, and the p-mosfet switches on to pull the output high Inverting Amplifier : Push-pull inverter Large signal analysis VTC and Inversion voltage. Compare with the earlier VTC. Small signal analysis Gain = Vout/Vin= - (gm1+ gm2)/(gds1 + gds2) Rout = Vout/Iout Vin=0 1/(gds1 + gds2) CMOS Inverter analysis : Inverter Threshold (midpoint, inversion) Voltage(VI) : point of intersection of VTC and unity gain line. Inverter design 1: DC Design : To design the value of VI for a particular VTC Compute the design parameter from the expression of VI. Calculate the value of VI for inverter having same aspect ratio (W/L)n = (W/L)p Inverter design 2: Transient Design : The transient response should be symmetrical with tlh=thl.

28 but once (W/L)n and (W/L)p are decided the time constants are also determined. DC design sets the general shape of the switching waveforms High performance design To achieve smaller time delays in digital signal path Cout= Cint + CL, Cint : internal MOSFET capacitance and is dependent on device aspect ratio. CL: external load capacitance due to large no of fan-out. Large aspect ratio (W/L) is to be chosen for design to achieve fast charging and discharging of Cout.. Trans conductance: Transconductance, also known as mutual conductance, is a property of certain electronic components. Conductance is the reciprocal of resistance; transconductance, meanwhile, is the ratio of the current change at the output port to the voltage change at the input port. It is written as gm. For direct current, transconductance is defined as follows: PASS TRANSISTOR: In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. This reduces the number of active devices, but has the disadvantage that output levels can be no higher than the input level. Each transistor in series has a lower voltage at its output than at its input. If several devices are chained in series in a logic path, a conventionally-constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic always switches transistors to the power supply rails, so logic voltage levels in a sequential chain do not decrease.

29 BICMOS INVERTER: BiCMOS is an evolved semiconductor technology that integrates two formerly separate semiconductor technologies - those of the analog bipolar junction transistor and the digital CMOS transistor - in a single integrated circuit device. Two bipolar transistors (T3 and T4), one nmos and one pmos transistor (both enhancement-type devices, OFF at Vin=0V) The MOS switches perform the logic function & bipolar transistors drive output loads Vdd Vin T2 T4 Vout T1 T3 CL UNIT 2 VLSI CIRCIUT DESIGN PROCESSES MOS design is aimed at specification into masks for processing silicon to meet the specification.mos circuits are formed on four basic layers n-diffusion, p-diffusion, polysilicon and metal, which are isolated from one another by thick or thin(thinox)silicon dioxide insulating layers. The thin oxide (thinox) mask includes n=diffusion, p-diffusion and transistor channels. STICK DIAGRAM: Stick diagrams are used yo convey the information through the use of a color code.the below table shows the color code

30 Metal poly ndiff pdiff Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon Interface between circuit designer and fabrication engineer Compromise designer - tighter, smaller fabricator - controllable, reproducible Lambda Based Design Rules : Design rules based on single parameter, λ Simple for the designer Wide acceptance Provide feature size independent way of setting out mask If design rules are obeyed, masks will produce working circuits Minimum feature size is defined as 2 λ Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be contacted Wiring: wiring is the space required for a wire 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track

31 Design Rules : Manufacturing processes have inherent limitations in accuracy and repeatability Design rules specify geometry of masks that provide reasonable yield Design rules are determined by experience Nmos stick diagram: Layout of CMOS NAND and NOR Gates: The mask layout designs of CMOS NAND and NOR gates follow the general principles examined earlier for the CMOS inverter layout. Figure 3.7 shows the sample layouts of a two- input NOR gate and a two- input NAND gate, using single-layer polysilicon and single- layer meta.

32 CMOS Layout Design Rules: The layout designer must follow these rules in order to guarantee a certain yield for the finished product, i.e., a certain ratio of acceptable chips out of a fabrication batch. A design which violates some of the layout design rules may still result in a functional chip, but the yield is expected to be lower because of random process variations.the design rules below are given in terms of scaleable lambda-rules. Note that while the concept of scaleable design rules is very convenient for defining a technology-independent mask layout and for memorizing the basic constraints, most of the rules do not scale linearly,

33 especially for sub-micron technologies. This fact is illustrated in the right column, where a representative rule set is given in real micron dimensions. A simple comparison with the lambda- based rules shows that there are significant differences. Therefore, lambdabased design rules are simply not useful for sub-micron CMOS technologies. CMOS Design Rules: Figure 2.11 defines the design rules for a CMOS process using pictures. Arrows between objects denote a minimum spacing, and arrows showing the size of an object denote a minimum width. Rule 3.1, for example, is the minimum width of poly (2 l ). Each of the rule numbers may have different values for different manufacturers there are no standards for design rules.

34 UNIT 3 GATE LEVEL DESIGN Logic gate is an idealized or physical device implementing a Boolean function, that is, it performs a logical operation on one or more logic inputs and produces a single logic output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device. Switch logic: Switch logic is based on the pass transistor or on transmission gates. This approach is fast for small arrays and takes no static current from the supply rails. Thus, power dissipation of such arrays is small since current inly fows on switching. (figure shows transmission gates) Pass transistors and Transmission gates: Switches and switch logic ay be formed from simple n or p-pass transistors or from transmission gates comprising an n-pass and a p-pass transistor in parallel the reason for adopting the apparent complexity of the transmission gate, rather than using a simple n- switch or p-switch in most CMOS applications, is to eliminate the undesirable threshold voltage effects which give rise to the loss of logic levels in pass transistors Other forms of CMOS logic: Clocked CMOS Logic (C2MOS): Clocked CMOS logic has been used for very low power CMOS and/or for minimizing hot electron effect problems in N-FET devices.clocking transistors allow valid logic output only when clk is high. Clocking transistors may be at output end of logic trees (maximum performance) or at power supply end of logic trees (maximum protection from hot electrons)

35 Pseudo-noms logic: Using a PMOS transistor simply as a pull-up device for an n-block is called pseudo- NMOS logic. Note, that this type of logic is no longer ratio-less, i.e., the transistor widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can still pull down the output safely. Dynamic CMOS logic: The actual logic is implemented in the inherently faster nmos logic, a p-transistor is used for the non-time-critical precharging of the output line so that the output capacitance is charged to Vdd during the of period of the clock signal. Domino CMOS logic Domino logic is a CMOS-based evolution of the dynamic logic techniques which were based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits.

36 In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error. Sheet Resistance: Resistance of a square slab of material RAB = ρl/a => R = ρl/t*w Let L = W (square slab) => RAB = ρ/t = Rs ohm / square Typical sheet resistance values for materials are very well characterized Layer Rs (Ohm / Sq Aluminium 0.03 N Diffusion Silicide 2 4 Polysilicon N-transistor Channel 104 P-transistor Channel 2.5 x 104

37 N-type Minimum Feature Device: R = 1sq x Rs = Rs = 104 Ώ 2λ Capacitance: Standard unit for a technology node is the gate - channel capacitance of the minimum sized transistor (2λ x 2λ), given as Cg.This is a technology specific value. Delay Unit: For a feature size square gate, τ = Rs x Cg i.e. for 5µm technology, τ = 104 ohm/sq x 0.01pF = 0.1ns Because of effects of parasitic which we have not considered in our model, delay is typically of the order of ns Note that τ is very similar to channel transit time τsd. CMOS Inverter Delay: Pull-down delay = Rpd x 2 Cg Pull-up delay = Rpu x 2 Cg Asymmetry in rise and fall due to resistance difference between pull-up and pulldown (factor of 2.5) (due to mobilities of carriers) Delay through a pair of inverters is 2 τ (fall time) + 5 τ (rise time)

38 Delay through a pair of CMOS inverters is therefore 7 τ. CMOS Inverter Rise and Fall Time Estimation: Tf ~ 3CL / βvdd Τr ~ 3CL / βvdd (Derivations for the above are in Pucknell and Eshraghian Pages ) So, τ r/ τf = βn/βp Given that (due to motilities) βn = 2.5 βp, rise time is slower by a factor of 2.5 when using minimum dimensions of n and p transistors. Super Buffers: The symmetry of the conventional inverter is clearly undesirable, and gives rise to significant delay problems when an inverter is used to drive more significant capacitive loads. Other NMOS arrangements such as those based on the native transistor, and known as native super buffers, may be used. Unit 4: DATA PATH SUBSYSTEMS Large systems are composed of sub-systems, known as Leaf-Cell.The most basic leaf cell is the common logic gate (inverter, and,..etc). Structured Design-High regularity-leaf cells replicated many times and interconnected to form the system. Logical and systematic approach to VLSI design is essential. SHIFTER: A Shifter is most widely used for arithmetic operations. usually shifting is equivalent to multiplication by powers of two. Shifting is required during floating-point arithmetic. The shit register is simplest shifters that can shift by one position per clock cycle. BARREL SHIFTER: Barrel shifter produces n output bits and accepts 2n data bits, n control signals. The Barrel shifter shifts by transmitting a n-bits slice of the 2n data bits to the output.

39 Adders The adder is probably the most studied digital circuit. There are a great many ways to perform binary addition, each with its own area/delay trade-offs. A great many tricks have been used to speed up addition: encoding, replication of common factors and precharging are just some of them. The origins of some of these methods are lost in the mists of antiquity. Since advanced circuits are used in conjunction with advanced logic, we need to study some higher-level addition methods before covering circuits for addition. Serial adder: Serial adder may require many clock cycles to add two n-bit numbers, but with a very short cycle time. Usually, they can work on nibbles or on bytes. The most extreme form of the serial adder is a bit serial adder. When current data bits are the least significant bits of the addends then a n LSB signal is high. The addends appear LSB first and can be of arbitrary length the end of a pair of numbers is signaled by the LSB bit for the next pair.

40 CARRY SELECT ADDER: It one. comprises two versions of the addition whose carry ins are different, then selects the right ALU: An ALU is a Arithmetic Logic Unit that requires Arithmetic operations and Boolean operations. Basically arithmetic operations are addition and subtraction. one may either multiplex between an adder and a Boolean unit or merge the Boolean unit into the adder as in tha classic transistor-transistor logic.

41 MULTIPLIERS: The above figure shown is booth recoded multiplier. The multiplier is divided into two parts namely, Both-array and carry propagate adder (CPA). By ascending the 16-bit inputs, the booth array feeds the result of the multiplier is divided by the floor plan according hierarchy using an array block and a CPA block. This array section of multiplier consists of 8 ranks of adders each 17 -bits wide. The schematic which can be used to represent the first rank and remaining ranks are different. A Booth decode cell which observes 3-bits of the multiplier(mier) and procedures the control signals used in the array adders, can be used by both the above ranks. A Booth multiplier for multiplying a first number with a second number to produce product thtat has an array of array cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multipliers. This input circuitry includes a plurality of Booth recoding logic cells that control signals to mulipilexers in the adder cells in the array. the below example shows the booth recoded multiplier ARRAY MULTIPLIERS:

42 Array multipliers is a structure well suited to VLSI implementation.figure shows the structure of an array multiplier for unsigned numbers. When multiplying the multiplicand and multiplier by hand, partial products are formed in rows and accumulate in columns, with partial products shifted by the appropriate amount. In layout, the a bits generally would be distributed with horizontal wires since each row exactly one a-bits PARITY GENERATORS: Parity generators is a function related to binary addition.parity generator detects whether the number of ones in an input word is even or odd. Parity generator is most widely used to generate the parity of 16-bits or 32-bit word. COMPARATOR: The magnitude of two binary numbers is compared by a magnitude comparator. Basically a comparator is build with an adder and an inverter.

43 A<B or A>B may be generated by logical combinations of these signals. Whenever quality comparisons requires, XNOR gates and AND gates and all that is required. DYNAMIC RAM: Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. STATIC RAM: Static random-access memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. Unit 5:Programmable logic devices A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured. PLA s: Combinational circuit elements are an important part of any digital design. Three common methods of implementing a combinational block are random logic, read-only memory (ROM), and programmable logic array (PLA). In random-logic designs, the logic description of the circuit is directly translated into hardware structures such as AND and OR gates. The difficulty in this method is that the placement and interconnection cost is high. In a large system, this cost could be prohibitive. The ROM is useful for tabular data that has little regularity, but it is very wasteful of space for data that could be algorithmically derived. The PLA combines features of both other methods by allowing the designer to realize combinational design with programming taps on a logic array. The PLA is made up of an AND plane and an OR plane. The AND plane produces product terms of input variables selected by the programming taps and the OR plane produces the sums of these product terms selected by a different set of programming taps. The symbolic representation of the places where the programming taps are placed is known as the personality matrix of the PLA. Figure 4.1 shows the generic structure of a PLA that programs these logic functions:

44 PLA s are popular because their generation can be automated, which frees the designer from spending valuable time creating random-logic gates. Since the PLA generator fixes the physical structure of the PLA, there arises the problem of accommodating the designer's special requirements, if any. The first requirement would be to reduce the area occupied by the PLA. Usually the personality matrix is so sparse that a straightforward mapping of the matrix to the silicon will result in wasted silicon area. Instead, the PLA is folded to reduce the area required for the physical implementation. Instead of having one AND plane and one OR plane, the PLA can be split into many more AND and OR planes. Also, the input and output columns can be moved and folded such that there are two to a column instead of the usual one. The rows can be similarly moved and folded. Gate-Arrays: The gate-array is a popular technique used to design IC chips. Like the PLA, it contains a fixed mesh of unfinished layout that must be customized to yield the final circuit. Gate-arrays are more powerful, however, because the contents of the mesh are less structured so the interconnection options are more flexible.

45 Typical gate-array is built from blocks that contain unconnected transistor pairs, although any simple component will do. An array of these blocks combined with I/O pads forms a complete integrated circuit and offers a wide range of digital electronic options (as shown in above figure). These blocks are internally customized by connecting the components to form various logical operators such as AND, OR, NOT, and so on. The blocks are also externally connected to produce the overall chip. VLSI Design Styles: Full Custom ASIC - Application-Specific Integrated Circuit PLD, FPGA - Programmable Logic So C - System-on-a-Chip Full Custom Design Style: Pre-manufactured components with programmable interconnect wired by CAD tools Tradeoffs High Design Costs (huge effort!) High NRE Cost High Performance Low Unit Cost (good for high volume products!) Examples Analog and Mixed-Signal Microprocessor ASIC Design Style: Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools. Standard cell (pre-designed cells) Gate array (pre-manufactured cells - just add wiring) Structured ASIC (complex function customized by wiring) Tradeoffs Low Design Cost High NRE Cost (lower in Gate Array / Structured ASIC) Medium Unit Cost Medium Performance Examples: Control chip for cell phone

46 Graphics chips for desktop computers (e.g. nvidia, ATI) CPLD: As the technology surrounding programmable devices improved, new devices were developed which combined several PLD s together on a single integrated circuit to form complex programmable logic devices, CPLD s. The concept is to have a few PLD blocks or macro cells on a single device with a general-purpose interconnect in-between. Basically, a CPLD consists of several blocks, each of which is a PLD, which are connected together. I/Os of each of the PLD blocks are connected by a global interconnect array. Each logic block contains 4 to 16 macro cells depending on the vendor and the architecture. A macro cell on most modern CPLD s contains a sum-ofproducts combinatorial logic function and an optional flip-flop. The combinatorial logic function typically supports four to 16 product terms with wide fan-in. In other words, a macro cell function can have many inputs, but the complexity of the logic function is limited. CPLD s are generally best for control- oriented designs due in part to their fast pin-to-pin performance. The wide fan-in of their macro cells makes them well-suited to complex, high-performance state machines. CPLD has less flexible internal architecture and the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorter. The below figure shows CPLD architecture. FPGA: At the beginning of 1980, there were programmable logic devices, which had fast design, highly configurable and reprogrammable, but they were support only small functions.an FPGA have bunch of programmable logic blocks in an array with programmable switches. FPGA s are approximately 10 times less dense. FPGA has two levels of programmability, each logic block can be programmed individually to perform simple logic functions and then, switches can be programmed to implement desire logic function. The key element in programmable logics are 3-input Look Up Table (LUT), multiplexer and flip-flop. The 3-input LUT is similar to PAL,

47 used to implement combinational or Boolean equations. FPGA s contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGA s, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. PAL - Programming Array Logic: PALs were introduced in late 1970 to address speed problem shown by PLA devices. A PAL is opposite to PROM, where AND array is programmable but OR array is fixed. This led PAL faster than PLA devices. PAL s usually contain flip-flops connected to the OR-gate outputs to implement sequential circuits. Registered or combinational output functions are modeled in a sum of product form. Each output is a sum (logical or) of a fixed number of products (logical and) of the input signals. PAL architecture has feedback terms. The outputs of the fixed "or" array are fed back to some of the inputs of the "and" array.