DATASHEET ISL71010B50. Features. Applications. Related Literature. Ultra Low Noise, 5V Precision Voltage Reference

Transcription

1 DATASHEET ISL711B5 Ultra Low Noise, 5V Precision Voltage Reference FN8961 Rev.. The ISL711B5 is an ultra low noise, high DC accuracy precision voltage reference, with a wide input voltage range from 7.V to 3V. The ISL711B5 uses the dielectrically isolated PR4 process to achieve 4.2µV P-P noise at.1hz to 1Hz with an initial voltage accuracy of ±.5%. The ISL711B5 offers a 5.V output voltage with 1ppm/ C temperature coefficient and also provides excellent line and load regulation. The device is offered in an 8 Ld SOIC package. The ISL711B5 is ideal for high-end instrumentation, data acquisition, and processing applications requiring high DC precision where low noise performance is critical. Applications Low Earth Orbit (LEO) High altitude avionics Precision instruments Data acquisition systems for space applications Strain and pressure gauges for space applications Active sources for sensors Features Reference output voltage: 5.V ±.5% Accuracy over temperature/radiation: ±.15% Output voltage noise: 4.2µV P-P typical (.1Hz to 1Hz) Supply current: 93µA (typical) Temperature coefficient: 1ppm/ C (maximum) Output current capability: 2mA Line regulation: 2ppm/V (maximum) Load regulation: 17ppm/mA (maximum) NiPdAu-Ag lead finish (Sn Free) Dielectrically isolated PR4 process Operating temperature range: -55 C to +125 C Characterized radiation level Low dose rate (1mrad(Si): 3 krad(si) Single event burnout LET: 43MeV cm 2 /mg Related Literature For a full list of related documents, visit our website ISL711B5 product page. VIN 1µF.1µF DNC VIN COMP GND DNC DNC VOUT TRIM VREF.1µF UNIT4 5.5V +.1% VDD VREF DACOUTx Serial Clock Chip Select SCLK CSb OUTxS OUTxF Serial Data I/O SDIO GND DAC Figure 1. ISL711B5 Typical Application Diagram V OUT (V) 5.6 UNIT UNIT3 UNIT1 UNIT V -.1% Temperature ( C) Figure 2. V OUT vs Temperature FN8961 Rev.. Page 1 of 22

2 1. Overview 1. Overview 1.1 Functional Block Diagram VIN BIAS REGULATOR DNC DNC DNC BAND GAP REFERENCE 1.2V 3.7V GND VOUT COMP TRIM 1.2V 1.2 Ordering Information Figure 3. Functional Block Diagram) Part Number (Notes 1, 2, 3) Part Marking V OUT Option (V) Accuracy (%) Tempco (ppm/ C) Temp Range ( C) Package (RoHS Compliant) Pkg. Dwg. # ISL711BMB5Z 711 BMZ5 5. ± to Ld SOIC M8.15 ISL711BM5EV1Z Evaluation Board Notes: 1. Add -TK suffix for 1k unit tape and reel option. Refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and NiPdAu-Ag plate -e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD For Moisture Sensitivity Level (MSL), see the product information page for the ISL711B5. For more information on MSL, refer to TB363. FN8961 Rev.. Page 2 of 22

3 1. Overview 1.3 Pin Configuration ISL711B5 (8 Ld SOIC) Top View 1 DNC DNC 8 2 VIN DNC 7 3 COMP VOUT 6 4 GND TRIM Pin Descriptions Pin Number Pin Name ESD Circuit Description 1, 7, 8 DNC 3 Do not connect. Internally terminated. 2 VIN 1 Input voltage connection 3 COMP 2 Compensation and noise reduction capacitor 4 GND 1 Ground connection. 5 TRIM 2 Voltage reference trim input 6 VOUT 2 Voltage reference output VDD VDD VDD CAPACITIVELY TRIGGERED CLAMP PIN GND GND DNC ESD CIRCUIT 1 ESD CIRCUIT 2 ESD CIRCUIT 3 FN8961 Rev.. Page 3 of 22

4 2. Specifications 2. Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit Max Voltage V IN to GND V V OUT to GND (1s) -.5 V OUT +.5 V Voltage on any Pin to Ground -.5 +V OUT +.5 V Voltage on DNC pins No connections permitted to these pins Input Voltage Slew Rate (Max).1 V/µs ESD Rating Value Unit Human Body Model (Tested per JS-1-214) 3 kv Machine Model (Tested per JESD22-A115-C) 2 V Charged Device Model (Tested per JS-2-214) 2 kv Latch-up (Tested per JESD-78E; Class 2, Level A, at +125 C) ±1 ma CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) 8 Ld SOIC Package (Notes 4, 5) 11 6 Notes: 4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB For JC, the case temp location is taken at the package top center. Parameter Minimum Maximum Unit Continuous Power Dissipation (T A = +125 C) 217 mw Maximum Junction Temperature (T JMAX ) +15 C Storage Temperature Range C 2.3 Recommended Operating Conditions Parameter Minimum Maximum Unit V IN V Temperature Range C FN8961 Rev.. Page 4 of 22

5 2. Specifications 2.4 Electrical Specifications V IN = 1V, I OUT = ma, C OUT =.1µF, COMP = 1nF unless otherwise specified. Boldface limits apply across the operating temperature range, -55 C to +125 C. Parameter Symbol Conditions Min (Note 7) Typ Max (Note 7) Unit Output Voltage V OUT V IN = 1V 5. V V OUT Accuracy at T A = +25 C V OA V OUT = 5.V, (Note 6) % V OUT Accuracy at T A = -55 C to +125 C V OUT = 5.V, (Note 6) % Output Voltage Temperature Coefficient (Note 8) TC V OUT 1 ppm/ C Input Voltage Range V IN V OUT = 5.V 7 3 V Supply Current I IN ma Line Regulation V OUT / V IN V IN = 7V to 3V, V OUT = 5.V 8 2 ppm/v Load Regulation V OUT / I OUT Sourcing: ma I OUT 2mA ppm/ma Sinking: -1mA I OUT ma ppm/ma Dropout Voltage (Note 9) V D V OUT = 5.V at 1mA V Short-Circuit Current I SC+ T A = +25 C, V OUT tied to GND ma Short-Circuit Current I SC- T A = +25 C, V OUT tied to V IN -1-6 ma Turn-On Settling Time t R 9% of final value, C L = 1.µF, C C = Open 15 µs Ripple Rejection f = 12Hz 9 db Output Voltage Noise e np-p.1hz f 1Hz, V OUT = 5.V 4.2 µv P-P Broadband Voltage Noise V n 1Hz f 1kHz, V OUT = 5.V 3.2 µv RMS Noise Voltage Density e n f = 1kHz, V OUT = 5.V 1 nv/ Hz Long Term Stability V OUT / t T A = +25 C 2 ppm Notes: 6. Post-reflow drift for the ISL711B5 devices can exceed 1µV to 1.mV based on experimental results with devices on FR4 double sided boards. The system engineer must take this into account when considering the reference voltage after assembly. 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 8. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in V OUT is divided by the temperature range; in this case, -55 C to +125 C = +18 C. See Temperature Coefficient on page Dropout Voltage is the minimum V IN - V OUT differential voltage measured at the point where V OUT drops 1mV from V IN = nominal at T A = +25 C. FN8961 Rev.. Page 5 of 22

6 3. Typical Performance Curves 3. Typical Performance Curves V +.1% V +.1% 5.8 V OUT (V) ma +125 C V OUT (V) ma +25 C 5.8 Unit 4 V OUT (V) V OUT (V) ma -55 C V OUT (V) Unit V -.1% V IN (V) Figure 4. V OUT Accuracy Over Temperature 5.2 Unit 3 Unit 1 Unit V -.1% Temperature ( C) Figure V V OUT Limits Plot V OUT (V) V -.1% 5.5V +.1% V OUT (V) ma +25 C V OUT (V) 2mA +25 C V OUT (V) -1mA +25 C V OUT (V) ma +125 C V OUT (V) 2mA +125 C V OUT (V) -1mA +125 C V OUT (V) ma -55 C V OUT (V) 2mA -55 C V OUT (V) -1mA -55 C V IN (V) Figure 6. V OUT vs V IN AT ma, 2mA, and -1mA Unit I IN (µa) 15 1 Unit Unit V IN (V) Figure 7. I IN vs V IN, Three Units I IN (µa) C -4 C +25 C V IN (V) Figure 8. I IN vs V IN, Three Temperatures FN8961 Rev.. Page 6 of 22

7 3. Typical Performance Curves V OUT (V) UNIT UNIT UNIT V IN (V) V OUT (V) C C C V IN (V) Figure 9. Line Regulation, Three Units Figure 1. Line Regulation, Three Temperatures 3.5 Line Regulation (ppm/v) Line Reg ppm/v +125 C Line Reg ppm/v M-55 C Line Reg ppm/v +25 C V IN (V) Figure 11. Line Regulation Over Temperature Amplitude (mv) 1-1 C L = 1nF Amplitude (mv) 1-1 C L = 1nF Time (µs) Figure 12. Line Transient with 1nF LOAD ( V IN = ±5mV) Time (µs) Figure 13. Line Transient with 1nF LOAD ( V IN = ±5mV) FN8961 Rev.. Page 7 of 22

8 3. Typical Performance Curves DV OUT (PPM) C C -4 C (Sourcing) I LOAD (ma) (Sinking) Figure 14. Load Regulation, Three Temperatures Amplitude (mv) C L = 1nF 4 C L = 1µF Time (µs) Figure 15. Load Transient ( I LOAD = ±1mA) +25 C V IN = 7V; V OUT = 5.5V; I OUT = ma TO 1mA; Slew Rate = 2mA/µs; C OUT = 1µF COMP = 1pF V OUT 1µs/DIV 2mV/DIV Figure 16. Load Transient (ma to 1mA) V IN 8 V IN V OUT (V) C L =.1µF V OUT (V) C L = 1µF Time (µs) Time (µs) Figure 17. Turn-On Time with.1µf Figure 18. Turn-On Time with 1µF FN8961 Rev.. Page 8 of 22

9 3. Typical Performance Curves Z OUT (W) C L = 1nF C L = 1nF C L = C L = 1nF PSRR (db) C L = 1nF C L = C L = 1nF C L = 1nF k 1k 1k 1M 1M Frequency (Hz) Figure 19. Z OUT vs Frequency k 1k 1k 1M 1M Frequency (Hz) Figure 2. PSRR at Different Capacitive Loads -2-4 PSRR (db) k 1k 1k 1M Frequency (Hz) Figure 21. PSRR (+25 C, V IN = 7V, V OUT = 5.5V, I OUT = ma, C IN =.1µF, C OUT = 1.µF, COMP = 1nF, V SIG = 3mV P-P ) -2 1 Current (ma) C -4 C +25 C Current (ma) C +25 C +125 C V IN (V) Figure 22. Short-Circuit to GND V IN (V) Figure 23. Short-Circuit to V IN FN8961 Rev.. Page 9 of 22

10 3. Typical Performance Curves V OUT (V) C +25 C +125 C Dropout (V) Dropout V AT +25 C Dropout V AT +15 C Dropout V AT +125 C V IN (V) I OUT (ma) Figure 24. Dropout with -1mA LOAD Figure 25. Dropout Voltage for 5.5V Output Noise Voltage (µv) Time (s) Figure 26. V OUT vs Noise,.1Hz to 1Hz Noise (nv/ Hz) 1k 1k 1 1 f = 1kHz, En = 67.9nV/ Hz k 1k 1k Frequency (Hz) Figure 27. Noise Density vs Frequency (V IN = 7.1V, I OUT = ma, C IN =.1µF, C OUT = 1µF, COMP = 1nF) FN8961 Rev.. Page 1 of 22

11 4. Applications Information 4. Applications Information 4.1 Bandgap Precision Reference The ISL711B5 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. 4.2 Board Mounting Considerations For applications requiring the highest accuracy, the board mounting location should be considered. The device uses a plastic SOIC package, which subjects the die to mild stresses when the Printed Circuit Board (PCB) is heated and cooled, which slightly changes the shape. Because of these die stresses, placing the device in areas subject to slight twisting can cause degradation of the reference voltage accuracy. It is normally best to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. Mounting the device in a cutout also minimizes flex. Obviously, mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy. 4.3 Board Assembly Considerations Some PCB assembly precautions are necessary. Normal output voltage shifts of 1µV can be expected with Pb-free reflow profiles or wave solder on multi-layer FR4 PC boards. Precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. 4.4 Noise Performance and Reduction The output noise voltage in a.1hz to 1Hz bandwidth is typically 4.2µV P-P (V OUT = 5.V). The noise measurement is made with a bandpass filter. The filter is made of a 1-pole high-pass filter, with a corner frequency at.1hz, and a 2-pole low-pass filter, with a corner frequency (3dB) at 9.9Hz, to create a filter with a 9.9Hz bandwidth. Noise in the 1Hz to 1kHz bandwidth is approximately 3.2µV RMS, with 1uF capacitance on the output. This noise measurement is made with a 2 decade bandpass filter. The filter is made of a 1-pole high-pass filter with a corner frequency at 1Hz of the center frequency, and 1-pole low-pass filter with a corner frequency at 1kHz. Load capacitance up to 1µF can be added, but will result in only marginal improvements in output noise and transient response. 4.5 Turn-On Time Normal turn-on time is typically 25µs. The circuit designer must take this into account when looking at power-up delays or sequencing. 4.6 Temperature Coefficient The limits stated for temperature coefficient (Tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures. Take the total variation, (V HIGH V LOW ), and divide by the temperature extremes of measurement (T HIGH T LOW ). The result is divided by the nominal reference voltage (at T = +25 C) and multiplied by 1 6 to yield ppm/ C. This is the Box method for specifying temperature coefficient. 4.7 Output Voltage Adjustment The output voltage can be adjusted above and below the factory-calibrated value using the trim terminal. The trim terminal is the negative feedback divider point of the output op amp. The voltage at the trim pin is set at approximately 1.216V by the internal bandgap and amplifier circuitry of the voltage reference. The suggested method to adjust the output is to connect a 1MΩ external resistor directly to the trim terminal and connect the other end to the wiper of a potentiometer that has a 1kΩ resistance and with outer terminals thatconnect to V OUT and ground. If a 1MΩ resistor is connected to trim, the output adjust range will be ±6.3mV. The TRIM pin should not have any capacitor tied to its output. Also it is important to minimize the capacitance on the trim terminal during layout to preserve output amplifier stability. It is also best to connect the series resistor FN8961 Rev.. Page 11 of 22

12 4. Applications Information directly to the trim terminal, to minimize that capacitance and also to minimize noise injection. Small trim adjustments will not disturb the factory-set temperature coefficient of the reference, but trimming near the extreme values can. 4.8 Output Stage The output stage of the device has a push pull configuration with a high-side PNP and a low-side NPN. This helps the device to act as a source and sink. The device can source 2mA. 4.9 Use of COMP Capacitors The reference can be compensated for the C OUT capacitors used by adding a capacitor from COMP pin to GND. See Table 1 for recommended values of the COMP capacitor. C OUT (µf) Table 1. COMP Capacitor Recommended Values C COMP (nf) FN8961 Rev.. Page 12 of 22

13 5. Radiation Tolerance 5. Radiation Tolerance The ISL711B5 is a radiation tolerant device for commercial space applications, Low Earth Orbit (LEO) applications, high altitude avionics, launch vehicles, and other harsh environments. This device s response to Total Ionizing Dose (TID) radiation effects and Single-Event Effects (SEE) has been measured, characterized, and reported in the following sections. However, TID performance is not guaranteed through radiation acceptance testing, nor is the SEE characterized performance guaranteed. 5.1 Total Ionizing Dose (TID) Testing Introduction This test was conducted to determine the sensitivity of the part to the total dose environment. Down points were krad(si), 1krad(Si), and 3krad(Si). Reference the ISL711B25 datasheet for additional down point and anneal results. Total dose testing was performed using a Hopewell Designs N4 panoramic 6 Co irradiator. The irradiations were performed at.875rad(si)/s. A PbAl box was used to shield the test fixture and devices under test against low energy secondary gamma radiation. The characterization matrix consisted of four samples irradiated under bias and four samples irradiated with all pins grounded. Four control units were used to ensure repeatable data. Two different wafers were used. The bias configuration is shown in Figure 28. VIN C 2 D 2 U NC VIN COMP GND NC NC VOUT TRIM C 3 C 4 C 5 VOUT TP1 R L TP2 PARTS: V IN = +36V ±1% R 1 = 3.86k, 1%, 1W R 2 = 47, 1%, 1W R L = 5k, 1%, 1/ 4 W C 2 =.1µF, 5V, 1%, X7R C 3, C 4 =.1µF, 5V, 1%, X7R C 5 =.1µF, 1V, 1%, X7R Figure 28. Irradiation Bias Configuration and Power Supply Sequencing for the ISL711B5 All electrical testing was performed outside the irradiator using the production Automated Test Equipment (ATE), with data logging at each down point. Down-point electrical testing was performed at room temperature. FN8961 Rev.. Page 13 of 22

14 5. Radiation Tolerance Results Table 2 summarizes the attributes data. Note that Bin 1 indicates a device that passes all datasheet specification limits. Table 2. ISL711B5 Total Dose Test Attributes Data Dose Rate (mrad(si)/s) Bias Sample Size Down Point Bin 1 Rejects 8.75 Figure 28 4 Pre-rad 4 1krad(Si) 4 3krad(Si) Grounded 4 Pre-rad 4 1krad(Si) 4 3krad(Si) 4 The plots in Figures 29 through 34 show data for key parameters at all down points. The plots show the average as a function of total dose for each of the irradiation conditions. All parts showed excellent stability over irradiation. Table 3 on page 16 shows the average of the key parameters with respect to total dose in tabular form Data Plots Max Limit 1.2 Max Limit Output Voltage (V) V IN = 7V, 1V, 36V (Biased) V IN = 7V, 1V, 36V (Grounded) Supply Current (ma) V IN = 7V, 1V (Biased) Min Limit 4.99 K 1K 2K 3K Total Dose (rad(si)) Figure 29. VREF Output Voltage vs TID V.2 IN = 7V, 1V (Grounded) Spec Max. K 1K 2K 3K Total Dose (rad(si)) Figure 3. Supply Current vs TID FN8961 Rev.. Page 14 of 22

15 5. Radiation Tolerance Line Regulation (ppm/v) Max Limit Avg (Biased) Avg (Grounded) -15. Min Limit K 1K 2K 3K Total Dose (rad(si)) Figure 31. Line Regulation vs TID Load Regulation 2mA (ppm/ma) Max Limit Avg (Biased) 2. Avg (Grounded). -2. K 1K 2K 3K Total Dose (rad(si)) Figure 32. Load Regulation 2mA Sourcing vs TID Load Regulation -1mA (ppm/ma) Max Limit Avg (Biased) 4. Avg (Grounded) K 1K 2K 3K Total Dose (rad(si)) Figure 33. Load Regulation -1mA Sinking vs TID Short-Circuit Current (ma) ISC+ Avg (Biased) 2. ISC+ Avg (Grounded). -2. ISC- Avg (Biased) -4. ISC- Avg (Grounded) Max Limit Spec Min Min Limit -12. K 1K 2K 3K Total Dose (rad(si)) Figure 34. Short-Circuit Current vs TID Conclusion ATE characterization testing showed no rejects to the datasheet limits at all down points. Variables data for selected parameters is presented in Figures 29 through 34. No differences between biased and unbiased irradiation were noted, and the part is not considered bias sensitive. FN8961 Rev.. Page 15 of 22

16 5. Radiation Tolerance Table 3. ISL711B5 Response of Key Parameters vs TID Parameter Symbol Condition Bias krad(si) 1krad(Si) 3krad(Si) Unit Output Voltage V OUT V IN = 1V Biased V Grounded V IN = 7V Biased Grounded V IN = 36V Biased Grounded Supply Current I IN V CC = 7V Biased ma Grounded V CC = 1V Biased Grounded Line Regulation Load Regulation V OUT V IN = 4V to 3V, V OUT = 2.5V Biased ppm/v / V IN Grounded V OUT 2mA Sourcing Biased ppm/ma / I OUT Grounded Single Event Effects Testing Introduction The intense heavy ion environment encountered in space applications can cause a variety of Single-Event Effects (SEE). SEE can lead to system-level performance issues including disruption, degradation, and destruction. For predictable and reliable space system operation, individual electronic components should be characterized to determine their SEE response. The following is a summary of the ISL711B5 SEE testing SEE Test Setup -1mA Sinking Biased Grounded Short-Circuit Current I SC+ V OUT = GND Biased ma Grounded I SC- V OUT = V IN Biased Grounded Testing was performed at the Texas A&M University (TAMU) Cyclotron Institute heavy ion facility. A schematic of the ISL711B5 SEE test circuit is shown in Figure 39 on page 19. The test circuit is configured to accept an input voltage from 7V to 3V and generate the 5.V nominal output voltage. The output current of the reference was adjusted using fixed load resistors on a test board. The output capacitor, C 4, and the compensation capacitor C 2 were.1µf and 1nF, respectively. Digital multimeters were used to monitor input voltage (V IN ), output voltage (V OUT ), and input current (I IN ). A LeCroy waverunner digital oscilloscope was used to monitor, capture, and store key signal waveforms. The scope was configured to trigger with VOUT signal levels of ±5mV. FN8961 Rev.. Page 16 of 22

17 5. Radiation Tolerance SEB Testing Results For the SEB tests, conditions were selected to maximize the electrical and thermal stresses on the Device Under Test (DUT), thus insuring worst-case conditions. The input voltage (V IN ) was initially set to 35V and then increased in 1V increments. The capacitors were set to C OUT =.1µF and C COMP = 1nF. SEB testing was conducted with the ISL711B25. Output current (I OUT ) was set to 2mA which is the maximum recommended current rating for load regulation of the device. Case temperature was maintained at +125ºC by controlling the current flowing into a resistor heater bonded to the underside of the DUT. Four DUTs were irradiated with Ag ions at a normal incident angle, resulting in an effective LET of 43MeV cm 2 /mg. The failure criterion for destructive SEE was an increase in operating input current (I IN ) greater than 5% measured at 2mA output current. I IN is defined as the total current drawn by the device. Failed devices were not further irradiated. From a design perspective, the ISL711B25 and the ISL711B5 are exactly the same in silicon. The output voltage, even though they are different values, are produced the same way and trimmed through a resistor ladder network. All the parts are built in the same process and are functionally equivalent. Therefore, the ISL711B25 SEB results are applicable to the ISL711B5. Four parts passed irradiation to 1x1 7 ions/cm 2 with 43MeV cm 2 /mg at 39V and +125ºC case temperature Single Event Transient (SET) Testing SET testing was done on four samples of the ISL711B5, which were irradiated at room temperature at LETs of 2.7MeV cm 2 /mg and 28MeV cm 2 /mg to observe SET performance. Samples were separately tested to V IN of 7V and 3V. The parts were configured with a.1µf output capacitor, 1nF compensation capacitor, and a 2mA load current to set up the worst conditions for negative going transients. Table 4 shows the SET summary giving the cross section for each input voltage and LET level. Figures 35 through 38 represent output waveform responses of the DUTs at the respective bias conditions and LET levels. The plots are composites of all the transients captured on the scope. The SET exhibited by the ISL711B5 fall into two basic categories; fast negative spike and slow negative ramp. The fast spikes can be as large as 5mV for LET 28 and V IN = 3V. Under the same conditions, the slow (2µs) negative ramp can reach 3mV. The slow ramp disturbances can take significantly over 16µs to recover. Even at LET = 8.5MeV cm 2 /mg (Figures 35 and Figures 36), there are SET of approximately 2mV. Table 4. SET Summary of Fully Functional ISL711B5 Samples at 7.V and 3V Input Voltage. Trigger Level for the Output Voltage SET to ±5mV. Supply Voltage (V) LET (MeV cm 2 /mg) Fluence (Particles/cm 2 ) Events (±5mV) Events CS (cm 2 ) E E E E E E E E-4 FN8961 Rev.. Page 17 of 22

18 5. Radiation Tolerance.5 5mV/DIV.5 5mV/DIV Amplitude (V) -.5 2mV Amplitude (V) -.5 2µs/DIV Time (sec) x1-5 Figure 35. Composite SET Plot for ISL711B5 at LET 8.5 V IN = 7V, I OUT = 2mA, C OUT =.1µF, C COMP = 1nF 2µs/DIV Time (sec) x1-5 Figure 36. Composite SET Plot for ISL711B5 at LET 8.5 V IN = 3V, I OUT = 2mA, C OUT =.1µF, C COMP = 1nF.5 5mV/DIV.5 5mV/DIV Amplitude (V) -.5 AMPLITUDE (V) -.5 2µs/DIV Time (sec) x1-5 Figure 37. Composite SET Plot for ISL711B5 at LET 28 V IN = 7V, I OUT = 2mA, C OUT =.1µF, C COMP = 1nF 2µs/DIV Time (sec) x1-5 Figure 38. Composite SET Plot for ISL711B5 at LET 28 V IN = 3V, I OUT = 2mA, C OUT =.1µF, C COMP = 1nF FN8961 Rev.. Page 18 of 22

19 6. Conclusion 6. Conclusion SEE testing has demonstrated that the ISL711B5 is not susceptible to Single Event Burnout (SEB) at an LET of 43MeV cm 2 /mg with an input voltage of 39V and a load current of 2mA. This represents conditions that are over 3% above the recommended input voltage of 3V and 1% of the load regulation drive capability of the IC (2mA). SET testing demonstrated that all transients are negative and the higher the LET level the greater the magnitude of the negative transient. At LET = 28MeV cm 2 /mg and V IN = 3V with C OUT =.1µF, showed a 5mV fast negative transient and a 3mV slow (2us) negative transient during an SET event. The slow transient can take over 16us to recovery. At LET = 8.5MeV cm 2 /mg there are SET of approximately 2mV. A larger C OUT capacitance value will suppress the SET magnitude but the SET disturbance duration will stretch out. Capacitor selection represents a compromise between SET magnitude and recovery duration. Figure 39. SEE Testing Schematic for the ISL711B5 FN8961 Rev.. Page 19 of 22

20 7. Revision History 7. Revision History Rev. Date Description. Initial release FN8961 Rev.. Page 2 of 22

21 8. Package Outline Drawing 8. Package Outline Drawing For the most recent package outline drawing, see M8.15. M LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (.5).4 (.16) INDEX AREA 4. (.157) 3.8 (.15) 6.2 (.244) 5.8 (.228).5 (.2).25 (.1) x TOP VIEW 8 SIDE VIEW B.25 (.1).19 (.8) 2.2 (.87) SEATING PLANE (.197) 4.8 (.189) 1.75 (.69) 1.35 (.53) (.23) 1.27 (.5) 3 6 -C (.5).51(.2).33(.13).25(.1).1(.4) (.25) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-12-AA ISSUE C. FN8961 Rev.. Page 21 of 22

22 9. About Intersil 9. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at For a listing of definitions and abbreviations of common terms used in our documents, visit: You can report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC 217. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN8961 Rev.. Page 22 of 22