Lesson: Binary Arithmetic and Arithmetic Circuits-2. Lesson Developer: Dr. Divya Haridas
|
|
- Isaac May
- 6 years ago
- Views:
Transcription
1 Bary Arithmetic and Arithmetic Circuits-2 Lesson: Bary Arithmetic and Arithmetic Circuits-2 Lesson Developer: Dr. Divya Haridas College/ Department: Keshav Mahavidyalaya, University of Delhi 1 Institute of Lifelong Learng, University of Delhi
2 Table of Contents Bary Arithmetic and Arithmetic Circuits-2 Arithmetic Circuits-2 Chapter 2 Arithmetic Circuits 2.1 Chapters Objective 2.2 Introduction 2.3 Arithmetic Circuits 2.4 Adder Half Adder Full Adder 2.5 Subtractor Half Subtractor Full Subtractor 2.6 Adder/Subtractor bit parallel Adder/Subtractor 2.7 Summary 2.8 Exercises Subjective Questions Fill the Blanks Multiple Choice Questions 2.9 Glossary 2.10 References 2 Institute of Lifelong Learng, University of Delhi
3 Bary Arithmetic and Arithmetic Circuits Chapter Objectives Introduction to combational logic circuits. Design Half adder and understand it s workg. Design Full adder and to understand it s workg. To implement Bary addition usg Full adder Design Half Subtractor and understand it s workg. Design Full Subtractor and to understand it s workg. To implement Bary Subtraction usg Full Subtractor. Use full adders to implement four bit adder/subtractor 2.2 Introduction Logic circuits digital systems are broadly classified as A) Combational logic circuits B) Sequential logic circuits. A combational circuit is one whose output at any time is determed from the present combation of puts whereas the outputs of sequential circuits at any time depend not only on present value of puts but also on the past puts. Arithmetic circuits are the examples of combational circuits. I/P Combational O/P I/P Sequential Circuits O/P circuits Feedback 2.3 Arithmetic circuits Figure 1: Block diagram of combational and sequential circuits Arithmetic circuits are the circuits that perform arithmetic operations such as addition and subtraction, examples of arithmetic circuit are adders and subtractors. Adders are important digital systems which numerical data are processed. In this section adders, subtractor and adder/subtractor are troduced. 2.4 Adder Half Adder The half adder accepts two bary digits on its put and provides two bary digits on its outputs, a sum bit and a carry bit. The logic symbol of half adder is given figure 2. Σ Input bits C A Σ Sum B out Carry Output bits Figure 2: Logic symbol of Half Adder 3 Institute of Lifelong Learng, University of Delhi
4 Bary Arithmetic and Arithmetic Circuits-2 The truth table for half adder is given as Tip to memorize A B C out Σ Σ Sum C out =Carry A & B are the put variables Whenever odd number of 1 is present truth table then sum will be high. When both puts are 1 then only carry will be high. From the above truth table the Boolean expression for sum and carry are S AB AB A B C AB A half adder can therefore be realized by usg one X-OR gate (for sum operation) and one AND gate (for carry operation). The logic circuit for half adder is shown figure 3 Figure 3: Circuit diagram of Half Adder The logic circuit for half adder can be implemented usg only NAND gates and is shown figure 4 4 Institute of Lifelong Learng, University of Delhi
5 Bary Arithmetic and Arithmetic Circuits-2 Figure 4: Circuit diagram for half adder implemented usg NAND gates only The Boolean expression for sum and carry is given as: Sum AAB BAB A AB B AB A ( A B) B ( A B) AA AB BA BB AB AB Carry AB AB Try yourself Draw logic circuit for half adder usg only NOR gates only. Solution: Full Adder A half adder has only two puts and there is no provision to add a carry comg from the lower bits even the case of 4 bit addition operation. For this another circuit is required which can add three bits simultaneously. A full adder is a combational logic circuit that performs the arithmetic addition of three put bits. The full adder accepts two put bits and put carry and generates a sum output and an output carry. So a full adder has three puts and two outputs. The logic symbol of full adder is given figure 5 Σ Input bits Input Carry A B Σ Sum Output bits C C out Carry 5 Institute of Lifelong Learng, University of Delhi
6 Bary Arithmetic and Arithmetic Circuits-2 Figure 5: Logic symbol of full adder Two of the put variables denoted by A and B represent the two significant bits to be added. The third put C represents the carry from the previous lower significant position. Table 2 shows the truth table for a full adder. A B C C out Σ Σ Sum C =Input Carry C out =Output Carry A, B & C are the put variables Tip to memorize When the number of 1 s truth table is odd then the output for sum would be high. i.e it will follow a three put XOR gate function. Whenever the number of 1 s truth table appear more than once, then carry will be high. Karnaugh Map simplification for Full Adder Karnaugh Map for Sum C A B 0 C 1 AB 1 0 AB 0 1 A B 1 0 Boolean expression for sum = ABC ABC ABC ABC 6 Institute of Lifelong Learng, University of Delhi
7 Bary Arithmetic and Arithmetic Circuits-2 Karnaugh Map for Carry C C A B 0 0 AB 0 1 AB 1 1 A B 0 1 Boolean expression for Carry = AB BC AC From the above Boolean expression we can design the logic circuit for full adder. Students are advised to first design the circuit on their own and then verify their results. Figure 6 shows the simplified circuit diagram of Full adder Figure 6: Logic circuit for Full adder Full adder can also be designed usg two half adders. Logic circuit of Full adder usg two half adders is given figure 7 7 Institute of Lifelong Learng, University of Delhi
8 Bary Arithmetic and Arithmetic Circuits-2 Figure 7: Logic circuit of Full adder usg two half adders Complete logic circuit of figure 7 is given figure 8. Figure 8: Complete logic circuit of Full adder usg two half adders The sum output of the first half adder is the exclusive OR (X-OR) of two put variables A B. This output is fed as put for the second half adder. The second put variable for the second half adder is C (carry put). Therefore this put carry C must be exclusive ORed with A B, yieldg the equation for the sum Sum, A B C AB ABC AB A BA B C ABC ABC AB AB C ABC ABC ABC ABC AB C 8 Institute of Lifelong Learng, University of Delhi ABC ABC The output carry is a 1 when both puts to the first XOR gate are 1s or when both puts to the second XOR gate are 1s. The output carry of the full adder is therefore produced by the puts A ANDed with B and expression is given as A B ANDed with C. These two terms are ORed and the
9 Bary Arithmetic and Arithmetic Circuits-2 C Out AB AB AB ABC A B BC A B C AB AC A B C AB AC ABC AB A ABC AB A B C AB AB C ABC BC ABC ABC Try Yourself Design Full Adder usg universal NAND gate only. Design Full Adder usg universal NOR gate only. 9 Institute of Lifelong Learng, University of Delhi
10 Bary Arithmetic and Arithmetic Circuits-2 Value Addition More complex adders Ripple-carry adder It is possible to create a logical circuit usg multiple full adders to add N-bit numbers. Each full adder puts a C, which is the C out of the previous adder. This kd of adder is called a ripple-carry adder, sce each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder (under the assumption that C = 0). The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, sce each full adder must wait for the carry bit to be calculated from the previous full adder. Carry-look ahead adder 4-bit adder with carry look ahead A carry-look ahead adder (CLA) is a type of adder used digital logic. A carry-look ahead adder improves speed by reducg the amount of time required to determe carry bits. It can be constructed with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to beg calculatg its own result and carry bits. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. The Kogge-Stone adder and Brent-Kung adder are examples of this type of adder. Gerald Rosenberger of IBM filed for a patent on a modern bary carry-look ahead adder From Wikipedia, the free encyclopedia: 10 Institute of Lifelong Learng, University of Delhi
11 Bary Arithmetic and Arithmetic Circuits Subtractor Trivia Half Subtractor: The circuit which will subtract two bits and produce a borrow and difference. Full Subtractor: The circuit which will subtract three bits and produce a borrow and difference Half Subtractor: The half subtractor needs two puts a muend and a subtrahend bit and output bits are borrow and difference. The logic symbol of the half subtractor is given figure 9. Input bits A B Borrow Difference Output bits The truth table of half subtractor is given as Figure 9: Logic symbol of Half subtractor A B Difference Borrow A & B are the put variables The Boolean expression for difference and borrow can be written as Difference AB AB A B Borrow AB Students are advised to design logic circuits usg the above Boolean expression and verify their diagram (see figure 10) 11 Institute of Lifelong Learng, University of Delhi
12 Bary Arithmetic and Arithmetic Circuits-2 Figure 10: Logic circuit for Half subtractor Half subtractor can be realized usg NAND gates only and is given figure 11 Figure 11: Logic circuit for Half subtractor usg NAND gates only Difference AAB BAB A AB B AB A A B BA B AB BA Borrow BAB BAB B A B AB 12 Institute of Lifelong Learng, University of Delhi
13 Bary Arithmetic and Arithmetic Circuits-2 Try Yourself Design half subtractor usg NOR gates only and obta Boolean expression for difference & borrow Difference A A B B A B A A B B A B A A B BA B AB AB Borrow A A B A( A B) AB Full Subtractor The half subtractor can be used only for LSB subtraction. If there is a borrow durg the subtraction of the LSBs, it affects the subtractions the next higher column; the subtrahend bit is subtracted from the muend bit, considerg the borrow from that column used for the subtraction the precedg column. Such a subtraction is performed by a full subtractor. It subtracts one bit (B) from another bit (A), when already there is a borrow B from the column for the subtraction the precedg column, and outputs the difference bit and the borrow bit required from the next column. The block diagram and the truth table of a full subtractor are shown below: A B B B out Difference Institute of Lifelong Learng, University of Delhi
14 Bary Arithmetic and Arithmetic Circuits B =Input Borrow B out =Borrow A, B & B are the put variables Input bits Input Borrow A Difference B B B out Borrow Output bits Figure 12: Logic symbol of Full Subtractor The difference and borrow for full subtractor are evaluated as: Difference ABB B B ABB AB AB B AB AB A BB A B A B B ABB ABB Borrow ABB AB ABB A B B ABB ABB The logic diagram of a full subtractor, usg two half subtractor is shown figure 12 Figure 12: Block diagram of Full subtractor usg two half subtractors 14 Institute of Lifelong Learng, University of Delhi
15 Bary Arithmetic and Arithmetic Circuits-2 The complete circuit diagram of Full subtractor is given figure 13. Figure 13: Complete circuit diagram of Full subtractor The full subtractor can also be realized Universal logic usg either only NAND gates and is shown figure 14. Figure 14: Complete circuit diagram of Full subtractor 2.6 Adder/Subtractor bit Parallel Adder/subtractor The 4-bit parallel Adder/Subtractor can perform the operation of addition and subtraction. The logic circuit is given Figure 15 The circuit is used for addition or subtraction of 4 bit puts A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. A B 8s 3 3 A B 2 2 4s A B 1 1 A B 0 0 2s 1s The circuit can either do addition or can do subtraction which is controlled by a control le, but both the operation can not be performed simultaneously. 15 Institute of Lifelong Learng, University of Delhi
16 Bary Arithmetic and Arithmetic Circuits-2 Figure 15: 4-bit parallel Adder/Subtractor The truth table for the operation can be summarized as Control A B Y When the control le is low i.e 0, then when a 0 is placed put A of the XOR gates, the bits pass through the XOR gate with no change. This can be verified from the truth table that when A is 0 the output is the same as that of the put present at the put B. With the control at 0, the puts available at the Full Adders (FA) are A 3 A 2 A 1 A 0, B 3 B 2 B 1 B 0 and C. The AND gate is disabled as one of the put is zero. Sce the output of the AND gate is zero 16 Institute of Lifelong Learng, University of Delhi
17 Bary Arithmetic and Arithmetic Circuits-2 so there is no end carry C put for FA (1s). Thus with the control at 0 the units add the bary number A 3 A 2 A 1 A 0 to B 3 B 2 B 1 B 0. The result appears at the output dicators. When the control bit is 1 position this causes the XOR gate to act as an verter for the B puts to the full adders. From the truth table it can be verified that when control is 1 position. The output is complement of B put. The 1 at the control bit also activates the AND gate so that the formation from the 8s Full adder can take the end around carry le back to the 1s full adder. This subtractor, subtracts the bary put number B 3 B 2 B 1 B 0 from A 3 A 2 A 1 A 0. With 2 s complement method. Takg an example as Decimal Subtraction Bary Subtraction With the control le at 1, the puts at FA as A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0. i.e. 1 s complement of put B 3 B 2 B 1 B 0 first take place. After 1 s complement of Muend and fally addg Muend and Subtrahend End around carry (difference) The difference appears bary form on the output dicators. 17 Institute of Lifelong Learng, University of Delhi
18 Bary Arithmetic and Arithmetic Circuits-2 Addg mache An addg mache was a class of mechanical calculator, usually specialized for bookkeepg calculations. In the United States, the earliest addg maches were usually built to read dollars and cents. Addg maches were ubiquitous office equipment until they were phased out favor of calculators the 1970s and by personal computers begng about The older addg maches were rarely seen American office settgs by the year Blaise Pascal and Wilhelm Schickard were the two origal ventors of the mechanical calculator 1642; For Pascal this was an addg mache that could perform additions and subtractions directly and multiplication and divisions by repetitions, whilst Schickard's mache, vented several decades earlier was less functionally efficient but was supported by a mechanized form of multiplication tables. These two were followed by a strg of ventors and ventions leadg to those of Thomas de Colmar who launched the mechanical calculator dustry 1851 when he released his simplified arithmometer (it took him thirty years to refe his mache, patented 1820, to a simpler and more reliable form). However, they didn't ga widespread use until Dorr E. Felt started manufacturg his comptometer (1887) and Burroughs started the commercialization of differently conceived addg maches (1892) Addg mache for the Australian pound c.1910, note the complement numberg, and the columns set up for shillgs and pence An addg mache Older addg mache. Its mechanism is similar to a car odometer Institute of Lifelong Learng, University of Delhi A manual addg mache manufactured the 1950s.
19 Bary Arithmetic and Arithmetic Circuits Summary Summary A combational circuit is one whose output at any time is determed from the present combation of puts with no storage or memory capability. The truth table for half adder is summarized as A B C out Sum The truth table for full adder is summarized as A B C C out Sum The truth table for half subtractor is summarized as A B Difference Borrow The truth table for full subtractor is summarized as A B B B out Difference Institute of Lifelong Learng, University of Delhi
20 Bary Arithmetic and Arithmetic Circuits-2 A 4-bit parallel Adder/Subtractor can be designed usg full adders only and can perform both addition and subtraction operation. 2.8 Exercises Subjective Questions 1) Draw the circuit diagram of Half Adder usg NAND gate only. Describe the operation performed by Half adder. 2) Draw a block diagram of a full adder labelg all the puts and outputs. Write the truth table for full adder. 3) Draw the circuit diagram of Half Subtractor usg NAND gate only. Describe its operation. 4) Draw a block diagram of a full Subtractor labelg all the puts and outputs. Write the truth table for full Subtractor. 5) Draw the Half Adder circuit usg two put NOR gate. 6) Draw the Full Adder circuit usg two put NOR gate. 7) Draw the Half Subtractor circuit usg two put NOR gate. 8) Draw the Half Subtractor circuit usg two put NOR gate. 9) Draw a logic circuit that has three puts A, B and C and whose output will be high only when majority puts are high Fill the blank 1) A half adder circuit is used for addg only the. (1s, 2s, 4s, 8s) column of a bary addition problem. 2) Adder circuits are widely used. Section of microprocessor. 3) The output of full adder is Σ = 1, C out =1 when the puts are.. 4) The put of the full subtractor is A=B=B =1 then the output is given as.. Answers to the questions: 1) 1s 2) Arithmetic logic unit (ALU) 3) 1,1,1 4) Difference = 1 & Borrow = Multiple Choice Questions 1) Full subtractor has. Inputs and. Outputs A) 2,3 B) 2, 2 20 Institute of Lifelong Learng, University of Delhi
21 Bary Arithmetic and Arithmetic Circuits-2 C) 3, 2 D) 3, 3 2) An Adder/Subtractor can perform A) only addition B) both addition and subtraction C) only subtraction D) only multiplication 3) The sum of a Full adder can be represented by A) 2 put X-OR gate B) 2 put NAND gate C) 3 put NAND gate D) 3 put X-OR gate 4) The control le should be kept. For performg subtraction usg 4 bit adder/subtractor A) 0 B)1 C) 11 D) 10 Answers to multiple choice questions 1) 3,2 Justification: Full Subtractor has 3 puts A, B, B and 2 outputs namely difference and Borrow output 2) Both addition and subtraction Justification: An Adder/Subtractor is designed to add two numbers as well as subtract two numbers usg 2 s complement method. 3) 3 put X-OR gate Justification: Sum = ABC 4) 1 Justification: With Control le at 1, the Adder/subtractor subtracts two number usg 2 s complement method. 21 Institute of Lifelong Learng, University of Delhi
22 Bary Arithmetic and Arithmetic Circuits Glossary Combational Logic Circuit A combational logic circuit is one whose output at any time is determed from the present combation of puts Half Adder A digital circuit that adds two bits and produces a sum and a carry. Full Adder A digital circuit which adds two bits and an put carry to produce a sum and an output carry Half Subtractor A digital circuit that subtracts two bits and produces difference and a borrow if any. Full Subtractor It subtracts one bit (B) from another bit (A), when already there is a borrow B from the column for the subtraction the precedg column, and outputs the difference bit and a borrow bit Reference Books: Digital Prciples & Applications, A.P.Malvo, D.P.Leach & Saha, 7th Ed., 2011, Tata McGraw Fundamentals of Digital Circuits, A. Anand Kumar, 2nd Edition, 2009, PHI Learng Pvt. Ltd. Digital Electronics, Prciples and applications, Roger L Tokheim, 2003, Tata McGraw Hill. Digital Systems: Prciples and Applications, R.J. Tocci, N.S.Widmer, 2001, PHI Learng. Digital Electronics, An troduction to theory and practice, W H Gothmann, 1982, PHI Learng. 22 Institute of Lifelong Learng, University of Delhi
UNIT-IV Combinational Logic
UNIT-IV Combinational Logic Introduction: The signals are usually represented by discrete bands of analog levels in digital electronic circuits or digital electronics instead of continuous ranges represented
More informationCOMBINATIONAL LOGIC CIRCUIT First Class. Dr. AMMAR ABDUL-HAMED KHADER
COMBINATIONAL LOGIC CIRCUIT First Class 1 BASIC ADDER Adders are important in computers and also in other types of digital system in which numerical data are processed. An understanding of the basic operation
More informationCombinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Combinational Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design 2 Combinational logic A combinational circuit
More informationUNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS
UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS STRUCTURE 2. Objectives 2. Introduction 2.2 Simplification of Boolean Expressions 2.2. Sum of Products 2.2.2 Product of Sums 2.2.3 Canonical
More informationUnit 3. Logic Design
EE 2: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Unit 3 Chapter Combinational 3 Combinational Logic Logic Design - Introduction to Analysis & Design
More informationExperiment # 3 Combinational Circuits (I) Binary Addition and Subtraction
Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor
More informationUNIT III. Designing Combinatorial Circuits. Adders
UNIT III Designing Combinatorial Circuits The design of a combinational circuit starts from the verbal outline of the problem and ends with a logic circuit diagram or a set of Boolean functions from which
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationModule 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits
1 Module-4 Design and Analysis of Combinational Circuits 4.1 Motivation: This topic develops the fundamental understanding and design of adder, substractor, code converter multiplexer, demultiplexer etc
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More informationSubtractor Logic Schematic
Function Of Xor Gate In Parallel Adder Subtractor Logic Schematic metic functions, including half adder, half subtractor, full adder, independent logic gates to form desired circuits based on dif- by integrating
More informationExperiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa
Experiment # 4 Binary Addition & Subtraction Eng. Waleed Y. Mousa 1. Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor circuits.
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure NAND-NAND & NOR-NOR Networks DeMorgan
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More informationDigital. Design. R. Ananda Natarajan B C D
Digital E A B C D 0 1 2 3 4 5 6 Design 7 8 9 10 11 12 13 14 15 Y R. Ananda Natarajan Digital Design Digital Design R. ANANDA NATARAJAN Professor Department of Electronics and Instrumentation Engineering
More informationChapter 1: Digital logic
Chapter 1: Digital logic I. Overview In PHYS 252, you learned the essentials of circuit analysis, including the concepts of impedance, amplification, feedback and frequency analysis. Most of the circuits
More informationNumber system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished
Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL SYSTEM DESIGN SEMESTER III SUBJECT CODE: EC UNIT : Design of Combinational Circuits PART -A ( Marks).
More informationTopic Notes: Digital Logic
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 20 Topic Notes: Digital Logic Our goal for the next couple of weeks is to gain a reasonably complete understanding of how
More informationCombinational Logic Circuits. Combinational Logic
Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The
More informationAdder (electronics) - Wikipedia, the free encyclopedia
Page 1 of 7 Adder (electronics) From Wikipedia, the free encyclopedia (Redirected from Full adder) In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers
More informationSubject: Analog and Digital Electronics Code:15CS32
Subject: Analog and Digital Electronics Code:15CS32 Syllabus: The Basic Gates : Review of Basic Logic gates, Positive and Negative Logic, Introduction to HDL. Combinational Logic Circuits:Sum-of-Products
More information(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification
More informationCombinational Circuits DC-IV (Part I) Notes
Combinational Circuits DC-IV (Part I) Notes Digital Circuits have been classified as: (a) Combinational Circuits: In these circuits output at any instant of time depends on inputs present at that instant
More informationLaboratory Manual CS (P) Digital Systems Lab
Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification
More informationDr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006
COE/EE2DI4 Midterm Test #1 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 Instructions: This examination paper includes 10 pages and 20 multiple-choice questions starting
More informationFunction Table of an Odd-Parity Generator Circuit
Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as
More informationCOMBINATIONAL CIRCUIT
Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits
More information2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
More informationOdd-Prime Number Detector The table of minterms is represented. Table 13.1
Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1
More informationAsst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)
2145230 Aircraft Electricity and Electronics Asst. Prof. Thavatchai Tayjasanant, PhD Email: taytaycu@gmail.com aycu@g a co Power System Research Lab 12 th Floor, Building 4 Tel: (02) 218-6527 1 Chapter
More informationCHAPTER 5 DESIGN OF COMBINATIONAL LOGIC CIRCUITS IN QCA
90 CHAPTER 5 DESIGN OF COMBINATIONAL LOGIC CIRCUITS IN QCA 5.1 INTRODUCTION A combinational circuit consists of logic gates whose outputs at any time are determined directly from the present combination
More informationGates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
More informationFUNCTION OF COMBINATIONAL LOGIC CIRCUIT
HAPTER FUNTION OF OMBINATIONAL LOGI IRUIT OUTLINE HALF-ADDER ANF FULL ADDER IRUIT -BIT PARALLEL BINARY RIPPLE ARRY ADDER -BIT PARALLEL BINARY ARRY LOOK- AHEAD ADDER BD ADDER IRUIT DEODER ENODER MULTIPLEXER
More informationTABLE 3-2 Truth Table for Code Converter Example
997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z 2 3 4 5 6 7 8 9 Truth
More informationCS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page
More informationLinear & Digital IC Applications (BRIDGE COURSE)
G. PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY Accredited by NAAC with A Grade of UGC, Approved by AICTE, New Delhi Permanently Affiliated to JNTUA, Ananthapuramu (Recognized by UGC under 2(f) and 12(B)
More informationEXPERIMENT NO 1 TRUTH TABLE (1)
EPERIMENT NO AIM: To verify the Demorgan s theorems. APPARATUS REQUIRED: THEORY: Digital logic trainer and Patch cords. The digital signals are discrete in nature and can only assume one of the two values
More informationLab Report: Digital Logic
Lab Report: Digital Logic Introduction The aim of the Digital Logic Lab was to construct a simple 4-bit Arithmetic Logic Unit (ALU) in order to demonstrate methods of using Boolean Algebra to manipulate
More informationDepartment of Electronics and Communication Engineering
Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 22 Representations of Combinatorial Logic Circuits Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 100 MPG Car contest!
More informationa b y UC Berkeley CS61C : Machine Structures Hello Helo,world!
CS61C L23 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 23 Representations of Combinatorial Logic Circuits 2006-10-20
More informationDEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING
DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING (Regulation 2013) EE 6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL 1 SYLLABUS OBJECTIVES: Working Practice in simulators / CAD Tools / Experiment
More informationUC Berkeley CS61C : Machine Structures
CS61C L22 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 22 Representations of Combinatorial Logic Circuits 27-3-9 TA David
More informationFan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationOn Built-In Self-Test for Adders
On Built-In Self-Test for s Mary D. Pulukuri and Charles E. Stroud Dept. of Electrical and Computer Engineering, Auburn University, Alabama Abstract - We evaluate some previously proposed test approaches
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING COMPUTER ARCHITECTURE AND ORGANIZATION (CSE18R174) LAB MANUAL Name of the Student:..... Register No Class Year/Sem/Class :. :. :... 1 This page is left intentionally
More informationNORTH MAHARASHTRA UNIVERSITY. F.Y. B. Sc. Electronics. Syllabus. Wieth effect from june2015
Syllabus Wieth effect from june2015 Paper- I, Semester I ELE-111: Analog Electronics I Unit- I:Introduction to Basic Circuit Components Definition and unit, Circuit Symbol, Working Principle, Classification
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitII 2. SKILLS ADDRESSED: Learning I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 Representations of Combinational Logic Circuits Senior Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Conway s Life
More informationLecture 2: Digital Logic Basis
Lecture 2: Digital Logic Basis Xufeng Kou School of Information Science and Technology ShanghaiTech University 1 Outline Truth Table Basic Logic Operation and Gates Logic Circuits NOR Gates and NAND Gates
More informationExercise 2: OR/NOR Logic Functions
Exercise 2: OR/NOR Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an OR and a NOR logic gate. You will verify your results by generating
More information0 A. Review. Lecture #16. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You!ll see them again in 150, 152 & 164
CS61C L15 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #16 Representations of Combinatorial Logic Circuits CPS today! 2005-10-26
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,
More informationIn this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions
In this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions Dr Pete Sedcole Department of E&E Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 3.1 3.6, 4.1) (Tocci 3.1 3.9)
More information4:Combinational logic circuits. 3 July
4:Combinational logic circuits 3 July 2014 1 overview What is combinational logic circuit? Examples of combinational logic circuits Binary-adder Binary-subtractor Binary-multiplier Decoders Multiplexers
More informationDIGITAL ELECTRONICS QUESTION BANK
DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure
More informationCHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT
CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression
More informationDigital Electronics Course Objectives
Digital Electronics Course Objectives In this course, we learning is reported using Standards Referenced Reporting (SRR). SRR seeks to provide students with grades that are consistent, are accurate, and
More informationLESSON PLAN. Sub Code & Name: ME2255 Electronics and Microprocessors Unit : I Branch : ME Semester: IV UNIT I SEMICONDUCTORS AND RECTIFIERS 9
Unit : I Branch : ME Semester: IV Page 01 of 06 UNIT I SEMICONDUCTORS AND RECTIFIERS 9 Classification of solids based on energy band theory - Intrinsic semiconductors - Extrinsic semiconductors - P type
More informationDESIGN OF 32-BIT ARITHMETIC LOGIC UNIT (ALU) USING VHDL Saif Abbas* 1, Bhavya Chaturvedi 1, Rituraj Akhauri 1, Rupali Singh 2
ISSN 2277-2685 IJESR/April 2018/ Vol-8/Issue-4/58-68 Saif Abbas et. al., / International Journal of Engineering & Science Research DESIGN OF 32-BIT ARITHMETIC LOGIC UNIT (ALU) USING VHDL Saif Abbas* 1,
More informationLogic Circuit Design
Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic
More informationB.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET. Course Outline
Course Outline B.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET The purpose of the course is to teach principles of digital electronics. This course covers varieties of topics including
More informationBinary Adder and Subtractor circuit
Digital circuit Experiment manual Experiment 9 inary dder and Subtractor circuit Part list. x. x. 8 x. x. 8 x Theory inary number addition n adder is a digital circuit that performs addition of numbers.
More informationGUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM. Course Title: Digital Electronics (Code: )
GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM Course Title: Digital Electronics (Code: 3322402) Diploma Programmes in which this course is offered Semester in which offered Power
More informationPractical Workbook Logic Design & Switching Theory
Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering
More informationBrought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.
Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector
More informationDELD UNIT 3. Question Option A Option B Option C Option D Correct Option A B C
Class : S.E.Comp Matoshri College of Engineering and Research Center Nasik Department of Computer Engineering Digital Elecronics and Logic Design (DELD) UNIT - III Subject : DELD Sr. No. Question Option
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More informationIndex terms: Gate Diffusion Input (GDI), Complementary Metal Oxide Semiconductor (CMOS), Digital Signal Processing (DSP).
GDI Based Design of Low Power Adders and Multipliers B.Shanmukhi Abstract: The multiplication and addition are the important operations in RISC Processor and DSP units. Specifically, speed and power efficient
More informationDhanalakshmi College of Engineering
Dhanalakshmi College of Engineering Manimangalam, Tambaram, Chennai 601 301 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY III SEMESTER -
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Adders
Introduction to Digital Logic Missouri S&T University CPE 22 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu
More informationDHANALAKSHMI COLLEGE OF ENGINEERING MANIMANGALAM. TAMBARAM, CHENNAI B.E. ELECTRICAL AND ELECTRONICS ENGINEERING III SEMESTER EE6311 Linear and Digital Integrated Circuits Laboratory LABORATORY MANUAL CLASS:
More informationEEE 301 Digital Electronics
EEE 301 Digital Electronics Lecture 1 Course Contents Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic logic functions, Boolean algebra,combinational logic
More informationGates and and Circuits
Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the
More informationAREA OPTIMIZED ARITHMETIC AND LOGIC UNIT USING LOW POWER 1-BIT FULL ADDER
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol. 3, Issue 3, Aug 2013, 115-120 TJPRC Pvt. Ltd. AREA OPTIMIZED ARITHMETIC
More informationB.Sc. ELECTRONICS 3 rd SEMESTER (CBCS) Courses of Study. B.Sc. ELECTRONICS 4 th (CBCS) Courses of Study
B.Sc. ELECTRONICS 3 rd SEMESTER (CBCS) Courses of Study SNo. Course Title Credits Code 1 UELTC301 DIGITAL ELECTRONICS 4 2 UELPC302 DIGITAL CIRCUIT LAB 2 3 UELTS303 RENEWABLE ENERGY AND ENERGY HARVESTING
More informationLOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.
LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two
More informationElectronics. Digital Electronics
Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital
More informationNORTH MAHARASHTRA UNIVERSITY, JALGAON
, JALGAON Syllabus for F.Y.B.Sc. Semester I and II ELECTRONICS (w. e. f. June 2012) F.Y. B. Sc. Subject Electronics Syllabus Structure Semester Code Title Number of Lectures ELE-111 Paper I : Analog Electronics
More informationExercise 1: AND/NAND Logic Functions
Exercise 1: AND/NAND Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an AND and a NAND logic gate. You will verify your results
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd Chapter 6 组合逻辑电路函数 Floyd, Digital Fundamentals, th ed 29 Pearson Education, Upper 28 Pearson Saddle River, Education NJ 7458. All Rights Reserved Summary Half-Adder
More informationWinter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28
Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationGovernment of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru
Prerequisites Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Course Title :Digital Electronics Lab I Course Code : 15EC2P Semester : II Course Group
More informationArea Delay Efficient Novel Adder By QCA Technology
Area Delay Efficient Novel Adder By QCA Technology 1 Mohammad Mahad, 2 Manisha Waje 1 Research Student, Department of ETC, G.H.Raisoni College of Engineering, Pune, India 2 Assistant Professor, Department
More informationSyllabus for: Electronics for F Y B Sc (Electronics) Semester- 1 (With effect from June 2014) PAPER I: Basic Electrical Circuits
Unit I: Passive Devices Syllabus for: Electronics for F Y B Sc (Electronics) Semester- 1 (With effect from June 2014) PAPER I: Basic Electrical Circuits Resistors, Fixed resistors & variable resistors,
More informationDigital Fundamentals. Lab 4 EX-OR Circuits & Combinational Circuit Design
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 4 EX-OR Circuits & Combinational Circuit Design
More informationFinal Project Report 4-bit ALU Design
ECE 467 Final Project Report 4-bit ALU Design Fall 2013 Kai Zhao Aswin Gonzalez Sepideh Roghanchi Soroush Khaleghi Part 1) Final ALU Design: There are 6 different functions implemented in this ALU: 1)
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering
More informationELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100
EC 40 MODEL TEST PAPER - 1 ELECTRONIC CIRCUITS Time: Three Hours Maximum Marks: 100 Answer five questions, taking ANY TWO from Group A, any two from Group B and all from Group C. All parts of a question
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationlogic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs
Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces
More informationDomino CMOS Implementation of Power Optimized and High Performance CLA adder
Domino CMOS Implementation of Power Optimized and High Performance CLA adder Kistipati Karthik Reddy 1, Jeeru Dinesh Reddy 2 1 PG Student, BMS College of Engineering, Bull temple Road, Bengaluru, India
More informationChapter 4: The Building Blocks: Binary Numbers, Boolean Logic, and Gates
Chapter 4: The Building Blocks: Binary Numbers, Boolean Logic, and Gates Objectives In this chapter, you will learn about The binary numbering system Boolean logic and gates Building computer circuits
More informationDESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR
e-issn 2455 1392 Volume 4 Issue 9, September 2018 pp. 9 16 Scientific Journal Impact Factor : 4.23 http://www.ijcter.com DESIGN OF MODIFIED AND UNERRING FOUR BIT BINARY SIGNED SUBTRACTOR Hemant Singh Bisht
More informationComparative Analysis of Various Adders using VHDL
International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-3, Issue-4, April 2015 Comparative Analysis of Various s using VHDL Komal M. Lineswala, Zalak M. Vyas Abstract
More informationPaper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor
Swami Ramanand Teerth Marathwada University, Nanded B. Sc. First Year Electronics Syllabus Semester system (To be implemented from Academic Year 2009-10) Name of the Theory marks Practical marks Periods
More informationWEEK 4.1. ECE124 Digital Circuits and Systems Page 1
WEEK 4.1 ECE124 Digital Circuits and Systems Page 1 Combina=onal circuits A combinatorial circuit is one that consists of logic gates with outputs that are determined en=rely by the present value of the
More information